lr/sc loop

[xusq123]

Since Spike doesn't have the concept of a cache, how can we simulate whether an LR/SC loop succeeds? For example, if multiple I-type instructions are executed directly in the LR/SC and then an SD is executed, should the LR/SC fail? Also, if other memory access instructions are executed in between, can Spike simulate these scenarios?

[chihminchao]

Spec allows the reservation state of lr could be released for some period. Spike is one of the implementations modeling that in this way. Each hart in spike could execute a specific steps(instructions) and yield to main loop to choose another hart. The state will be cleared at that time.