Run SystemVerilog-based Debug Module design using riscv-tests

[Thelittleelon]

Hi, can anyone tell me the steps to run this test for a Debug Module design that is written in SystemVerilog? I tried using Verilator to simulate my design, and then I write my own Python target files and also config files to run my design. The OpenOCD was successfully connected, but somehow the GDB always failed. I see that the PULP RISCV Debug, an open source design for a debug module, also uses this test to verify their design, but I just don't know how to do it. Can anyone describe all the steps in detail for me? I would be extremely grateful.