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I'm using riscv-tests with Chipyard and I failed to start a multi-thread program on a multi-core Chipyard config.
I noticed in the file benchmarks/common/crt.S, the startup code currently handles core entry as follows. This implementation puts all cores with mhartid>=1 into a deadloop and never calls the entry function for those cores.
# get core id
csrr a0, mhartid
# for now, assume only 1 core
li a1, 1
1:bgeu a0, a1, 1b
A straightforward way is to replace these lines with the following ones. And add a -DNUM_CORES=4 (according to actual core numbers) when compiling.
# get core id
csrr a0, mhartid
li a1, NUM_CORES
1:bgeu a0, a1, 1b
Would be great if riscv-tests provide a complete solution for multi-thread support.
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