Add a generator for RISC-V OpCode table in QEMU

**Is your feature request related to a problem? Please describe.**
QEMU currently maintains ~1,400 opcode entries by hand, keeping them in sync with the RISC-V ISA is error-prone.

**Describe the solution you'd like**
Add a backends generator to generate the op_code table present in the qemu/disas/riscv.c file in the QEMU project.

