feat(backends): add opcode-table generator for QEMU #1271
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- Implement a generator that generates insn32.decode for qemu. - Move load_full_instructions to generator.py so that other generators can use it. Resolves issue: riscv-software-src#1255
Implement a generator that emits rv_opcode_data entries straight from the Unified DB. Signed-off-by: Animesh Agarwal <[email protected]>
AnimeshAgarwal28
requested review from
ThinkOpenly and
dhower-qc
as code owners
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Summary:
This PR implements a generator that emits rv_opcode_data entries for QEMU from the Unified DB.
Usage:
This command emits rv_opcode_data that mirror the layout used in qemu/disas/riscv.c. Unsupported opcodes are listed at the end of the output.
Note:
This PR is stacked over #1258.