Add vector illegal instruction tests for reserved vtype settings (vsetvli/vsetvl/vsetivli)

[UmerShahidengr]

The current ACT test suite (Ssstrict) does not include tests that probe the behavior of vector configuration instructions (vsetvli, vsetvl, vsetivli) with reserved vtype field values.

The RISC-V V specification states that when a vset* instruction is given an unsupported or reserved vtype encoding, the implementation should set vtype.vill = 1 and vl = 0. However, Implementations could choose
to trap when illegal values are written to vtype instead of setting vill, to allow emulation to
support new configurations for forward-compatibility. Both behaviors may be considered legal depending on spec interpretation.

Blocking issue:

These tests cannot currently be enabled in CI because Sail (the reference model) traps with mcause=2 on reserved vtype, while DUTs (QEMU) set vill=1 without trapping. A Sail configuration parameter is needed first.

[dev-aditya-hub]

Quick spec-side note:

The V spec section on vtype encoding gives the canonical behavior for reserved/unsupported vtype writes as "the vill bit is set in vtype, the remaining bits in vtype are set to zero, and the vl register is also set to zero." The same chapter then notes that implementations may instead raise an illegal-instruction exception, positioned as the forward-compat path for emulating new configs. So QEMU's "set vill" matches the default and Sail's "trap with mcause=2" is the spec-permitted alternative, both are legal, they just need to be selectable per config.

The cleanest fix on the test side is probably a sail.json knob along these lines:

"reserved_vtype_behavior": "set_vill"   // default, matches QEMU / canonical
// or "trap"                            // matches current Sail

testgen can then pick the expected outcome per DUT, and the reserved-vtype Ssstrict tests can land in CI without forcing Sail to change its model. Happy to take the testgen side once the Sail knob exists, if that's useful.