Releases: riscv/riscv-cheri
Releases · riscv/riscv-cheri
v0.8.2-prerelease
Minor spec changes:
- Removed src1 != 0 constraint for cbld by @francislaus in #219
- make CBLD follow ACPERM rules by @tariqkurd-repo in #238
- Clarify CRE spec and note which instructions depend on it by @tariqkurd-repo in #223
- Fix exception codes, the invalid address exception was missing by @tariqkurd-repo in #241
Minor spec fixes and clarifications:
- Fix dscratch{0,1}c reset values by @AJoannou-Cap in #200
- Make CSRR{S|W} read CLEN bits by @andresag01 in #203
- Fix bit indices of envcfg registers by @PRugg-Cap in #208
- amoswap_32bit_cap: fix the amoswap.c mnemonics by @martin-kaiser in #210
- amo_32bit.adoc: fix the amo.[w|d] mnemonics by @martin-kaiser in #211
- Correct the length violation condition for cbo.clean & cbo.flush by @Timmmm in #216
- add note about PA handling, and add exception classes by @tariqkurd-repo in #226
- Clarify bit-slices in edge cases of the decoded bound figure by @PRugg-Cap in #228
- Fix typo in csrr pseudoinstruction by @mayyamal in #233
Notes
- Add note that INVAL is dangerous and should be FLUSH by @tariqkurd-repo in #221
Extension and mode renaming
- Make CHERI extension names legal by @andresag01 in #207
- rename legacy to hybrid by @tariqkurd-repo in #232
Typos, formatting, dead text removal, misc
- Makefile: (trivial) show which file is being generated by @martin-kaiser in #209
- Remove reset notice for debug CSRs without tag/metadata by @andresag01 in #202
- Chapter 1 minor revision by @marnovandermaas in #204
- keep tables together by @tariqkurd-repo in #206
- Remove unused prefetch exception text by @Timmmm in #214
- Minor revisions to anatomy chapter by @marnovandermaas in #215
- Remove out of place text in legacy ext by @andresag01 in #235
- Fix minor typos wording by @andresag01 in #237
- contributors and version number by @tariqkurd-repo in #239
- resolve problem with mode names by @tariqkurd-repo in #242
- bump version number, as v0.8.1 had a problem by @tariqkurd-repo in #243
New Contributors
- @AJoannou-Cap made their first contribution in #200
- @marnovandermaas made their first contribution in #204
- @martin-kaiser made their first contribution in #209
- @mayyamal made their first contribution in #233
Full Changelog: v0.8.0-prerelease...v0.8.2-prerelease
v0.8.0-prerelease
New or removed extensions
- Added thread identifier (TID) by @francislaus in #187
- Merge Zcheri_mode and Zcheri_legacy by @arichardson in #161
Capability encoding changes and fixes
- Fix minor nits in representable region section by @PRugg-Cap in #147
- Revert "Fix malformed check to avoid 65-bit top overflow" by @arichardson in #196
- Fix the auipcc reachability challenge by @PeterRugg in #116
- Permission transitions by @tariqkurd-repo in #175
- Define a new 32-bit permissions format by @arichardson in #155
- Fix malformed check to avoid 65-bit top overflow by @PRugg-Cap in #184
Specification changes
- Remove old text: PCC is no longer a CSR by @PRugg-Cap in #157
- Clarify that misaligned SC/LC except by @andresag01 in #125
- fix-issue-122: Add rules around programming CRE and CME bits, and variable XLEN by @tariqkurd-repo in #126
- fix C.MODESW encoding so it doesn't overlap C.SUBW by @tariqkurd-repo in #137
- Remove JALR.MODE by @arichardson in #167
- Change CSR/jump/branch invalid address handling by @andresag01 in #188
- Document minimum resources for Sdext operation by @sorear in #88
- Define AP field for Infinite on purecap and legacy exts by @andresag01 in #197
- Merge XLEN and CLEN CSR address space by @arichardson in #168
- change Zcmt checking to PCC bounds in legacy mode, and change JVTC reset value by @tariqkurd-repo in #178
- Remove the CHERI mode enable CSR bits by @arichardson in #174
Build or formatting
- Add IntelliJ editing plugin support by @arichardson in #120
- Add missing tag to CSR diagrams by @andresag01 in #129
- Tiny fixes 2 by @sorear in #131
- Fix broken variable resolution in title by @andresag01 in #172
- fix broken xref - build on main is broken by @tariqkurd-repo in #185
- reorder capability chapter to show cap layout first by @axel-h in #23
Other changes, clarifications, fixes, etc
- Redundant pcc unseal text by @tariqkurd-repo in #124
- add ASR permission and target out of bounds exception priority by @tariqkurd-repo in #128
- Update CTestSubset mnemonic by @Timmmm in #135
- Invert subset/superset for CBLD by @Timmmm in #136
- Mnemonic fixes by @PRugg-Cap in #146
- C.SC and C.SCSP imm should be 64-bit aligned (RV32) by @James-Williams in #150
- MODESW, CBO.* - Specify all bits of funct5 fields by @James-Williams in #152
- Fix CSR menmonic operand order in specification by @veselypeta in #148
- Indicate tag value for NULL and Infinite caps by @andresag01 in #153
- Fix various Zba bugs by @PRugg-Cap in #160
- Indicate that GPRs have tag cleared on reset by @andresag01 in #170
- encoding fixes by @tariqkurd-repo in #177
- Add table with exception priority with triggers by @andresag01 in #171
- Remove XLENMAX by @sorear in #123
- make SH4ADD/SH4ADD.UW RV64 only by @tariqkurd-repo in #181
- Add some missed RV64 prerequisites by @PRugg-Cap in #183
- Clarify that cbld cd.tag=0 if checks fail by @andresag01 in #189
- Clarify non-user mode CSRs in CSR insns listing by @andresag01 in #192
- Fix typo in SCADDR listings by @andresag01 in #194
- Fix typos in instruction listings by @andresag01 in #195
New Contributors
- @PRugg-Cap made their first contribution in #146
- @James-Williams made their first contribution in #150
Full Changelog: v0.7.1-prelease...v0.8.0-prerelease
v0.7.1-prelease
What's Changed - Spec Changes, fixes and clarifications:
- Removed that prefetch instructions can throw exceptions by @francislaus in #7
- Added exceptions to compressed jump instructions by @francislaus in #26
- [RISCV-CHERI] Fix description of CSetMode by @veselypeta in #27
- correct prerequisite rules by @tariqkurd-repo in #35
- correct shift and add operands by @tariqkurd-repo in #33
- fixed prerequisite rules for 16-bit fp dp load/store by @tariqkurd-repo in #45
- Make permission bit order consistent by @Timmmm in #36
- Specify value of mode bit in null/infinite caps by @Timmmm in #19
- Fix issue 42 (XLEN-bit results of CSR instructions must be sign extended to XLENMAX ) by @tariqkurd-repo in #49
- Fix issue 42 (XLEN-bit results of CSR instructions must be sign extended to XLENMAX ) by @tariqkurd-repo in #46
- clarify PCC bounds after zcmt instruction by @tariqkurd-repo in #76
- Clarify CJALR operation order by @Timmmm in #10
- Misaligned LC/SC is a fatal error by @sorear in #66
- Cbuildcap and ctestsubset do not use DDC by @francislaus in #82
- Csealentry changes by @tariqkurd-repo in #105
- Added note to cbuildcap and reserved cs1 == 0 by @francislaus in #103
- replace null-cap CSR reset values with a tag clear (fixes issue 43) by @tariqkurd-repo in #101
- Fix issue 90 (debug mode spec) by @tariqkurd-repo in #113
- Clarify that sealing check is not needed on pcc by @andresag01 in #112
- Allow CSRRS/C to read CLEN-wide values by @andresag01 in #108
- Clarify csrr[s|c]i write behavior when imm=0 by @andresag01 in #117
- capability mode enables and register access controls for Zcheri_legacy by @sorear in #81
- Capabilities are little endian by @sorear in #119
- Document that DDC/DDDC are address pointers and can be compressed by @andresag01 in #98
- Specify behaviour for reserved permission encoding by @Timmmm in #53
- Clarify difference in IE between current spec and CHERI v9 by @andresag01 in #97
Mnemonic renaming
- remove C prefix from capability mode load/store/atomics by @tariqkurd-repo in #87
- rename CSHxADD opcodes to SHxADD by @tariqkurd-repo in #95
- Rename cheri insns by @tariqkurd-repo in #109
- Rename AUIPCC, CJ* and fix some other minor documentation issues by @tariqkurd-repo in #104
Generation or formatting
- Support building HTML output by @Timmmm in #12
- Minor fixes and formatting changes by @PeterRugg in #11
- improve wording by @axel-h in #24
- Deploy to Github pages on release by @Timmmm in #21
- representable range description, and some other minor clarifications by @tariqkurd-repo in #22
- Remove sole reference to embedded exponent by @Timmmm in #38
- improve wording about about tag by @axel-h in #61
- Sync with template repository to add pre-commit checks and CI by @arichardson in #68
- Don't override VERSION and REVMARK for default actions builds by @arichardson in #73
- Section with Special Capabilities by @axel-h in #62
- Add newline between includes to fix chapter headers by @andresag01 in #75
- Add a link to the latest spec to the README by @arichardson in #78
- Merge from templates repo by @arichardson in #79
- Minor fixes by @sorear in #54
- Deploy GitHub pages on every commit to main by @arichardson in #89
- fix destination type for sc.c by @tariqkurd-repo in #102
- PCC does not grant store permission before PTE checks by @andresag01 in #111
New Contributors
- @francislaus made their first contribution in #7
- @Timmmm made their first contribution in #12
- @PeterRugg made their first contribution in #11
- @axel-h made their first contribution in #24
- @veselypeta made their first contribution in #27
- @tariqkurd-repo made their first contribution in #35
- @arichardson made their first contribution in #68
- @sorear made their first contribution in #66
Full Changelog: v0.0.1-prerelease...v0.7.1
Release 0.0.1-prerelease
v0.0.1-prerelease Add draft specification proposal from Codasip (#2)