Replaced all latexmath calls with built-in AsciiDoc substitutes. Done to make normative rule extraction provide better results (i.e., rules without images, just normal characters). (#2411)

Signed-off-by: James Ball <[email protected]>
Co-authored-by: James Ball <[email protected]>

Author: aswaterman

src/bfloat16.adoc

@@ -219,10 +219,10 @@ as well as in the `frm` CSR
 [cols = "1,1,1"]
 |===
 |Rounding Mode | Mnemonic | Meaning
-|000 | RNE | Round to Nearest, ties to Even
-|001 | RTZ | Round towards Zero
-|010 | RDN | Round Down (towards −∞)
-|011 | RUP | Round Up (towards +∞)
+| 000 | RNE | Round to Nearest, ties to Even
+| 001 | RTZ | Round towards Zero
+| 010 | RDN | Round Down (towards −{inf})
+| 011 | RUP | Round Up (towards +{inf})
 |100 | RMM | Round to Nearest, ties to Max Magnitude
 |===
 

src/colophon.adoc

@@ -361,9 +361,9 @@ instructions, which had suggested the incorrect sign of a zero result.
 * Instructions `FMV.S.X` and `FMV.X.S` were renamed to `FMV.W.X` and `FMV.X.W`
 respectively to be more consistent with their semantics, which did not
 change. The old names will continue to be supported in the tools.
-* Specified behavior of narrower (latexmath:[$<$]FLEN) floating-point
+* Specified behavior of narrower (<FLEN) floating-point
 values held in wider `f` registers using NaN-boxing model.
-* Defined the exception behavior of FMA(latexmath:[$\infty$], 0, qNaN).
+* Defined the exception behavior of FMA({inf}, 0, qNaN).
 * Added note indicating that the `P` extension might be reworked into an
 integer packed-SIMD proposal for fixed-point operations using the
 integer registers.
@@ -385,7 +385,7 @@ software conventions.
 
 * Numerous additions and improvements to the commentary sections.
 * Separate version numbers for each chapter.
-* Modification to long instruction encodings latexmath:[$>$]64 bits to
+* Modification to long instruction encodings >64 bits to
 avoid moving the _rd_ specifier in very long instruction formats.
 * CSR instructions are now described in the base integer format where
 the counter registers are introduced, as opposed to only being
@@ -456,7 +456,7 @@ added.
 64-bits wide, with separate read access to the upper and lower 32 bits.
 * Canonical `NOP` and `MV` encodings have been defined.
 * Standard instruction-length encodings have been defined for 48-bit,
-64-bit, and latexmath:[$>$]64-bit instructions.
+64-bit, and >64-bit instructions.
 * Description of a 128-bit address space variant, `RV128`, has been added.
 * Major opcodes in the 32-bit base instruction format have been
 allocated for user-defined custom extensions.

src/f-st-ext.adoc

@@ -127,8 +127,8 @@ particular, with regard to decoding legal vs. reserved encodings).
 |Rounding Mode |Mnemonic |Meaning
 |000 |RNE |Round to Nearest, ties to Even
 |001 |RTZ |Round towards Zero
-|010 |RDN |Round Down (towards latexmath:[$-\infty$])
-|011 |RUP |Round Up (towards latexmath:[$+\infty$])
+|010 |RDN |Round Down (towards −{inf})
+|011 |RUP |Round Up (towards +{inf})
 |100 |RMM |Round to Nearest, ties to Max Magnitude
 |101 | |_Reserved for future use._
 |110 | |_Reserved for future use._
@@ -270,8 +270,8 @@ rounding mode using the _rm_ field with the encoding shown in
 <<rm>>.
 
 Floating-point minimum-number and maximum-number instructions FMIN.S and FMAX.S write, respectively, the smaller or larger of _rs1_ and _rs2_ to _rd_. For the purposes of these instructions only, the value
-latexmath:[$-0.0$] is considered to be less than the value
-latexmath:[$+0.0$]. If both inputs are NaNs, the result is the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand.
+−0.0 is considered to be less than the value
++0.0. If both inputs are NaNs, the result is the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand.
 Signaling NaN inputs set the invalid operation exception flag, even when the result is not NaN.
 
 [NOTE]
@@ -293,14 +293,14 @@ instruction format. R4-type instructions specify three source registers (_rs1_,
 
 FMADD.S multiplies the values in _rs1_ and _rs2_, adds the value in
 _rs3_, and writes the final result to _rd_. FMADD.S computes
-_(rs1latexmath:[$\times$]rs2)latexmath:[$\+$]rs3_.
+_(rs1×rs2)+rs3_.
 
 FMSUB.S multiplies the values in _rs1_ and _rs2_, subtracts the value in _rs3_, and writes the final result to _rd_. FMSUB.S computes
-_(rs1latexmath:[$\times$]rs2)latexmath:[$\-$]rs3_.
+_(rs1×rs2)−rs3_.
 
-FNMSUB.S multiplies the values in _rs1_ and _rs2_, negates the product, adds the value in _rs3_, and writes the final result to _rd_. FNMSUB.S computes _-(rs1latexmath:[$\times$]rs2)latexmath:[$\+$]rs3_.
+FNMSUB.S multiplies the values in _rs1_ and _rs2_, negates the product, adds the value in _rs3_, and writes the final result to _rd_. FNMSUB.S computes _−(rs1×rs2)+rs3_.
 
-FNMADD.S multiplies the values in _rs1_ and _rs2_, negates the product, subtracts the value in _rs3_, and writes the final result to _rd_. FNMADD.S computes _-(rs1latexmath:[$\times$]rs2)latexmath:[$\-$]rs3_.
+FNMADD.S multiplies the values in _rs1_ and _rs2_, negates the product, subtracts the value in _rs3_, and writes the final result to _rd_. FNMADD.S computes _−(rs1×rs2)−rs3_.
 
 [NOTE]
 ====
@@ -331,12 +331,12 @@ would require additional move instructions in some common sequences. The current
 ====
 
 The fused multiply-add instructions must set the invalid operation
-exception flag when the multiplicands are latexmath:[$\infty$] and zero, even when the addend is a quiet NaN.
+exception flag when the multiplicands are {inf} and zero, even when the addend is a quiet NaN.
 
 [NOTE]
 ====
 The IEEE 754-2008 standard permits, but does not require, raising the
-invalid exception for the operation latexmath:[$\infty\times 0\ +$]qNaN.
+invalid exception for the operation {inf}×0 + qNaN.
 ====
 
 === Single-Precision Floating-Point Conversion and Move Instructions
@@ -349,7 +349,7 @@ register _rd_. FCVT.S.W or FCVT.S.L converts a 32-bit or 64-bit signed
 integer, respectively, in integer register _rs1_ into a floating-point
 number in floating-point register _rd_. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU,
 and FCVT.S.LU variants convert to or from unsigned integer values. For
-XLENlatexmath:[$>32$], FCVT.W[U].S sign-extends the 32-bit result to the
+XLEN>32, FCVT.W[U].S sign-extends the 32-bit result to the
 destination register width. FCVT.L[U].S and FCVT.S.L[U] are RV64-only
 instructions. If the rounded result is not representable in the
 destination format, it is clipped to the nearest value and the invalid
@@ -367,23 +367,23 @@ FCVT.S.W _rd_, `x0`, which will never set any exception flags.
 [%autowidth,float="center",align="center",cols="<,>,>,>,>",options="header",]
 |===
 | |FCVT.W.S |FCVT.WU.S |FCVT.L.S |FCVT.LU.S
-|Minimum valid input (after rounding) |latexmath:[$-2^{31}$] |0
-|latexmath:[$-2^{63}$] |0
+|Minimum valid input (after rounding) |−2^31^ |0
+|−2^63^ |0
 
-|Maximum valid input (after rounding) |latexmath:[$2^{31}-1$]
-|latexmath:[$2^{32}-1$] |latexmath:[$2^{63}-1$] |latexmath:[$2^{64}-1$]
+|Maximum valid input (after rounding) |2^31^−1
+|2^32^−1 |2^63^−1 |2^64^−1
 
-|Output for out-of-range negative input |latexmath:[$-2^{31}$] |0
-|latexmath:[$-2^{63}$] |0
+|Output for out-of-range negative input |−2^31^ |0
+|−2^63^ |0
 
-|Output for latexmath:[$-\infty$] |latexmath:[$-2^{31}$] |0
-|latexmath:[$-2^{63}$] |0
+|Output for -{inf} |−2^31^ |0
+|−2^63^ |0
 
-|Output for out-of-range positive input |latexmath:[$2^{31}-1$]
-|latexmath:[$2^{32}-1$] |latexmath:[$2^{63}-1$] |latexmath:[$2^{64}-1$]
+|Output for out-of-range positive input |2^31^−1
+|2^32^−1 |2^63^−1 |2^64^−1
 
-|Output for latexmath:[$+\infty$] or NaN |latexmath:[$2^{31}-1$]
-|latexmath:[$2^{32}-1$] |latexmath:[$2^{63}-1$] |latexmath:[$2^{64}-1$]
+|Output for +{inf} or NaN |2^31^−1
+|2^32^−1 |2^63^−1 |2^64^−1
 |===
 
 All floating-point conversion instructions set the Inexact exception
@@ -444,10 +444,8 @@ representing integer values in the floating-point registers by defining conversi
 
 Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the
 specified comparison between floating-point registers
-(latexmath:[$\mbox{\em rs1}
-= \mbox{\em rs2}$], latexmath:[$\mbox{\em rs1} < \mbox{\em rs2}$],
-latexmath:[$\mbox{\em rs1} \leq
-\mbox{\em rs2}$]) writing 1 to the integer register _rd_ if the
+(_rs1_ = _rs2_, _rs1_ < _rs2_,
+_rs1_ {le} _rs2_) writing 1 to the integer register _rd_ if the
 condition holds, and 0 otherwise.
 
 FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as
@@ -461,9 +459,9 @@ include::images/wavedrom/spfloat-comp.edn[]
 
 [NOTE]
 ====
-The F extension provides a latexmath:[$\leq$] comparison, whereas the
-base ISAs provide a latexmath:[$\geq$] branch comparison. Because
-latexmath:[$\leq$] can be synthesized from latexmath:[$\geq$] and
+The F extension provides a {le} comparison, whereas the
+base ISAs provide a {ge} branch comparison. Because
+{le} can be synthesized from {ge} and
 vice-versa, there is no performance implication to this inconsistency,
 but it is nevertheless an unfortunate incongruity in the ISA.
 ====
@@ -488,14 +486,14 @@ include::images/wavedrom/spfloat-classify.edn[]
 [%autowidth,float="center",align="center",cols="^,<",options="header",]
 |===
 |_rd_ bit |Meaning
-|0 |_rs1_ is latexmath:[$-\infty$].
+|0 |_rs1_ is −{inf}.
 |1 |_rs1_ is a negative normal number.
 |2 |_rs1_ is a negative subnormal number.
-|3 |_rs1_ is latexmath:[$-0$].
-|4 |_rs1_ is latexmath:[$+0$].
+|3 |_rs1_ is −0.
+|4 |_rs1_ is +0.
 |5 |_rs1_ is a positive subnormal number.
 |6 |_rs1_ is a positive normal number.
-|7 |_rs1_ is latexmath:[$+\infty$].
+|7 |_rs1_ is +{inf}.
 |8 |_rs1_ is a signaling NaN.
 |9 |_rs1_ is a quiet NaN.
 |===

src/hypervisor.adoc

@@ -729,7 +729,7 @@ counters to the guest virtual machine.
 .Hypervisor counter-enable register (`hcounteren`).
 include::images/bytefield/hcounterenreg.edn[]
 
-When the CY, TM, IR, or HPM_n_ bit in the `hcounteren` register is
+When the CY, TM, IR, or HPM__n__ bit in the `hcounteren` register is
 clear, attempts to read the `cycle`, `time`, `instret`, or
 `hpmcounter` _n_ register while V=1 will cause a virtual-instruction
 exception if the same bit in `mcounteren` is 1. When one of these bits

src/intro.adoc

@@ -355,13 +355,13 @@ regardless of any subsequent extensions.
 
 
 A RISC-V hart has a single byte-addressable address space of
-latexmath:[$2^{\text{XLEN}}$] bytes for all memory accesses. A _word_ of
+2^XLEN^ bytes for all memory accesses. A _word_ of
 memory is defined as 32{nbsp}bits (4{nbsp}bytes). Correspondingly, a _halfword_ is 16{nbsp}bits (2{nbsp}bytes), a
 _doubleword_ is 64{nbsp}bits (8{nbsp}bytes), and a _quadword_ is 128{nbsp}bits (16{nbsp}bytes). The memory address space is
-circular, so that the byte at address latexmath:[$2^{\text{XLEN}}-1$] is
+circular, so that the byte at address 2^XLEN^−1 is
 adjacent to the byte at address zero. Accordingly, memory address
 computations done by the hardware ignore overflow and instead wrap
-around modulo latexmath:[$2^{\text{XLEN}}$].
+around modulo 2^XLEN^.
 
 The execution environment determines the mapping of hardware resources
 into a hart's address space. Different address ranges of a hart's

src/m-st-ext.adoc

@@ -66,8 +66,7 @@ the sign of a nonzero result equals the sign of the dividend.#
 [NOTE]
 ====
 For both signed and unsigned division, except in the case of overflow, it holds
-that
-latexmath:[$\textrm{dividend} = \textrm{divisor} \times \textrm{quotient} + \textrm{remainder}$].
+that dividend = divisor {times} quotient + remainder.
 ====
 
 If both the quotient and remainder are required from the same division,
@@ -89,7 +88,7 @@ The semantics for division by zero and division overflow are summarized
 in <<divby0>>. [#norm:div_by_zero]#The quotient of division by zero has all bits
 set#, and [#norm:rem_by_zero]#the remainder of division by zero equals the dividend.#
 [#norm:signed_div_overflow]#Signed division overflow occurs only when the most-negative integer is divided
-by latexmath:[$-1$]. The quotient of a signed division with overflow is
+by −1. The quotient of a signed division with overflow is
 equal to the dividend, and the remainder is zero.# Unsigned division
 overflow cannot occur.
 
@@ -100,17 +99,17 @@ overflow cannot occur.
 |Condition |Dividend |Divisor |DIVU[W] |REMU[W] |DIV[W] |REM[W]
 
 |Division by zero +
-Overflow (signed only) |latexmath:[$x$] +
-latexmath:[$-2^{L-1}$] |0 +
-latexmath:[$-1$] |latexmath:[$2^{L}-1$] +
- - |latexmath:[$x$] +
- - |latexmath:[$-1$] +
- latexmath:[$-2^{L-1}$] +
-  |latexmath:[$x$] +
+Overflow (signed only) |_x_ +
+-2^L-1^ |0 +
+−1 |2^L^-1 +
+ - |_x_ +
+ - |−1 +
+ -2^L-1^ +
+  |_x_ +
   0
 |===
 
-//|Overflow (signed only) |latexmath:[$-2^{L-1}$] |latexmath:[$-1$] |– |– |latexmath:[$-2^{L-1}$] |0
+//|Overflow (signed only) |−2^L−1^ |−1 |– |– |−2^L−1^ |0
 //|===
 
 [NOTE]

src/machine.adoc

@@ -456,7 +456,7 @@ S-mode respectively. When executing an __x__RET instruction, supposing
 __x__PP holds the value _y_, __x__IE is set to __x__PIE; the privilege mode is
 changed to _y_; __x__PIE is set to 1; and __x__PP is set to the
 least-privileged supported mode (U if U-mode is implemented, else M). If
-__y__≠M, __x__RET also sets MPRV=0.
+__y__{ne}M, __x__RET also sets MPRV=0.
 
 [NOTE]
 ====
@@ -1626,7 +1626,7 @@ of this register.
 
 When the CY, IR, or HPM__n__ bit in the `mcountinhibit` register is clear,
 the `mcycle`, `minstret`, or `mhpmcountern` register increments as usual.
-When the CY, IR, or HPM_n_ bit is set, the corresponding counter does
+When the CY, IR, or HPM__n__ bit is set, the corresponding counter does
 not increment.
 
 The `mcycle` CSR may be shared between harts on the same core, in which
@@ -2101,7 +2101,7 @@ include::images/bytefield/mconfigptrreg.edn[]
 
 The pointer alignment in bits must be no smaller than MXLEN:
 i.e., if MXLEN is
-latexmath:[$8\times n$], then `mconfigptr`[latexmath:[$\log_2n$]-1:0]
+8{times}__n__, then `mconfigptr`[log~2n~-1:0]
 must be zero.
 
 The `mconfigptr` register must be implemented, but it may be zero to indicate the
@@ -3225,20 +3225,19 @@ If  `pmpaddr~i-1~≥``pmpaddr~i~``` and `pmpcfg~i~.A`=TOR, then PMP entry _i
 
 Although the PMP mechanism supports regions as small as four bytes,
 platforms may specify coarser PMP regions. In general, the PMP grain is
-latexmath:[$2^{G+2}$] bytes and must be the same across all PMP regions.
-When latexmath:[$G \geq 1$], the NA4 mode is not selectable. When
-latexmath:[$G \geq 2$] and latexmath:[${\tt pmpcfg}_i$].A[1] is set,
-i.e. the mode is NAPOT, then bits latexmath:[${\tt pmpaddr}_i$][G-2:0]
-read as all ones. When latexmath:[$G \geq 1$] and
-latexmath:[${\tt pmpcfg}_i$].A[1] is clear, i.e. the mode is OFF or TOR,
-then bits latexmath:[${\tt pmpaddr}_i$][G-1:0] read as all zeros. Bits
-latexmath:[${\tt
-pmpaddr}_i$][G-1:0] do not affect the TOR address-matching logic.
-Although changing latexmath:[${\tt pmpcfg}_i$].A[1] affects the value
-read from latexmath:[${\tt pmpaddr}_i$], it does not affect the
+2^G+2^ bytes and must be the same across all PMP regions.
+When G {ge} 1, the NA4 mode is not selectable. When
+G {ge} 2 and pmpcfg~i~.A[1] is set,
+i.e. the mode is NAPOT, then bits pmpaddr~i~[G-2:0]
+read as all ones. When G {ge} 1 and
+pmpcfg~i~.A[1] is clear, i.e. the mode is OFF or TOR,
+then bits pmpaddr~i~[G-1:0] read as all zeros. Bits
+pmpaddr~i~[G-1:0] do not affect the TOR address-matching logic.
+Although changing pmpcfg~i~.A[1] affects the value
+read from pmpaddr~i~, it does not affect the
 underlying value stored in that register—in particular,
-latexmath:[${\tt pmpaddr}_i$][G-1] retains its original value when
-latexmath:[${\tt pmpcfg}_i$].A is changed from NAPOT to TOR/OFF then
+pmpaddr~i~[G-1] retains its original value when
+pmpcfg~i~.A is changed from NAPOT to TOR/OFF then
 back to NAPOT.
 
 [NOTE]