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Connect unprivileged to privileged references
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src/unpriv/cfi.adoc

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@@ -64,8 +64,9 @@ provide backward-edge and forward-edge CFI respectively.
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The Unprivileged ISA for ext:zicfilp[] extension is specified in <<ext:zicfilp>>
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and for the Unprivileged ISA for ext:zicfiss[] extension is specified in
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<<ext:zicfiss>>. The Privileged ISA for these extensions is specified in the
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Privileged ISA specification.
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<<ext:zicfiss>>. The Privileged ISA for ext:zicfilp[] extension is specified in
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<<priv-forward>> and for the Privileged ISA for ext:zicfiss[] extension is
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specified in <<priv-backward>>.
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[[ext:zicfilp]]
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==== ext:zicfilp[] for Landing Pad

src/unpriv/mm-explanatory.adoc

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@@ -1101,9 +1101,8 @@ RVWMO does not currently attempt to formally describe how FENCE.I,
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SFENCE.VMA, I/O fences, and PMAs behave. All of these behaviors will be
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described by future formalizations. In the meantime, the behavior of
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insn:fence.i[] is described in extlink:zifencei[], the
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behavior of SFENCE.VMA is described in the RISC-V Instruction Set
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Privileged Architecture Manual, and the behavior of I/O fences and the
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effects of PMAs are described below.
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behavior of SFENCE.VMA is described in <<sfence.vma>>, and the behavior
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of I/O fences and the effects of PMAs are described below.
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===== Coherence and Cacheability
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src/unpriv/zk.adoc

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===== Access Control to csr:seed[]
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The ext:zkr[] extension adds the csr::[sseed] and csr::[useed] fields to the csr:mseccfg[] CSR to
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control access to the csr:seed[] CSR from U, S, or HS modes (see Privileged ISA
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specification).
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control access to the csr:seed[] CSR from U, S, or HS modes (see <<sec:mseccfg>>).
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Systems should implement carefully considered access control policies from
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lower privilege modes to physical entropy sources. The system can trap

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