instruction-fetch exception write *tval CSR need to follow pointer masking rule？ #2423
Description
Spec say：
When pointer masking is enabled, the ignore transformation will be applied to every explicit memory
access (e.g., loads/stores, atomics operations, and floating point loads/stores). The transformation
does not apply to implicit accesses such as page-table walks or instruction fetches. The set of
accesses that pointer masking applies to is described in Section 24.2.6.
Spec say：
For example, software is free to write a tagged or untagged address to stvec, but on trap delivery (e.g.,
due to an exception or interrupt), pointer masking will not be applied to the address of the trap
handler. However, pointer masking will be applied by the hardware to any address written into stval
when delivering an exception.
Q. i want to confirm that instruction-fetch exception （e.g., instruction page fault）write *tval CSR need to follow pointer masking rule？