From fb836d194ad551f9b6edf2eb2f25e2083f0ae6af Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 25 Nov 2025 13:47:12 -0800 Subject: [PATCH] Fix non-normative description of RV32V_Zdinx EEW=64 FP operands are supplied by register pairs. --- src/v-st-ext.adoc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/v-st-ext.adoc b/src/v-st-ext.adoc index b7e8a138d..c25570b7f 100644 --- a/src/v-st-ext.adoc +++ b/src/v-st-ext.adoc @@ -2242,10 +2242,10 @@ by naming the immediate `uimm` in the assembly syntax. NOTE: When adding a vector extension to the Zfinx/Zdinx/Zhinx extensions, floating-point scalar arguments are taken from the `x` -registers. NaN-boxing is not supported in these extensions, and so -the vector floating-point scalar value is produced using the same -rules as for an integer scalar operand (i.e., when XLEN > SEW use the -lowest SEW bits, when XLEN < SEW use the sign-extended value). +registers. +NaN-boxing is not supported in these extensions, and so operands narrower +than XLEN bits are not checked for a NaN box; bits XLEN-1:EEW are ignored. +For RV32_Zdinx, EEW=64 scalar arguments are supplied by an `x`-register pair. Vector arithmetic instructions are masked under control of the `vm` field.