Release riscv-isa-release-4d1303b-2025-12-27

This release was created by: wmat
Release of RISC-V ISA, built from commit 4d1303b, is now available.

What's Changed

• Bump actions/upload-artifact from 4 to 6 by @dependabot[bot] in #2533

Full Changelog: riscv-isa-release-b62fe14-2025-12-27...riscv-isa-release-4d1303b-2025-12-27

Release riscv-isa-release-bd49f88-2025-12-25

This release was created by: aswaterman
Release of RISC-V ISA, built from commit bd49f88, is now available.

What's Changed

• Clarify ill-configured counters by @ved-rivos in #2539

Full Changelog: riscv-isa-release-117c442-2025-12-25...riscv-isa-release-bd49f88-2025-12-25

Release riscv-isa-release-117c442-2025-12-25

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 117c442, is now available.

What's Changed

• Fix bitmanip extensions integration by @ved-rivos in #2538

Full Changelog: riscv-isa-release-851c681-2025-12-24...riscv-isa-release-117c442-2025-12-25

Release riscv-isa-release-ad48ae8-2025-12-24

This release was created by: aswaterman
Release of RISC-V ISA, built from commit ad48ae8, is now available.

What's Changed

• Adding Zalasr to the main spec by @mehnadnerd in #2091
• Fix bit-width for RoundKeyB in vaeskf2.vi Sail pseudocode by @GH4169 in #2487

New Contributors

• @mehnadnerd made their first contribution in #2091

Full Changelog: riscv-isa-release-7f956f7-2025-12-23...riscv-isa-release-ad48ae8-2025-12-24

Release riscv-isa-release-851c681-2025-12-24

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 851c681, is now available.

What's Changed

• Adding Zalasr to the main spec by @mehnadnerd in #2091
• Fix bit-width for RoundKeyB in vaeskf2.vi Sail pseudocode by @GH4169 in #2487

New Contributors

• @mehnadnerd made their first contribution in #2091

Full Changelog: riscv-isa-release-7f956f7-2025-12-23...riscv-isa-release-851c681-2025-12-24

Release riscv-isa-release-7f956f7-2025-12-23

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 7f956f7, is now available.

What's Changed

• Fix a typo in operation of vsha2c[hl].vv instruction by @cebarobot in #2536

Full Changelog: riscv-isa-release-1d89943-2025-12-23...riscv-isa-release-7f956f7-2025-12-23

Release riscv-isa-release-5c823ad-2025-12-23

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 5c823ad, is now available.

What's Changed

• Remove redundant parentheses in vghsh.vv Sail pseudocode by @GH4169 in #2530

Full Changelog: riscv-isa-release-59e4363-2025-12-20...riscv-isa-release-5c823ad-2025-12-23

Release riscv-isa-release-1d89943-2025-12-23

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 1d89943, is now available.

What's Changed

• Fix incorrect non-normative text in memory-model appendix by @aswaterman in #2535

Full Changelog: riscv-isa-release-5c823ad-2025-12-23...riscv-isa-release-1d89943-2025-12-23

Release riscv-isa-release-936aa76-2025-12-20

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 936aa76, is now available.

What's Changed

• Explicitly clarify that WFI in U-mode is unaffected by mstatus.TW by @ved-rivos in #2517

Full Changelog: riscv-isa-release-53a5ae2-2025-12-18...riscv-isa-release-936aa76-2025-12-20

Release riscv-isa-release-59e4363-2025-12-20

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 59e4363, is now available.

What's Changed

• [#2386] unifying carry-less spelling in vector crypto chapter by @nibrunieAtSi5 in #2527

Full Changelog: riscv-isa-release-2efad6f-2025-12-20...riscv-isa-release-59e4363-2025-12-20