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Supervisor Domain Interrupt Assignment

Interrupts that occur during the execution of a supervisor domain cause a trap to the RDSM in M-mode by default.

To increase performance, the RDSM can delegate the handling of certain interrupts, like the timer interrupt or the local performance counter overflow interrupt (LCOFI), to the supervisor domain by setting the appropriate mideleg bits. This delegation could necessitate the RDSM to context switch additional state related to such delegated interrupts, including stimecmp and the HPM CSRs.

Additionally, the RDSM may assert a virtual interrupt to a supervisor domain. Such virtual interrupts might be asserted as part of handling a real interrupt, such as a RAS interrupt, or they may have no direct connection to any actual interrupt event.

Some supervisor domains may have devices assigned to them for I/O operations. Devices designed to carry out I/O operations typically signal the completion of an I/O task or an associated error via an external interrupt. These external interrupts might be aggregated and indicated by an interrupt controller linked to the RDSM. The RDSM, in the course of handling an external interrupt, should forward the interrupt to the relevant supervisor domain. The efficiency of handling external interrupts by a supervisor domain can be enhanced if the external interrupts could be directly assigned to the supervisor domain.

To accommodate such supervisor domains, this specification extends the IMSIC and APLIC specified by the RISC-V Advanced Interrupt Architecture (AIA) specification cite:[AIA] to support multiple supervisor interrupt domains, enabling an individual supervisor interrupt domain to be associated with each such supervisor domain.

In some systems, a supervisor interrupt domain in both an APLIC and an IMSIC may be associated with a supervisor domain, with the supervisor interrupt domain of the APLIC configured to route interrupts as MSIs to the corresponding supervisor interrupt domain of the IMSIC.

Interrupt controllers other than APLIC and/or IMSIC that support multiple supervisor interrupt domains may also serve a supervisor domain.

If there are N implemented supervisor interrupt domains, they are numbered from 0 to N − 1, and the maximum implemented supervisor interrupt domain number is N − 1.

IMSIC Extension for Supervisor Domains

The IMSIC is extended to support multiple supervisor interrupt domains, where each supervisor interrupt domain may be associated with a supervisor domain. A supervisor interrupt domain in an IMSIC consists of:

  • A supervisor-level interrupt file.

  • Optionally, one or more guest interrupt files.

Each supervisor interrupt domain in an IMSIC is identified by a supervisor interrupt domain number (SIDN).

When all harts are within a single hart group as defined by cite:[AIA], the memory-mapped address of the supervisor-level interrupt file for SIDN n and hart h, is:

\[\text{Address} = B + n \times 2^I + h \times 2^D\]

Constants B, C, and D in this and later formulas are specified by cite:[AIA], while I is a new constant for supervisor interrupt domains. Constant I must be >= k + D, where k is the number of bits needed to represent any hart number h.

If the largest supervisor interrupt domain number is \$n_{\text{max}}\$, then q — the number of bits needed to represent any supervisor interrupt domain number — is defined as:

\[q = \lceil \log_2(n_{\text{max}} + 1) \rceil\]

Address B must be aligned to a \$2^{q + I}\$ address boundary. (This automatically makes B also aligned to a \$2^{k + D}\$ address boundary as required by the existing cite:[AIA].)

When there are hart groups, the memory-mapped address of the supervisor-level interrupt file for group g, SIDN n, and hart h within the group, is:

\[\text{Address} = g \times 2^E + B + n \times 2^I + h \times 2^D\]

Constant E must be >= max(k + C, q + I), but will usually be much larger.

The Smsdia extension ("Smsdia" : Standard Extension for Supervisor Domain Interrupt Assignment) provides the mechanism to select a supervisor interrupt domain in an IMSIC as a source of supervisor-level and guest external interrupts for a hart. The interrupt signal from the selected supervisor interrupt domain’s supervisor-level interrupt file appears as bit SEIP in mip and sip. The interrupt signals from any guest interrupt files of the selected supervisor interrupt domain appear as active bits in the hypervisor CSR hgeip.

The siselect and sireg CSRs access the registers of the supervisor-level interrupt file in the selected supervisor interrupt domain. If the selected supervisor interrupt domain implements guest interrupt files then the vsiselect and vsireg CSRs access the registers of a guest interrupt file, of that supervisor interrupt domain, as determined by hstatus.VGEIN.

APLIC Extension for Supervisor Domains

The APLIC supports the concept of multiple interrupt domains where each interrupt domain may be associated with a subset of RISC-V harts at one privilege level. To support the Supervisor Domain use cases, the APLIC must support multiple supervisor-level interrupt domains. A supervisor-level interrupt domain in the APLIC may be then associated with a Supervisor Domain by configuring it in direct delivery mode or when the hart uses an IMSIC by configuring it in MSI delivery mode.

To support supervisor domains in MSI delivery mode, the smsiaddrcfgh register is extended with two new parameters called DXS (Domain Index Shift) and DXW (Domain Index Width) to help determine the addresses to write outgoing MSIs. The extended smsiaddrcfgh has the following format:

    bits 28:24     DXS (WARL)
    bits 22:20     LHXS (WARL)
    bits 18:16     DXW (WARL)
    bits 11:0      High Base PPN (WARL)

Let CI be the Child Index from the sourcecfg[i] corresponding to an interrupt source i. The MSI target address for this interrupt source is then computed as follows:

\[n = \text{CI} \mathbin{\&} \left( 2^{\text{DXW}} - 1 \right)\]
\[\text{MSI address} = \left( \text{Base PPN} \mid ( n \ll \text{DXS} ) \mid ( g \ll (\text{HHXS} + 12) ) \mid ( h \ll \text{LHXS} ) \mid \text{Guest Index} \right) \ll 12\]

The parameter DXS relates to the constant I specified in section IMSIC Extension for Supervisor Domains as: DXS = (I - 12).

Refer to cite:[AIA] for the detailed definitions of constants HHXS, g, h, LHXS, and Guest Index.

"Smsdia" : Standard Extension for Supervisor Domain Interrupt Assignment

The Smsdia extension adds supports to select a supervisor interrupt domain in an interrupt controller as a source of supervisor-level and guest external interrupts for a hart using the msdcfg CSR.

The RDSM needs a method to be alerted if an external interrupt, whether a supervisor-level external interrupt or guest external interrupt, is pending for any supervisor domains not currently active on a hart. The RDSM could leverage this notification to inform its scheduling decisions. To facilitate this functionality, the Smsdia extension introduces the msideip and msideie CSRs, along with a machine supervisor domain external interrupt (MSDEI).

Machine supervisor domain configuration (msdcfg)

The msdcfg is a 32-bit read/write register, formatted as shown in [MSDCFG].

The SIDN field selects an interrupt domain among the plurality of supervisor interrupt domains associated with a hart as the active supervisor interrupt domain for supervisor-level external interrupt and guest external interrupts.

The SIDN field is a WLRL field that must be able to hold a value between 0 and the maximum implemented supervisor interrupt domain number, inclusive. If there is only a single supervisor interrupt domain connected to the hart, then SIDN may be read-only zero.

When SIDN is not the number of an implemented supervisor interrupt domain then the following rules apply:

  • The supervisor-level external interrupt pending signal indicated in mip.SEIP is 0.

  • All non-custom values of siselect that access IMSIC registers designate an inaccessible register. When siselect holds the number of an inaccessible register, attempts from M-mode or HS-mode to access sireg raise an illegal instruction exception.

  • Access to CSR stopei raises an illegal instruction exception.

  • The hstatus.vgein field is read-only zero.

  • hgeip and hgeie are read-only 0.

When the supervisor interrupt domain selected by msdcfg.SIDN is an implemented, and is an IMSIC, the following rules apply:

  • The supervisor-level external interrupt pending signal of supervisor-level interrupt file of the selected supervisor interrupt domain is indicated in mip.SEIP.

  • The siselect and stopei CSRs operate on the registers of the supervisor-level interrupt file in the selected supervisor interrupt domain.

  • The guest external interrupt pending signals of the guest interrupt files of selected supervisor interrupt domain are indicated in the hgeip CSR.

  • The hstatus.VGEIN selects a guest interrupt file in the selected supervisor interrupt domain and vsiselect and vstopei CSRs operate on the registers of the corresponding guest interrupt file.

When the supervisor interrupt domain selected by msdcfg.SIDN is implemented, and is an APLIC, the following rules apply:

  • The supervisor-level external interrupt pending signal of the selected APLIC supervisor interrupt domain is indicated in mip.SEIP.

Note

The Smsdia extension provides for directly associating a supervisor interrupt domain with up to 64 supervisor domains. The RDSM may emulate interrupt controllers for additional supervisor domains.

To emulate an IMSIC supervisor interrupt domain, the RDSM may use the illegal instruction trap facilitated by AIA-added state-enable bits to mstateen0/mstateen0h for emulation purposes.

Hypervisor Guest External Interrupt Registers (hgeip and hgeie)

When the H extension is also implemented, the implementation must internally maintain an array of registers that hold the state of the hgeip and hgeie CSRs, with one pair of registers per implemented supervisor interrupt domain number. The hgeip and hgeie CSRs access the element of this array corresponding to the value of msdcfg.SIDN.

Machine supervisor interrupt domain external interrupt pending (msideip/msideiph)

The msideip is a 64-bit read-only register, formatted as shown in msideip register. When MXLEN=32, msideiph is a 32-bit read-only register which aliases bits 63:32 of msideip. When MXLEN=64, msideiph does not exist.

msideip register
{reg: [
  {bits: 64, name: 'Interrupts'},
], config:{lanes: 1, hspace:1024}}

Each bit i in the register summarizes the external interrupts pending in the supervisor interrupt domain numbered i.

When the supervisor interrupt domain identified by i is implemented by an APLIC, the bit i indicates the state of the supervisor-level external interrupt pending signal provided by the supervisor interrupt domain in that APLIC.

When the supervisor interrupt domain identified by i is implemented by an IMSIC, bit i must be set to one if and only if either of the following conditions holds:

  • the SEIP signal for supervisor interrupt domain i is asserted; or

  • the bitwise logical AND of the internal hgeip and hgeie registers for supervisor interrupt domain i is nonzero (i.e., the value that SGEIP would have for that domain).

The summary of external interrupts pending in a supervisor interrupt domain is visible in the msideip register even when msdcfg.SIDN is not the valid number of an implemented supervisor interrupt domain.

Machine supervisor interrupt domain external interrupt enable (msideie/msideieh)

The msideie is a 64-bit read-write register, formatted as shown in msideie register. When MXLEN=32, msideieh is a 32-bit read-write register which aliases bits 63:32 of msideie. When MXLEN=64, msideieh does not exist.

msideie register
{reg: [
  {bits: 64, name: 'Interrupts (WARL)'},
], config:{lanes: 1, hspace:1024}}

The msideie CSR selects the subset of supervisor interrupt domains that cause a machine supervisor interrupt domain external interrupt. The enable bits in msideie do not affect the supervisor-level external interrupt and guest external interrupt pending signals from the supervisor interrupt domain selected by msdcfg.SIDN.

Machine and Supervisor Interrupt registers (mip/mie and sip/sie)

The Smsdia extension introduces the machine supervisor domain external interrupt (MSDEI). This interrupt is treated as a standard local interrupt that is assigned to bit 14 in the mip, mie, sip, and sie registers. The bit 14 in mip and sip is called MSDEIP and the same bit in mie and sie is called MSDEIE. The mideleg register controls the delegation of MSDEI to S-mode. This interrupt cannot be delegated to VS-mode and bit 14 of hideleg is read-only zero.

The mip.MSDEIP bit read-only and is set to 1 if the bitwise logical AND of CSRs msideip and msideie is nonzero in any bit. The mie.MSDEIE bit is writable.

When bit 14 of mideleg is zero, sip.MSDEIP and sie.MSDEIE are read-only zeros. Else, sip.MSDEIP and sie.MSDEIE are aliases of mip.MSDEIP and mie.MSDEIE.

Multiple simultaneous interrupts destined for different privilege modes are handled in decreasing order of destined privilege mode. For the base Privileged ISA’s major interrupts (numbers 0-15), multiple simultaneous interrupts destined for the same privilege mode are handled in the following decreasing default priority order: MEI, MSI, MTI, MSDEI, SEI, SSI, STI, SGEI, VSEI, VSSI, VSTI, LCOFI.

Note

The RDSM may use the machine supervisor interrupt domain external interrupt to determine if a supervisor domain has become ready to run since it was last descheduled. When a supervisor domain that has a supervisor domain interrupt controller directly assigned to it, the RDSM updates the msdcfg.SIDN to select that supervisor interrupt domain and may clear the bit corresponding to that supervisor interrupt domain in msideie prior to resuming execution of the supervisor domain.

The RDSM may delegate MSDEI to a supervisor domain that may be entrusted by the RDSM to get notified about supervisor domain external interrupts pending for one or more other supervisor domains. Typically, this use case involves a single supervisor domain that is trusted by the RDSM to receive such notifications. The delegation supports optimizing the exit sequence from such supervisor domain by enabling such supervisor domains to voluntarily yield execution in response to pending interrupts for the other supervisor domains.

"Smgeien/Ssgeien" : Standard Extension for Machine Guest External Interrupt Enables

The Smgeien extension enables access to a subset of the guest interrupt files within a supervisor interrupt domain in an IMSIC to a supervisor domain. The Smgeien extension depends on the Smsdia extension.

The Smgeien extension depends on the Smaia, Ssaia, and the H extension. When Smgeien is implemented, the bit 9 of mvien must be writable.

This extension introduces an MXLEN read-write WARL register named mgeien, formatted as shown in mgeien register for RV64 for RV64 and in [MGEIEN32] for RV32.

mgeien register for RV64
{reg: [
  {bits:  1, name: 'A'},
  {bits: 63, name: 'GIF'},
], config:{lanes: 1, hspace:1024}}
mgeien register for RV32
{reg: [
  {bits:  1, name: 'A'},
  {bits: 31, name: 'GIF'},
], config:{lanes: 1, hspace:1024}}
Note

The RDSM may use bit 9 of mvien to control access to the supervisor-level interrupt file in the supervisor interrupt domain selected by msdcfg.SIDN.

Each bit of the GIF field when set to 1 enables access to corresponding guest interrupt file in the supervisor interrupt domain selected by msdcfg.SIDN.

The number of writable bits in mgeien is determined by the maximum GEILEN value across all supervisor interrupt domains, and this maximum is referred to as MGEILEN. If MGEILEN is nonzero, bits MGEILEN-1:0 shall be writable in mgeien. All other bit positions in the GIF field shall be read-only zeros.

For a supervisor-level environment, extension Ssgeien is essentially the same as Smgeien except excluding the machine-level CSRs and behavior not directly visible to supervisor level.

If the supervisor interrupt domain selected by msdcfg.SIDN is implemented then:

  • Bits GEILEN:1 of hgeip are read-only aliases of the same bits in the internal hgeip register selected by msdcfg.SIDN if the bit at the same position in mgeien is 1. All other bits of hgeip are zero.

  • Bits GEILEN:1 of hgeie are writable aliases of the same bits in the internal hgeie register selected by msdcfg.SIDN if the bit at the same position in mgeien is 1. All other bits of hgeie are read-only zero.

  • If hstatus.VGEIN is not 0 and the bit selected by VGEIN in mgeien is 1 then the vsiselect, vsireg, and vstopei CSRs operate on the registers of the guest interrupt file selected by VGEIN. If VGEIN is 0 or the the bit selected by VGEIN in mgeien is 0 then the vsiselect, vsireg, and vstopei CSRs operate as-if the VGEIN is the number of an unimplemented guest external interrupt.

The mgeien.A bit, when set to 1, enables msideip to accumulate all external interrupts for the supervisor interrupt domain; otherwise, msideip accumulates only the subset of guest external interrupts determined by mgeien.GIF. When mgeien.A is 0, the SEIP for the supervisor interrupt domain is accumulated in msideip if it is not delegated to the supervisor domain.

Each bit i of msideip, corresponding to an implemented supervisor interrupt domain, must be set to one if and only if the relevant interrupt source is active.

Specifically:

  • If i equals msdcfg.SIDN, the bit is set to one if and only if either:

    • mip.SEIP is 1 and bit 9 (for SEI) of mideleg is zero; or

    • mip.SEIP is 1 and mgeien.A is 1; or

    • The bitwise logical AND of the following three components of the supervisor interrupt domain is nonzero:

      • the internal hgeip,

      • the internal hgeie, and

      • the logical complement of mgeien if mgeien.A is 0; otherwise, a value of all 1s.

Note

The Smgeien extension is intended for use cases involving supervisor domains that share the guest interrupt files in a supervisor interrupt domain.

Typically, one of the supervisor domains participating in the scheme acts as a donor domain that initially has access to all the interrupt files. Such a donor supervisor domain may then donate one or more interrupt files—​usually _guest interrupt files—​to a recipient supervisor domain, either temporarily or permanently, by invoking SBI functions provided by the RDSM. Once the interrupt files have been made accessible to the recipient domain by the RDSM, the donor domain is not expected to access them.

Recipient domains must not assume that the donated interrupt files are contiguously laid out in memory, nor should they expect the corresponding bits in hgeip and hgeie to be contiguous. Furthermore, a recipient must not assume it can use a supervisor-level interrupt file unless it has been explicitly made accessible. This behavior is indicated by the Ssgeien extension.

The memory locations of the accessible guest interrupt files, along with their guest external interrupt numbers, are communicated to recipient supervisor domains by the RDSM through software mechanisms such as SBI.