diff --git a/CMakeLists.txt b/CMakeLists.txt index 58fe2324f..22ea2e3f8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -125,8 +125,6 @@ execute_process( ) message(STATUS "Sail library directory: ${sail_dir}") -set(DEFAULT_ARCHITECTURES "rv32d;rv64d" CACHE STRING "Architectures to build by default (rv32f|rv64f|rv32d|rv64d)(_rvfi)? " ) - option(COVERAGE "Compile with Sail coverage collection enabled.") # Softfloat support. @@ -167,8 +165,8 @@ endif() include(CPack) # Convenience targets. -add_custom_target(csim DEPENDS riscv_sim_rv32d riscv_sim_rv64d) -add_custom_target(check DEPENDS generated_model_rv32d generated_model_rv64d) +add_custom_target(csim DEPENDS riscv_sim_rv) +add_custom_target(check DEPENDS generated_model_rv) # TODO: Add `interpret` target. # TODO: Add hol4 target. diff --git a/README.md b/README.md index 32e00e299..1c9e45e38 100644 --- a/README.md +++ b/README.md @@ -34,16 +34,14 @@ Install [Sail](https://github.com/rems-project/sail/). On Linux you can download $ ./build_simulators.sh ``` -will build the simulators in `build/c_emulator/riscv_sim_rv{32,64}d`. +will build the simulator at `build/c_emulator/riscv_sim_rv`. If you get an error message saying `sail: unknown option '--require-version'.` it's because your Sail compiler is too old. You need version 0.19 or later. -By default the RV32D and RV64D emulators are built, without RVFI-DII support. -You can see a complete list of targets by running `make help` in the -build directory, then e.g. +By default the emulator is built without RVFI-DII support. For RVFI support run ``` -$ make -C build riscv_sim_rv64f_rvfi +$ make -C build riscv_sim_rv_rvfi ``` By default `build_simulators.sh` will download and build [libgmp](https://gmplib.org/). @@ -54,7 +52,7 @@ To use a system installation of libgmp, run `env DOWNLOAD_GMP=FALSE ./build_simu The simulator can be used to execute small test binaries. ``` -$ build/c_emulator/riscv_sim_ +$ build/c_emulator/riscv_sim_rv ``` A suite of RV32 and RV64 test programs derived from the @@ -66,13 +64,13 @@ can be run using `make test` or `ctest` in the build directory. The model is configured using a JSON file specifying various tunable options. The default configuration used for the model can be examined -using `build/c_emulator/riscv_sim_ --print-default-config`. To +using `build/c_emulator/riscv_sim_rv --print-default-config`. To use a custom configuration, save the default configuration into a file, edit it as needed, and pass it to the simulator using the `--config` option. Information on other options for the simulator is available from -`build/c_emulator/riscv_sim_ -h`. +`build/c_emulator/riscv_sim_rv -h`. ### Booting OS images diff --git a/c_emulator/CMakeLists.txt b/c_emulator/CMakeLists.txt index 87447cfc1..5bb1f4033 100644 --- a/c_emulator/CMakeLists.txt +++ b/c_emulator/CMakeLists.txt @@ -14,70 +14,57 @@ set(EMULATOR_COMMON_SRCS riscv_softfloat.h ) -foreach (xlen IN ITEMS 32 64) - foreach (flen IN ITEMS 32 64) - foreach (variant IN ITEMS "" "rvfi") - set(arch "rv${xlen}") - if (flen EQUAL 32) - string(APPEND arch "f") - else() - string(APPEND arch "d") - endif() - if (variant) - string(APPEND arch "_${variant}") - endif() +foreach (variant IN ITEMS "" "rvfi") + set(arch "rv") + if (variant) + string(APPEND arch "_${variant}") + endif() - add_executable(riscv_sim_${arch} - "${CMAKE_BINARY_DIR}/riscv_model_${arch}.c" - ${EMULATOR_COMMON_SRCS} - ) - # The generated model is not warnings-clean, silence them. - # -Wno-self-assing is needed for `zhtif_tohost = zhtif_tohost` - # generated by the sail code to avoid optimizing the function out. - set(_generated_c_warning_opt_out - -Wno-extra - -Wno-unused - -Wno-uninitialized - $<$:-Wno-self-assign> - ) - set_source_files_properties("${CMAKE_BINARY_DIR}/riscv_model_${arch}.c" - PROPERTIES COMPILE_OPTIONS "${_generated_c_warning_opt_out}") + add_executable(riscv_sim_${arch} + "${CMAKE_BINARY_DIR}/riscv_model_${arch}.c" + ${EMULATOR_COMMON_SRCS} + ) + # The generated model is not warnings-clean, silence them. + # -Wno-self-assing is needed for `zhtif_tohost = zhtif_tohost` + # generated by the sail code to avoid optimizing the function out. + set(_generated_c_warning_opt_out + -Wno-extra + -Wno-unused + -Wno-uninitialized + $<$:-Wno-self-assign> + ) + set_source_files_properties("${CMAKE_BINARY_DIR}/riscv_model_${arch}.c" + PROPERTIES COMPILE_OPTIONS "${_generated_c_warning_opt_out}") - if (NOT arch IN_LIST DEFAULT_ARCHITECTURES) - set_target_properties(riscv_sim_${arch} PROPERTIES EXCLUDE_FROM_ALL TRUE) - endif() + add_dependencies(riscv_sim_${arch} generated_model_${arch}) - add_dependencies(riscv_sim_${arch} generated_model_${arch}) + target_link_libraries(riscv_sim_${arch} + PRIVATE softfloat sail_runtime default_config GMP::GMP + ) - target_link_libraries(riscv_sim_${arch} - PRIVATE softfloat sail_runtime default_config GMP::GMP - ) + target_include_directories(riscv_sim_${arch} + # So the generated C can find riscv_platform/prelude.h" + PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}" + ) - target_include_directories(riscv_sim_${arch} - # So the generated C can find riscv_platform/prelude.h" - PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}" - ) + if (arch MATCHES "rvfi") + target_compile_definitions(riscv_sim_${arch} + PRIVATE RVFI_DII + ) + endif() - if (arch MATCHES "rvfi") - target_compile_definitions(riscv_sim_${arch} - PRIVATE RVFI_DII - ) - endif() + # TODO: Enable warnings when we use the #include trick + # to include the generated Sail code. Currently it + # generates too many warnings to turn these on globally. - # TODO: Enable warnings when we use the #include trick - # to include the generated Sail code. Currently it - # generates too many warnings to turn these on globally. + # target_compile_options(riscv_sim_${arch} PRIVATE + # -Wall -Wextra + # # Too annoying at the moment. + # -Wno-unused-parameter + # ) - # target_compile_options(riscv_sim_${arch} PRIVATE - # -Wall -Wextra - # # Too annoying at the moment. - # -Wno-unused-parameter - # ) - - install(TARGETS riscv_sim_${arch} - OPTIONAL - RUNTIME DESTINATION "bin" - ) - endforeach() - endforeach() + install(TARGETS riscv_sim_${arch} + OPTIONAL + RUNTIME DESTINATION "bin" + ) endforeach() diff --git a/c_emulator/riscv_platform.cpp b/c_emulator/riscv_platform.cpp index c8aeff91d..d4baa3c41 100644 --- a/c_emulator/riscv_platform.cpp +++ b/c_emulator/riscv_platform.cpp @@ -24,9 +24,9 @@ mach_bits plat_get_16_random_bits(unit) return rv_16_random_bits(); } -unit load_reservation(mach_bits addr) +unit load_reservation(sbits addr) { - reservation = addr; + reservation = addr.bits; reservation_valid = true; RESERVATION_DBG("reservation <- %0" PRIx64 "\n", reservation); return UNIT; @@ -42,10 +42,10 @@ static mach_bits check_mask() return (zxlen_val == 32) ? 0x00000000FFFFFFFF : -1; } -bool match_reservation(mach_bits addr) +bool match_reservation(sbits addr) { mach_bits mask = check_mask(); - bool ret = reservation_valid && (reservation & mask) == (addr & mask); + bool ret = reservation_valid && (reservation & mask) == (addr.bits & mask); RESERVATION_DBG("reservation(%c): %0" PRIx64 ", key=%0" PRIx64 ": %s\n", reservation_valid ? 'v' : 'i', reservation, addr, ret ? "ok" : "fail"); diff --git a/c_emulator/riscv_platform.h b/c_emulator/riscv_platform.h index 2ee9c3bf5..944425bc2 100644 --- a/c_emulator/riscv_platform.h +++ b/c_emulator/riscv_platform.h @@ -9,8 +9,8 @@ extern "C" { mach_bits plat_get_16_random_bits(unit); bool speculate_conditional(unit); -unit load_reservation(mach_bits); -bool match_reservation(mach_bits); +unit load_reservation(sbits); +bool match_reservation(sbits); unit cancel_reservation(unit); unit plat_term_write(mach_bits); diff --git a/c_emulator/riscv_sail.h b/c_emulator/riscv_sail.h index 894b3ee5c..a072e83d5 100644 --- a/c_emulator/riscv_sail.h +++ b/c_emulator/riscv_sail.h @@ -8,12 +8,6 @@ extern "C" { typedef int unit; #define UNIT 0 -typedef uint64_t mach_bits; - -struct zMisa { - mach_bits zMisa_chunk_0; -}; -extern struct zMisa zmisa; void model_init(void); void model_fini(void); @@ -24,9 +18,9 @@ unit ztick_clock(unit); unit ztick_platform(unit); #ifdef RVFI_DII -unit zrvfi_set_instr_packet(mach_bits); -mach_bits zrvfi_get_cmd(unit); -mach_bits zrvfi_get_insn(unit); +unit zrvfi_set_instr_packet(uint64_t); +uint64_t zrvfi_get_cmd(unit); +uint64_t zrvfi_get_insn(unit); bool zrvfi_step(sail_int); unit zrvfi_zzero_exec_packet(unit); unit zrvfi_halt_exec_packet(unit); @@ -43,33 +37,20 @@ unit zprint_rvfi_exec(unit); unit zprint_instr_packet(uint64_t); #endif -extern mach_bits zxlen_val; +extern uint64_t zxlen_val; extern bool zhtif_done; -extern mach_bits zhtif_exit_code; +extern uint64_t zhtif_exit_code; extern bool have_exception; /* machine state */ -extern uint32_t zcur_privilege; - -extern mach_bits zPC; - -extern mach_bits zx1, zx2, zx3, zx4, zx5, zx6, zx7, zx8, zx9, zx10, zx11, zx12, - zx13, zx14, zx15, zx16, zx17, zx18, zx19, zx20, zx21, zx22, zx23, zx24, - zx25, zx26, zx27, zx28, zx29, zx30, zx31; - -extern mach_bits zmstatus; -extern mach_bits zmepc, zmtval; -extern mach_bits zsepc, zstval; - -extern mach_bits zfloat_result, zfloat_fflags; +unit zforce_pc(uint64_t pc); -struct zMcause { - mach_bits zMcause_chunk_0; -}; -extern struct zMcause zmcause, zscause; +extern uint64_t zfloat_result, zfloat_fflags; -extern mach_bits zminstret; +// Initialise types based on config values. +void sail_set_abstract_xlen(void); +void sail_set_abstract_ext_d_supported(void); #ifdef __cplusplus } // extern "C" diff --git a/c_emulator/riscv_sim.cpp b/c_emulator/riscv_sim.cpp index 03113c924..8bc9532d1 100644 --- a/c_emulator/riscv_sim.cpp +++ b/c_emulator/riscv_sim.cpp @@ -449,7 +449,7 @@ void init_sail_reset_vector(uint64_t entry) } /* boot at reset vector */ - zPC = rom_base; + zforce_pc(rom_base); } void init_sail(uint64_t elf_entry) @@ -465,15 +465,18 @@ void init_sail(uint64_t elf_entry) rv_clint_size = UINT64_C(0); rv_htif_tohost = UINT64_C(0); */ - zPC = elf_entry; - } else + zforce_pc(elf_entry); + } else { init_sail_reset_vector(elf_entry); + } } /* reinitialize to clear state and memory, typically across tests runs */ void reinit_sail(uint64_t elf_entry) { model_fini(); + sail_set_abstract_xlen(); + sail_set_abstract_ext_d_supported(); model_init(); init_sail(elf_entry); } @@ -676,6 +679,8 @@ int main(int argc, char **argv) { int files_start = process_args(argc, argv); + sail_set_abstract_xlen(); + sail_set_abstract_ext_d_supported(); model_init(); if (do_report_arch) { diff --git a/config/default.json b/config/default.json index 9ef58c764..55084ead6 100644 --- a/config/default.json +++ b/config/default.json @@ -1,5 +1,6 @@ { "base": { + "xlen": 64, "writable_misa": true, "writable_fiom": true, "writable_hpm_counters": { @@ -49,7 +50,10 @@ "A": { "supported": true }, - "FD": { + "F": { + "supported": true + }, + "D": { "supported": true }, "V": { diff --git a/config/rv32d.json b/config/rv32d.json new file mode 100644 index 000000000..e612261a4 --- /dev/null +++ b/config/rv32d.json @@ -0,0 +1,200 @@ +{ + "base": { + "xlen": 32, + "writable_misa": true, + "writable_fiom": true, + "writable_hpm_counters": { + "len": 32, + "value": "0xFFFF_FFFF" + }, + "mtval_has_illegal_instruction_bits": false + }, + "memory": { + "pmp": { + "grain": 0, + "count": 16 + }, + "misaligned": { + "supported": true + }, + "translation": { + "dirty_update": false + } + }, + "platform": { + "reset_vector": 4096, + "cache_block_size_exp": 6, + "ram": { + "base": 2147483648, + "size": 2147483648 + }, + "rom": { + "base": 4096, + "size": 4096 + }, + "clint": { + "base": 33554432, + "size": 786432 + }, + "instructions_per_tick": 100, + "wfi_is_nop": true + }, + "extensions": { + "M": { + "supported": true + }, + "A": { + "supported": true + }, + "F": { + "supported": true + }, + "D": { + "supported": true + }, + "V": { + "supported": true, + "vlen_exp": 9, + "elen_exp": 6, + "vl_use_ceil": false + }, + "B": { + "supported": true + }, + "S": { + "supported": true + }, + "U": { + "supported": true + }, + "Zicbom": { + "supported": true + }, + "Zicboz": { + "supported": true + }, + "Zicond": { + "supported": true + }, + "Zicntr": { + "supported": true + }, + "Zifencei": { + "supported": true + }, + "Zihpm": { + "supported": true + }, + "Zimop": { + "supported": true + }, + "Zmmul": { + "supported": false + }, + "Zaamo": { + "supported": false + }, + "Zabha": { + "supported": true + }, + "Zalrsc": { + "supported": false + }, + "Zfa": { + "supported": true + }, + "Zfh": { + "supported": true + }, + "Zfhmin": { + "supported": false + }, + "Zfinx": { + "supported": false + }, + "Zca": { + "supported": true + }, + "Zcf": { + "supported": true + }, + "Zcd": { + "supported": true + }, + "Zcb": { + "supported": true + }, + "Zcmop": { + "supported": true + }, + "Zba": { + "supported": false + }, + "Zbb": { + "supported": false + }, + "Zbs": { + "supported": false + }, + "Zbc": { + "supported": true + }, + "Zbkb": { + "supported": true + }, + "Zbkc": { + "supported": true + }, + "Zbkx": { + "supported": true + }, + "Zknd": { + "supported": true + }, + "Zkne": { + "supported": true + }, + "Zknh": { + "supported": true + }, + "Zkr": { + "supported": true + }, + "Zksed": { + "supported": true + }, + "Zksh": { + "supported": true + }, + "Zhinx": { + "supported": false + }, + "Zvbb": { + "supported": true + }, + "Zvkb": { + "supported": false + }, + "Zvbc": { + "supported": true + }, + "Zvknha": { + "supported": true + }, + "Zvknhb": { + "supported": true + }, + "Sscofpmf": { + "supported": true + }, + "Smcntrpmf": { + "supported": true + }, + "Sstc": { + "supported": true + }, + "Svinval": { + "supported": true + } + } +} diff --git a/config/rv64d.json b/config/rv64d.json new file mode 100644 index 000000000..3030692a4 --- /dev/null +++ b/config/rv64d.json @@ -0,0 +1,200 @@ +{ + "base": { + "xlen": 64, + "writable_misa": true, + "writable_fiom": true, + "writable_hpm_counters": { + "len": 32, + "value": "0xFFFF_FFFF" + }, + "mtval_has_illegal_instruction_bits": false + }, + "memory": { + "pmp": { + "grain": 0, + "count": 16 + }, + "misaligned": { + "supported": true + }, + "translation": { + "dirty_update": false + } + }, + "platform": { + "reset_vector": 4096, + "cache_block_size_exp": 6, + "ram": { + "base": 2147483648, + "size": 2147483648 + }, + "rom": { + "base": 4096, + "size": 4096 + }, + "clint": { + "base": 33554432, + "size": 786432 + }, + "instructions_per_tick": 100, + "wfi_is_nop": true + }, + "extensions": { + "M": { + "supported": true + }, + "A": { + "supported": true + }, + "F": { + "supported": true + }, + "D": { + "supported": true + }, + "V": { + "supported": true, + "vlen_exp": 9, + "elen_exp": 6, + "vl_use_ceil": false + }, + "B": { + "supported": true + }, + "S": { + "supported": true + }, + "U": { + "supported": true + }, + "Zicbom": { + "supported": true + }, + "Zicboz": { + "supported": true + }, + "Zicond": { + "supported": true + }, + "Zicntr": { + "supported": true + }, + "Zifencei": { + "supported": true + }, + "Zihpm": { + "supported": true + }, + "Zimop": { + "supported": true + }, + "Zmmul": { + "supported": false + }, + "Zaamo": { + "supported": false + }, + "Zabha": { + "supported": true + }, + "Zalrsc": { + "supported": false + }, + "Zfa": { + "supported": true + }, + "Zfh": { + "supported": true + }, + "Zfhmin": { + "supported": false + }, + "Zfinx": { + "supported": false + }, + "Zca": { + "supported": true + }, + "Zcf": { + "supported": true + }, + "Zcd": { + "supported": true + }, + "Zcb": { + "supported": true + }, + "Zcmop": { + "supported": true + }, + "Zba": { + "supported": false + }, + "Zbb": { + "supported": false + }, + "Zbs": { + "supported": false + }, + "Zbc": { + "supported": true + }, + "Zbkb": { + "supported": true + }, + "Zbkc": { + "supported": true + }, + "Zbkx": { + "supported": true + }, + "Zknd": { + "supported": true + }, + "Zkne": { + "supported": true + }, + "Zknh": { + "supported": true + }, + "Zkr": { + "supported": true + }, + "Zksed": { + "supported": true + }, + "Zksh": { + "supported": true + }, + "Zhinx": { + "supported": false + }, + "Zvbb": { + "supported": true + }, + "Zvkb": { + "supported": false + }, + "Zvbc": { + "supported": true + }, + "Zvknha": { + "supported": true + }, + "Zvknhb": { + "supported": true + }, + "Sscofpmf": { + "supported": true + }, + "Smcntrpmf": { + "supported": true + }, + "Sstc": { + "supported": true + }, + "Svinval": { + "supported": true + } + } +} diff --git a/model/CMakeLists.txt b/model/CMakeLists.txt index 8c1bfb2cb..4cbd83f18 100644 --- a/model/CMakeLists.txt +++ b/model/CMakeLists.txt @@ -6,587 +6,561 @@ function(string_upper_initial s result) set("${result}" "${new}" PARENT_SCOPE) endfunction() -foreach (xlen IN ITEMS 32 64) - foreach (flen IN ITEMS 32 64) - foreach (variant IN ITEMS "" "rvfi" "rocq" "rmem" "lean" "lem" "isabelle") - set(arch "rv${xlen}") - if (flen EQUAL 32) - string(APPEND arch "f") - else() - string(APPEND arch "d") - endif() - if (variant STREQUAL "rvfi") - string(APPEND arch "_${variant}") - endif() - - set(sail_xlen - "riscv_xlen${xlen}.sail" - "riscv_xlen.sail" - ) - - # TODO: Unfortunately 32 or 64 bit float support is a compile time. - # See https://github.com/riscv/sail-riscv/issues/348 - if (flen EQUAL 64) - set(sail_flen "riscv_flen_D.sail") - else() - set(sail_flen "riscv_flen_F.sail") - endif() - list(APPEND sail_flen "riscv_flen.sail") - - set(sail_vlen "riscv_vlen.sail") - - # Instruction sources, depending on target - set(sail_check_srcs - "riscv_addr_checks_common.sail" - "riscv_addr_checks.sail" - "riscv_misa_ext.sail" - ) - - set(vext_srcs - "riscv_insts_vext_utils.sail" - "riscv_insts_vext_fp_utils.sail" - "riscv_insts_vext_vset.sail" - "riscv_insts_vext_arith.sail" - "riscv_insts_vext_fp.sail" - "riscv_insts_vext_mem.sail" - "riscv_insts_vext_mask.sail" - "riscv_insts_vext_vm.sail" - "riscv_insts_vext_fp_vm.sail" - "riscv_insts_vext_red.sail" - "riscv_insts_vext_fp_red.sail" - ) - - set(sail_default_inst - "riscv_insts_base.sail" - "riscv_insts_zifencei.sail" - "riscv_insts_aext.sail" - "riscv_insts_zca.sail" - "riscv_insts_mext.sail" - "riscv_insts_zicsr.sail" - "riscv_insts_hints.sail" - "riscv_insts_fext.sail" - "riscv_insts_zcf.sail" - "riscv_insts_dext.sail" - "riscv_insts_zcd.sail" - "riscv_insts_svinval.sail" - "riscv_insts_zba.sail" - "riscv_insts_zbb.sail" - "riscv_insts_zbc.sail" - "riscv_insts_zbs.sail" - "riscv_insts_zcb.sail" - "riscv_insts_zfh.sail" - # Zfa needs to be added after fext, dext and Zfh (as it needs - # definitions from those) - "riscv_insts_zfa.sail" - "riscv_insts_zkn.sail" - "riscv_insts_zks.sail" - "riscv_insts_zbkb.sail" - "riscv_insts_zbkx.sail" - "riscv_insts_zicond.sail" - ${vext_srcs} - "riscv_insts_zicbom.sail" - "riscv_insts_zicboz.sail" - "riscv_insts_zvbb.sail" - "riscv_insts_zvbc.sail" - "riscv_insts_zvknhab.sail" - # Zimop and Zcmop should be at the end so they can be overridden by earlier extensions - "riscv_insts_zimop.sail" - "riscv_insts_zcmop.sail" - ) - - if (variant STREQUAL "rmem") - set(sail_seq_inst - ${sail_default_inst} - "riscv_jalr_rmem.sail" - "riscv_insts_rmem.sail" - ) - else() - set(sail_seq_inst - ${sail_default_inst} - "riscv_jalr_seq.sail" - ) - endif() - - set(sail_seq_inst_srcs - "riscv_insts_begin.sail" - ${sail_seq_inst} - "riscv_insts_end.sail" - "riscv_csr_end.sail" - ) - - set(sail_sys_srcs - "riscv_vext_control.sail" - "riscv_sys_exceptions.sail" - "riscv_sync_exception.sail" - "riscv_zihpm.sail" - "riscv_sscofpmf.sail" - "riscv_zkr_control.sail" - "riscv_zicntr_control.sail" - "riscv_softfloat_interface.sail" - "riscv_fdext_regs.sail" - "riscv_fdext_control.sail" - "riscv_smcntrpmf.sail" - "riscv_sys_control.sail" - ) - - set(sail_vm_srcs - "riscv_vmem_pte.sail" - "riscv_vmem_ptw.sail" - "riscv_vmem_tlb.sail" - "riscv_vmem.sail" - ) - - set(prelude - "prelude.sail" - "riscv_errors.sail" - ${sail_xlen} - ${sail_flen} - ${sail_vlen} - "prelude_mem_addrtype.sail" - "prelude_mem_metadata.sail" - "prelude_mem.sail" - "arithmetic.sail" - ) - - if (variant STREQUAL "rvfi") - list(APPEND prelude "rvfi_dii.sail") - endif() - - set(sail_regs_srcs - "riscv_csr_begin.sail" - "riscv_reg_type.sail" - "riscv_freg_type.sail" - "riscv_regs.sail" - "riscv_pc_access.sail" - "riscv_sys_regs.sail" - "riscv_pmp_regs.sail" - "riscv_pmp_control.sail" - "riscv_ext_regs.sail" - ${sail_check_srcs} - "riscv_vreg_type.sail" - "riscv_vext_regs.sail" - ) - - set(sail_arch_srcs - ${prelude} - "riscv_extensions.sail" - "riscv_types_common.sail" - "riscv_types_ext.sail" - "riscv_types.sail" - "riscv_vmem_types.sail" - ${sail_regs_srcs} - ${sail_sys_srcs} - "riscv_platform.sail" - "riscv_mem.sail" - ${sail_vm_srcs} - # Shared/common code for the cryptography extension. - "riscv_types_kext.sail" - "riscv_zvk_utils.sail" - "riscv_inst_retire.sail" - ) - - if (variant STREQUAL "rvfi") - set(riscv_step_ext "riscv_step_rvfi.sail") - set(riscv_fetch "riscv_fetch_rvfi.sail") - else() - set(riscv_step_ext "riscv_step_ext.sail") - set(riscv_fetch "riscv_fetch.sail") - endif() - - set(sail_step_srcs - "riscv_step_common.sail" - ${riscv_step_ext} - "riscv_decode_ext.sail" - ${riscv_fetch} - "riscv_step.sail" - ) - - if (variant STREQUAL "rocq" OR variant STREQUAL "lean") - list(APPEND sail_step_srcs - "riscv_termination.sail" - ) - endif() - - # Final file list. - set(sail_srcs - ${sail_arch_srcs} - ${sail_seq_inst_srcs} - ${sail_step_srcs} - "main.sail" - ) - - # Convert to absolute paths, so we can run - - # Generate C code from Sail model with & without RVFI-DII support. - if (NOT variant OR variant STREQUAL "rvfi") - set(c_model_no_ext "${CMAKE_BINARY_DIR}/riscv_model_${arch}") - set(c_model "${c_model_no_ext}.c") - - if (COVERAGE) - set(branch_info_file "${c_model_no_ext}.branch_info") - set(coverage_args "--c-coverage" ${branch_info_file}) - else() - set(branch_info_file) - set(coverage_args) - endif() - - add_custom_command( - DEPENDS ${sail_srcs} - OUTPUT ${c_model} ${branch_info_file} - VERBATIM - COMMENT "Building C code from Sail model (${arch})" - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - COMMAND - ${SAIL_BIN} - # Output file (without extension). - -o ${c_model_no_ext} - # Generate a file containing information about all possible branches. - # See https://github.com/rems-project/sail/blob/sail2/sailcov/README.md - ${coverage_args} - # Don't allow implicit var declaration (like Python). This is - # deprecated because it is error-prone. - --strict-var - # bits('n) is only well-formed if 'n >= 0. - --strict-bitvector - # Minimum required Sail compiler version. - --require-version ${SAIL_REQUIRED_VER} - # Optimisations. - -O --Oconstant-fold - # Cache Z3 results in z3_problems file to speed up incremental compilation. - --memo-z3 - # Output C code. - -c - # Don't generate a main() function. - --c-no-main - # Extra #include's. - --c-include riscv_prelude.h - --c-include riscv_platform.h - # Don't dead-code eliminate these functions. These should match the - # ones used from riscv_sail.h - --c-preserve init_model - --c-preserve try_step - --c-preserve tick_clock - --c-preserve tick_platform - # Preserve RVFI functions. - --c-preserve rvfi_set_instr_packet - --c-preserve rvfi_get_cmd - --c-preserve rvfi_get_insn - --c-preserve rvfi_get_v2_trace_size - --c-preserve rvfi_get_v2_support_packet - --c-preserve rvfi_get_exec_packet_v1 - --c-preserve rvfi_get_exec_packet_v2 - --c-preserve rvfi_get_mem_data - --c-preserve rvfi_get_int_data - --c-preserve rvfi_zero_exec_packet - --c-preserve rvfi_halt_exec_packet - --c-preserve print_instr_packet - --c-preserve print_rvfi_exec - # Input files. - ${sail_srcs} - ) - - add_custom_target(generated_model_${arch} DEPENDS ${c_model}) - endif() - - if (NOT variant) - # Generate JSON snippets file. - set(model_doc "riscv_model_${arch}.json") - - add_custom_command( - DEPENDS ${sail_srcs} - OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/${model_doc}" - VERBATIM - COMMENT "Building documentation JSON from Sail model (${arch})" - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - COMMAND - ${SAIL_BIN} - # Generate JSON documentation file. - --doc - # Format to interpret comments as. You can also use 'asciidoc' - # in which case it will interpret them as Markdown and output them - # as Asciidoc, but there's a bug in the Sail compiler so it can't - # parse the Markdown and it doesn't seem to output the comments - # anyway. - --doc-format identity - # Don't pretty-print the JSON output. It's too big to be readable anyway. - --doc-compact - # Actually embed the code snippets in the JSON as plain text rather - # than referencing them. The other option is base64. - --doc-embed plain - # The directory that the JSON will be saved in. - -o ${CMAKE_CURRENT_BINARY_DIR} - # The name of the JSON file. - --doc-bundle ${model_doc} - # Minimum required Sail compiler version. - --require-version ${SAIL_REQUIRED_VER} - # Input files. - ${sail_srcs} - ) - - add_custom_target(generated_docs_${arch} DEPENDS "${CMAKE_CURRENT_BINARY_DIR}/${model_doc}") - - # Generate smtlib2 code from the Sail code. - # A separate .smt2 file is created for each $property or $counterexample. - # Since the true output files are unknown we need to manually - # generate a file to indicate that we have run this command. - set(smt_stamp_file "${CMAKE_CURRENT_BINARY_DIR}/smt_${arch}.stamp") - add_custom_command( - DEPENDS ${sail_srcs} - VERBATIM - OUTPUT ${smt_stamp_file} - COMMENT "Building smtlib2 from Sail model (${arch})" - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - COMMAND - ${SAIL_BIN} - # Generate SMT files. - --smt - # The prefix of the output files. - -o "${CMAKE_CURRENT_BINARY_DIR}/model" - # Minimum required Sail compiler version. - --require-version ${SAIL_REQUIRED_VER} - --config ${CMAKE_SOURCE_DIR}/config/default.json - # Input files. - ${sail_srcs} - COMMAND ${CMAKE_COMMAND} -E touch ${smt_stamp_file} - ) - - add_custom_target(generated_smt_${arch} DEPENDS ${smt_stamp_file}) - endif() - - if (variant STREQUAL "rmem") - # Generate riscv.lem, riscv_toFromInterp2.ml and riscv.defs - # These are used for "rmem". - add_custom_command( - DEPENDS ${sail_srcs} - VERBATIM - OUTPUT "rmem_${arch}.lem" - COMMENT "Building rmem lem from Sail model (${arch})" - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - COMMAND - ${SAIL_BIN} - # Generate lem files. - --lem - --lem-mwords - --lem-lib Riscv_extras - --lem-lib Riscv_extras_fdext - --lem-lib Mem_metadata - # Output dir for Lem. - --lem-output-dir ${CMAKE_CURRENT_BINARY_DIR} - # Output dir for ISabelle auxiliary theories. - # We do not need the Isabelle .thy files, but sail always generates them. - --isa-output-dir ${CMAKE_CURRENT_BINARY_DIR} - # The prefix of the output files. - -o "lem_${arch}" - # Minimum required Sail compiler version. - --require-version ${SAIL_REQUIRED_VER} - # Input files. - ${sail_srcs} - ) - add_custom_command( - DEPENDS ${sail_srcs} - VERBATIM - OUTPUT "rmem_${arch}_toFromInterp2.ml" - COMMENT "Building rmem toFromInterp2.ml from Sail model (${arch})" - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - COMMAND - ${SAIL_BIN} - --tofrominterp - --tofrominterp-lem - --tofrominterp-mwords - --tofrominterp-output-dir ${CMAKE_CURRENT_BINARY_DIR} - # The prefix of the output files. - -o "rmem_${arch}" - # Minimum required Sail compiler version. - --require-version ${SAIL_REQUIRED_VER} - # Input files. - ${sail_srcs} - ) - add_custom_command( - DEPENDS ${sail_srcs} - VERBATIM - OUTPUT "rmem_${arch}.defs" - COMMENT "Building rmem defs from Sail model (${arch})" - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - COMMAND - ${SAIL_BIN} - --marshal - # The prefix of the output files. - -o "rmem_${arch}" - # Minimum required Sail compiler version. - --require-version ${SAIL_REQUIRED_VER} - # Input files. - ${sail_srcs} - ) - - add_custom_target(generated_rmem_${arch} DEPENDS - "rmem_${arch}.lem" - "rmem_${arch}_toFromInterp2.ml" - "rmem_${arch}.defs" - ) - endif() - - # Build Rocq (formerly Coq) definitions. - if (variant STREQUAL "rocq") - add_custom_command( - DEPENDS ${sail_srcs} - VERBATIM - OUTPUT "${CMAKE_BINARY_DIR}/rocq/${arch}.v" "${CMAKE_BINARY_DIR}/rocq/${arch}_types.v" - COMMENT "Building Rocq definitions from Sail model (${arch})" - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - COMMAND - ${SAIL_BIN} - --dcoq-undef-axioms - --coq - --coq-lib riscv_extras - --coq-lib mem_metadata - --coq-output-dir "${CMAKE_BINARY_DIR}/rocq" - # The prefix of the output files. - -o "${arch}" - --config ${CMAKE_SOURCE_DIR}/config/default.json - # Minimum required Sail compiler version. - --require-version ${SAIL_REQUIRED_VER} - # Input files. - ${sail_srcs} - ) - add_custom_command( - DEPENDS build_rocq_common "${CMAKE_BINARY_DIR}/rocq/${arch}.v" "${CMAKE_BINARY_DIR}/rocq/${arch}_types.v" - VERBATIM - OUTPUT "${CMAKE_BINARY_DIR}/rocq/${arch}.vo" "${CMAKE_BINARY_DIR}/rocq/${arch}_types.vo" - COMMENT "Building Rocq definitions from Sail model (${arch})" - WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/rocq" - COMMAND - coqc - -R . Riscv - "${arch}_types.v" - COMMAND - coqc - -R . Riscv - "${arch}.v" - ) - add_custom_target(generated_rocq_${arch} DEPENDS "${CMAKE_BINARY_DIR}/rocq/${arch}.v") - add_custom_target(build_rocq_${arch} DEPENDS "${CMAKE_BINARY_DIR}/rocq/${arch}.vo") - endif() - - # Build Lean definitions - if (variant STREQUAL "lean") - string(TOUPPER ${arch} arch_uppercase) - add_custom_command( - DEPENDS ${sail_srcs} - VERBATIM - OUTPUT "lean_${arch_uppercase}.lean" - COMMENT "Building Lean definitions from Sail model (${arch})" - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - COMMAND - ${SAIL_BIN} - --lean - --memo-z3 - --require-version ${SAIL_REQUIRED_VER} - --lean-output-dir ${CMAKE_CURRENT_BINARY_DIR} - --lean-force-output - --lean-noncomputable - --lean-noncomputable-function encdec_forwards - --lean-noncomputable-function encdec_backwards - --lean-noncomputable-function encdec_forwards_matches - --lean-noncomputable-function encdec_backwards_matches - --lean-noncomputable-function encdec_compressed_forwards - --lean-noncomputable-function encdec_compressed_backwards - --lean-noncomputable-function encdec_compressed_forwards_matches - --lean-noncomputable-function encdec_compressed_backwards_matches - --lean-import-file ../handwritten_support/RiscvExtras.lean - --config ${CMAKE_SOURCE_DIR}/config/default.json - -o "Lean_${arch_uppercase}" - ${sail_srcs} - ) - - add_custom_target(generated_lean_${arch} DEPENDS "lean_${arch_uppercase}.lean") - endif() - - # Build Lem definitions, en route to Isabelle or HOL4. - if (variant STREQUAL "lem") - string_upper_initial("${arch}" arch_thy) - add_custom_command( - DEPENDS ${sail_srcs} ${CMAKE_SOURCE_DIR}/config/default.json - VERBATIM - OUTPUT "${arch}.lem" "${arch}_types.lem" "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}_lemmas.thy" - COMMENT "Building Lem definitions from Sail model (${arch})" - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - COMMAND - ${SAIL_BIN} - --lem - --lem-lib Riscv_extras - --lem-lib Riscv_extras_fdext - --lem-output-dir ${CMAKE_CURRENT_BINARY_DIR} - # Sail also produces a lemmas file just for Isabelle - --isa-output-dir "${CMAKE_BINARY_DIR}/isabelle/${arch}" - # The prefix of the output files. - -o "${arch}" - # Minimum required Sail compiler version. - --require-version ${SAIL_REQUIRED_VER} - --config ${CMAKE_SOURCE_DIR}/config/default.json - # Input files. - ${sail_srcs} - COMMAND - echo - "declare {isabelle} rename field sync_exception_ext = sync_exception_ext_exception" - >> - ${CMAKE_CURRENT_BINARY_DIR}/${arch}_types.lem - - ) - add_custom_target(generated_lem_${arch} DEPENDS "${arch}.lem") - endif() - - # Build Isabelle definitions from Lem - if (variant STREQUAL "isabelle") - string_upper_initial("${arch}" arch_thy) - file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/isabelle/${arch}") - add_custom_command( - DEPENDS "${arch}.lem" "${arch}_types.lem" - VERBATIM - OUTPUT "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}.thy" "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}_types.thy" - COMMENT "Building Isabelle definitions from Lem definitions (${arch})" - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMAND - lem - -no_lifting_toplevel_match_for ${arch_thy}_types.ast - -wl ign - -isa - -outdir ${CMAKE_BINARY_DIR}/isabelle/${arch} - -lib Sail=${sail_dir}/src/gen_lib - ${CMAKE_SOURCE_DIR}/handwritten_support/riscv_extras.lem - ${CMAKE_SOURCE_DIR}/handwritten_support/riscv_extras_fdext.lem - ${arch}_types.lem - ${arch}.lem - COMMAND - sed - -e "s/datatype ast/datatype (plugins only: size) ast/" - -e "s/record( 'asidlen, 'valen, 'palen, 'ptelen) TLB_Entry/record (overloaded) ( 'asidlen, 'valen, 'palen, 'ptelen) TLB_Entry/" - "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}_types.thy" - > - "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}_types.thy.new" - COMMAND - mv - "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}_types.thy.new" - "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}_types.thy" - COMMAND - sed - -e "s/by pat_completeness auto/by pat_completeness (auto intro!: let_cong bind_cong result.case_cong)/" - -e "s/WriteRAM_Meta addr width meta/WriteRAM_Meta addr width ()/" - "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}.thy" - > - "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}.thy.new" - COMMAND - mv - "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}.thy.new" - "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}.thy" - COMMAND - sed - "s/%ARCH%/${arch_thy}/" - "${CMAKE_SOURCE_DIR}/handwritten_support/ROOT.in" - > - "${CMAKE_BINARY_DIR}/isabelle/${arch}/ROOT" - ) - add_custom_target(generated_isabelle_${arch} DEPENDS "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}.thy") - endif() - endforeach() - endforeach() +foreach (variant IN ITEMS "" "rvfi" "rocq" "rmem" "lean") + set(arch "rv") + if (variant STREQUAL "rvfi") + string(APPEND arch "_${variant}") + endif() + + # Instruction sources, depending on target + set(sail_check_srcs + "riscv_addr_checks_common.sail" + "riscv_addr_checks.sail" + "riscv_misa_ext.sail" + ) + + set(vext_srcs + "riscv_insts_vext_utils.sail" + "riscv_insts_vext_fp_utils.sail" + "riscv_insts_vext_vset.sail" + "riscv_insts_vext_arith.sail" + "riscv_insts_vext_fp.sail" + "riscv_insts_vext_mem.sail" + "riscv_insts_vext_mask.sail" + "riscv_insts_vext_vm.sail" + "riscv_insts_vext_fp_vm.sail" + "riscv_insts_vext_red.sail" + "riscv_insts_vext_fp_red.sail" + ) + + set(sail_default_inst + "riscv_insts_base.sail" + "riscv_insts_zifencei.sail" + "riscv_insts_aext.sail" + "riscv_insts_zca.sail" + "riscv_insts_mext.sail" + "riscv_insts_zicsr.sail" + "riscv_insts_hints.sail" + "riscv_insts_fext.sail" + "riscv_insts_zcf.sail" + "riscv_insts_dext.sail" + "riscv_insts_zcd.sail" + "riscv_insts_svinval.sail" + "riscv_insts_zba.sail" + "riscv_insts_zbb.sail" + "riscv_insts_zbc.sail" + "riscv_insts_zbs.sail" + "riscv_insts_zcb.sail" + "riscv_insts_zfh.sail" + # Zfa needs to be added after fext, dext and Zfh (as it needs + # definitions from those) + "riscv_insts_zfa.sail" + "riscv_insts_zkn.sail" + "riscv_insts_zks.sail" + "riscv_insts_zbkb.sail" + "riscv_insts_zbkx.sail" + "riscv_insts_zicond.sail" + ${vext_srcs} + "riscv_insts_zicbom.sail" + "riscv_insts_zicboz.sail" + "riscv_insts_zvbb.sail" + "riscv_insts_zvbc.sail" + "riscv_insts_zvknhab.sail" + # Zimop and Zcmop should be at the end so they can be overridden by earlier extensions + "riscv_insts_zimop.sail" + "riscv_insts_zcmop.sail" + ) + + if (variant STREQUAL "rmem") + set(sail_seq_inst + ${sail_default_inst} + "riscv_jalr_rmem.sail" + "riscv_insts_rmem.sail" + ) + else() + set(sail_seq_inst + ${sail_default_inst} + "riscv_jalr_seq.sail" + ) + endif() + + set(sail_seq_inst_srcs + "riscv_insts_begin.sail" + ${sail_seq_inst} + "riscv_insts_end.sail" + "riscv_csr_end.sail" + ) + + set(sail_sys_srcs + "riscv_vext_control.sail" + "riscv_sys_exceptions.sail" + "riscv_sync_exception.sail" + "riscv_zihpm.sail" + "riscv_sscofpmf.sail" + "riscv_zkr_control.sail" + "riscv_zicntr_control.sail" + "riscv_softfloat_interface.sail" + "riscv_fdext_regs.sail" + "riscv_fdext_control.sail" + "riscv_smcntrpmf.sail" + "riscv_sys_control.sail" + ) + + set(sail_vm_srcs + "riscv_vmem_pte.sail" + "riscv_vmem_ptw.sail" + "riscv_vmem_tlb.sail" + "riscv_vmem.sail" + ) + + set(prelude + "prelude.sail" + "riscv_errors.sail" + "riscv_xlen.sail" + "riscv_flen.sail" + "riscv_vlen.sail" + "prelude_mem_addrtype.sail" + "prelude_mem_metadata.sail" + "prelude_mem.sail" + "arithmetic.sail" + ) + + if (variant STREQUAL "rvfi") + list(APPEND prelude "rvfi_dii.sail") + endif() + + set(sail_regs_srcs + "riscv_csr_begin.sail" + "riscv_reg_type.sail" + "riscv_freg_type.sail" + "riscv_regs.sail" + "riscv_pc_access.sail" + "riscv_sys_regs.sail" + "riscv_pmp_regs.sail" + "riscv_pmp_control.sail" + "riscv_ext_regs.sail" + ${sail_check_srcs} + "riscv_vreg_type.sail" + "riscv_vext_regs.sail" + ) + + set(sail_arch_srcs + ${prelude} + "riscv_extensions.sail" + "riscv_types_common.sail" + "riscv_types_ext.sail" + "riscv_types.sail" + "riscv_vmem_types.sail" + ${sail_regs_srcs} + ${sail_sys_srcs} + "riscv_platform.sail" + "riscv_mem.sail" + ${sail_vm_srcs} + # Shared/common code for the cryptography extension. + "riscv_types_kext.sail" + "riscv_zvk_utils.sail" + "riscv_inst_retire.sail" + ) + + if (variant STREQUAL "rvfi") + set(riscv_step_ext "riscv_step_rvfi.sail") + set(riscv_fetch "riscv_fetch_rvfi.sail") + else() + set(riscv_step_ext "riscv_step_ext.sail") + set(riscv_fetch "riscv_fetch.sail") + endif() + + set(sail_step_srcs + "riscv_step_common.sail" + ${riscv_step_ext} + "riscv_decode_ext.sail" + ${riscv_fetch} + "riscv_step.sail" + ) + + if (variant STREQUAL "rocq" OR variant STREQUAL "lean") + list(APPEND sail_step_srcs + "riscv_termination.sail" + ) + endif() + + # Final file list. + set(sail_srcs + ${sail_arch_srcs} + ${sail_seq_inst_srcs} + ${sail_step_srcs} + "main.sail" + ) + + # Generate C code from Sail model with & without RVFI-DII support. + if (NOT variant OR variant STREQUAL "rvfi") + set(c_model_no_ext "${CMAKE_BINARY_DIR}/riscv_model_${arch}") + set(c_model "${c_model_no_ext}.c") + + if (COVERAGE) + set(branch_info_file "${c_model_no_ext}.branch_info") + set(coverage_args "--c-coverage" ${branch_info_file}) + else() + set(branch_info_file) + set(coverage_args) + endif() + + add_custom_command( + DEPENDS ${sail_srcs} + OUTPUT ${c_model} ${branch_info_file} + VERBATIM + COMMENT "Building C code from Sail model (${arch})" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMAND + ${SAIL_BIN} + # Output file (without extension). + -o ${c_model_no_ext} + # Generate a file containing information about all possible branches. + # See https://github.com/rems-project/sail/blob/sail2/sailcov/README.md + ${coverage_args} + # Don't allow implicit var declaration (like Python). This is + # deprecated because it is error-prone. + --strict-var + # bits('n) is only well-formed if 'n >= 0. + --strict-bitvector + # Minimum required Sail compiler version. + --require-version ${SAIL_REQUIRED_VER} + # Optimisations. + -O --Oconstant-fold + # Cache Z3 results in z3_problems file to speed up incremental compilation. + --memo-z3 + # Output C code. + -c + # Don't generate a main() function. + --c-no-main + # Extra #include's. + --c-include riscv_prelude.h + --c-include riscv_platform.h + # Don't dead-code eliminate these functions. These should match the + # ones used from riscv_sail.h + --c-preserve init_model + --c-preserve try_step + --c-preserve tick_clock + --c-preserve tick_platform + --c-preserve force_pc + # Preserve RVFI functions. + --c-preserve rvfi_set_instr_packet + --c-preserve rvfi_get_cmd + --c-preserve rvfi_get_insn + --c-preserve rvfi_get_v2_trace_size + --c-preserve rvfi_get_v2_support_packet + --c-preserve rvfi_get_exec_packet_v1 + --c-preserve rvfi_get_exec_packet_v2 + --c-preserve rvfi_get_mem_data + --c-preserve rvfi_get_int_data + --c-preserve rvfi_zero_exec_packet + --c-preserve rvfi_halt_exec_packet + --c-preserve print_instr_packet + --c-preserve print_rvfi_exec + # Input files. + ${sail_srcs} + ) + + add_custom_target(generated_model_${arch} DEPENDS ${c_model}) + endif() + + if (NOT variant) + # Generate JSON snippets file. + set(model_doc "riscv_model_${arch}.json") + + add_custom_command( + DEPENDS ${sail_srcs} + OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/${model_doc}" + VERBATIM + COMMENT "Building documentation JSON from Sail model (${arch})" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMAND + ${SAIL_BIN} + # Generate JSON documentation file. + --doc + # Format to interpret comments as. You can also use 'asciidoc' + # in which case it will interpret them as Markdown and output them + # as Asciidoc, but there's a bug in the Sail compiler so it can't + # parse the Markdown and it doesn't seem to output the comments + # anyway. + --doc-format identity + # Don't pretty-print the JSON output. It's too big to be readable anyway. + --doc-compact + # Actually embed the code snippets in the JSON as plain text rather + # than referencing them. The other option is base64. + --doc-embed plain + # The directory that the JSON will be saved in. + -o ${CMAKE_CURRENT_BINARY_DIR} + # The name of the JSON file. + --doc-bundle ${model_doc} + # Minimum required Sail compiler version. + --require-version ${SAIL_REQUIRED_VER} + # Input files. + ${sail_srcs} + ) + + add_custom_target(generated_docs_${arch} DEPENDS "${CMAKE_CURRENT_BINARY_DIR}/${model_doc}") + + # Generate smtlib2 code from the Sail code. + # A separate .smt2 file is created for each $property or $counterexample. + # Since the true output files are unknown we need to manually + # generate a file to indicate that we have run this command. + set(smt_stamp_file "${CMAKE_CURRENT_BINARY_DIR}/smt_${arch}.stamp") + add_custom_command( + DEPENDS ${sail_srcs} + VERBATIM + OUTPUT ${smt_stamp_file} + COMMENT "Building smtlib2 from Sail model (${arch})" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMAND + ${SAIL_BIN} + # Generate SMT files. + --smt + # The prefix of the output files. + -o "${CMAKE_CURRENT_BINARY_DIR}/model" + # Minimum required Sail compiler version. + --require-version ${SAIL_REQUIRED_VER} + --config ${CMAKE_SOURCE_DIR}/config/default.json + # Input files. + ${sail_srcs} + COMMAND ${CMAKE_COMMAND} -E touch ${smt_stamp_file} + ) + + add_custom_target(generated_smt_${arch} DEPENDS ${smt_stamp_file}) + endif() + + if (variant STREQUAL "rmem") + # Generate riscv.lem, riscv_toFromInterp2.ml and riscv.defs + # These are used for "rmem". + add_custom_command( + DEPENDS ${sail_srcs} + VERBATIM + OUTPUT "rmem_${arch}.lem" + COMMENT "Building rmem lem from Sail model (${arch})" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMAND + ${SAIL_BIN} + # Generate lem files. + --lem + --lem-mwords + --lem-lib Riscv_extras + --lem-lib Riscv_extras_fdext + --lem-lib Mem_metadata + # Output dir for Lem. + --lem-output-dir ${CMAKE_CURRENT_BINARY_DIR} + # Output dir for ISabelle auxiliary theories. + # We do not need the Isabelle .thy files, but sail always generates them. + --isa-output-dir ${CMAKE_CURRENT_BINARY_DIR} + # The prefix of the output files. + -o "lem_${arch}" + # Minimum required Sail compiler version. + --require-version ${SAIL_REQUIRED_VER} + # Input files. + ${sail_srcs} + ) + add_custom_command( + DEPENDS ${sail_srcs} + VERBATIM + OUTPUT "rmem_${arch}_toFromInterp2.ml" + COMMENT "Building rmem toFromInterp2.ml from Sail model (${arch})" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMAND + ${SAIL_BIN} + --tofrominterp + --tofrominterp-lem + --tofrominterp-mwords + --tofrominterp-output-dir ${CMAKE_CURRENT_BINARY_DIR} + # The prefix of the output files. + -o "rmem_${arch}" + # Minimum required Sail compiler version. + --require-version ${SAIL_REQUIRED_VER} + # Input files. + ${sail_srcs} + ) + add_custom_command( + DEPENDS ${sail_srcs} + VERBATIM + OUTPUT "rmem_${arch}.defs" + COMMENT "Building rmem defs from Sail model (${arch})" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMAND + ${SAIL_BIN} + --marshal + # The prefix of the output files. + -o "rmem_${arch}" + # Minimum required Sail compiler version. + --require-version ${SAIL_REQUIRED_VER} + # Input files. + ${sail_srcs} + ) + + add_custom_target(generated_rmem_${arch} DEPENDS + "rmem_${arch}.lem" + "rmem_${arch}_toFromInterp2.ml" + "rmem_${arch}.defs" + ) + endif() + + # Build Rocq (formerly Coq) definitions. + if (variant STREQUAL "rocq") + add_custom_command( + DEPENDS ${sail_srcs} + VERBATIM + OUTPUT "${CMAKE_BINARY_DIR}/rocq/${arch}.v" "${CMAKE_BINARY_DIR}/rocq/${arch}_types.v" + COMMENT "Building Rocq definitions from Sail model (${arch})" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMAND + ${SAIL_BIN} + --dcoq-undef-axioms + --coq + --coq-lib riscv_extras + --coq-lib mem_metadata + --coq-output-dir "${CMAKE_BINARY_DIR}/rocq" + # The prefix of the output files. + -o "${arch}" + --config ${CMAKE_SOURCE_DIR}/config/default.json + # Minimum required Sail compiler version. + --require-version ${SAIL_REQUIRED_VER} + # Input files. + ${sail_srcs} + ) + add_custom_command( + DEPENDS build_rocq_common "${CMAKE_BINARY_DIR}/rocq/${arch}.v" "${CMAKE_BINARY_DIR}/rocq/${arch}_types.v" + VERBATIM + OUTPUT "${CMAKE_BINARY_DIR}/rocq/${arch}.vo" "${CMAKE_BINARY_DIR}/rocq/${arch}_types.vo" + COMMENT "Building Rocq definitions from Sail model (${arch})" + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/rocq" + COMMAND + coqc + -R . Riscv + "${arch}_types.v" + COMMAND + coqc + -R . Riscv + "${arch}.v" + ) + add_custom_target(generated_rocq_${arch} DEPENDS "${CMAKE_BINARY_DIR}/rocq/${arch}.v") + add_custom_target(build_rocq_${arch} DEPENDS "${CMAKE_BINARY_DIR}/rocq/${arch}.vo") + endif() + + # Build Lean definitions + if (variant STREQUAL "lean") + string(TOUPPER ${arch} arch_uppercase) + add_custom_command( + DEPENDS ${sail_srcs} + VERBATIM + OUTPUT "lean_${arch_uppercase}.lean" + COMMENT "Building Lean definitions from Sail model (${arch})" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMAND + ${SAIL_BIN} + --lean + --memo-z3 + --require-version ${SAIL_REQUIRED_VER} + --lean-output-dir ${CMAKE_CURRENT_BINARY_DIR} + --lean-force-output + --lean-noncomputable + --lean-noncomputable-function encdec_forwards + --lean-noncomputable-function encdec_backwards + --lean-noncomputable-function encdec_forwards_matches + --lean-noncomputable-function encdec_backwards_matches + --lean-noncomputable-function encdec_compressed_forwards + --lean-noncomputable-function encdec_compressed_backwards + --lean-noncomputable-function encdec_compressed_forwards_matches + --lean-noncomputable-function encdec_compressed_backwards_matches + --lean-import-file ../handwritten_support/RiscvExtras.lean + --config ${CMAKE_SOURCE_DIR}/config/default.json + -o "Lean_${arch_uppercase}" + ${sail_srcs} + ) + + add_custom_target(generated_lean_${arch} DEPENDS "lean_${arch_uppercase}.lean") + endif() + + # Build Lem definitions, en route to Isabelle or HOL4. + if (variant STREQUAL "lem") + string_upper_initial("${arch}" arch_thy) + add_custom_command( + DEPENDS ${sail_srcs} ${CMAKE_SOURCE_DIR}/config/default.json + VERBATIM + OUTPUT "${arch}.lem" "${arch}_types.lem" "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}_lemmas.thy" + COMMENT "Building Lem definitions from Sail model (${arch})" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMAND + ${SAIL_BIN} + --lem + --lem-lib Riscv_extras + --lem-lib Riscv_extras_fdext + --lem-output-dir ${CMAKE_CURRENT_BINARY_DIR} + # Sail also produces a lemmas file just for Isabelle + --isa-output-dir "${CMAKE_BINARY_DIR}/isabelle/${arch}" + # The prefix of the output files. + -o "${arch}" + # Minimum required Sail compiler version. + --require-version ${SAIL_REQUIRED_VER} + --config ${CMAKE_SOURCE_DIR}/config/default.json + # Input files. + ${sail_srcs} + COMMAND + echo + "declare {isabelle} rename field sync_exception_ext = sync_exception_ext_exception" + >> + ${CMAKE_CURRENT_BINARY_DIR}/${arch}_types.lem + + ) + add_custom_target(generated_lem_${arch} DEPENDS "${arch}.lem") + endif() + + # Build Isabelle definitions from Lem + if (variant STREQUAL "isabelle") + string_upper_initial("${arch}" arch_thy) + file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/isabelle/${arch}") + add_custom_command( + DEPENDS "${arch}.lem" "${arch}_types.lem" + VERBATIM + OUTPUT "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}.thy" "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}_types.thy" + COMMENT "Building Isabelle definitions from Lem definitions (${arch})" + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + COMMAND + lem + -no_lifting_toplevel_match_for ${arch_thy}_types.ast + -wl ign + -isa + -outdir ${CMAKE_BINARY_DIR}/isabelle/${arch} + -lib Sail=${sail_dir}/src/gen_lib + ${CMAKE_SOURCE_DIR}/handwritten_support/riscv_extras.lem + ${CMAKE_SOURCE_DIR}/handwritten_support/riscv_extras_fdext.lem + ${arch}_types.lem + ${arch}.lem + COMMAND + sed + -e "s/datatype ast/datatype (plugins only: size) ast/" + -e "s/record( 'asidlen, 'valen, 'palen, 'ptelen) TLB_Entry/record (overloaded) ( 'asidlen, 'valen, 'palen, 'ptelen) TLB_Entry/" + "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}_types.thy" + > + "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}_types.thy.new" + COMMAND + mv + "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}_types.thy.new" + "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}_types.thy" + COMMAND + sed + -e "s/by pat_completeness auto/by pat_completeness (auto intro!: let_cong bind_cong result.case_cong)/" + -e "s/WriteRAM_Meta addr width meta/WriteRAM_Meta addr width ()/" + "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}.thy" + > + "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}.thy.new" + COMMAND + mv + "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}.thy.new" + "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}.thy" + COMMAND + sed + "s/%ARCH%/${arch_thy}/" + "${CMAKE_SOURCE_DIR}/handwritten_support/ROOT.in" + > + "${CMAKE_BINARY_DIR}/isabelle/${arch}/ROOT" + ) + add_custom_target(generated_isabelle_${arch} DEPENDS "${CMAKE_BINARY_DIR}/isabelle/${arch}/${arch_thy}.thy") + endif() endforeach() diff --git a/model/riscv_extensions.sail b/model/riscv_extensions.sail index f0c83a51b..01bc4a3e7 100644 --- a/model/riscv_extensions.sail +++ b/model/riscv_extensions.sail @@ -32,10 +32,12 @@ enum clause extension = Ext_A function clause hartSupports(Ext_A) = config extensions.A.supported // Single-Precision Floating-Point enum clause extension = Ext_F -function clause hartSupports(Ext_F) = config extensions.FD.supported +function clause hartSupports(Ext_F) = config extensions.F.supported // Double-Precision Floating-Point +// TODO: Ideally we'd use `config extensions.D.supported` here but it doesn't +// work due to https://github.com/rems-project/sail/issues/1255 enum clause extension = Ext_D -function clause hartSupports(Ext_D) = config extensions.FD.supported // TODO: Separate F and D supported flags +function clause hartSupports(Ext_D) = constraint(ext_d_supported) & hartSupports(Ext_F) // Bit Manipulation enum clause extension = Ext_B function clause hartSupports(Ext_B) = config extensions.B.supported diff --git a/model/riscv_flen.sail b/model/riscv_flen.sail index 99d9a85e5..30458e879 100644 --- a/model/riscv_flen.sail +++ b/model/riscv_flen.sail @@ -6,6 +6,11 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ +// This is only a type because `if (config extensions.D.supported : bool) then 8 else 4` +// gives a syntax error: https://github.com/rems-project/sail/issues/1256 +type ext_d_supported : Bool = config extensions.D.supported +type flen_bytes : Int = if ext_d_supported then 8 else 4 + type flen : Int = flen_bytes * 8 type flenbits = bits(flen) diff --git a/model/riscv_flen_D.sail b/model/riscv_flen_D.sail deleted file mode 100644 index 613bd07ff..000000000 --- a/model/riscv_flen_D.sail +++ /dev/null @@ -1,11 +0,0 @@ -/*=======================================================================================*/ -/* This Sail RISC-V architecture model, comprising all files and */ -/* directories except where otherwise noted is subject the BSD */ -/* two-clause license in the LICENSE file. */ -/* */ -/* SPDX-License-Identifier: BSD-2-Clause */ -/*=======================================================================================*/ - -/* Define the FLEN value for the 'D' extension. */ - -type flen_bytes : Int = 8 diff --git a/model/riscv_flen_F.sail b/model/riscv_flen_F.sail deleted file mode 100644 index b3fdeecaf..000000000 --- a/model/riscv_flen_F.sail +++ /dev/null @@ -1,11 +0,0 @@ -/*=======================================================================================*/ -/* This Sail RISC-V architecture model, comprising all files and */ -/* directories except where otherwise noted is subject the BSD */ -/* two-clause license in the LICENSE file. */ -/* */ -/* SPDX-License-Identifier: BSD-2-Clause */ -/*=======================================================================================*/ - -/* Define the FLEN value for the 'F' extension. */ - -type flen_bytes : Int = 4 diff --git a/model/riscv_pc_access.sail b/model/riscv_pc_access.sail index 018512336..af0120104 100644 --- a/model/riscv_pc_access.sail +++ b/model/riscv_pc_access.sail @@ -30,3 +30,8 @@ val tick_pc : unit -> unit function tick_pc() = { PC = nextPC } + +// For forcing PC from C. This is ugly. +function force_pc(pc : bits(64)) -> unit = { + PC = truncate(pc, xlen); +} diff --git a/model/riscv_platform.sail b/model/riscv_platform.sail index 36788a362..33a09725f 100644 --- a/model/riscv_platform.sail +++ b/model/riscv_platform.sail @@ -54,8 +54,9 @@ function plat_clint_base() -> physaddrbits = to_bits(physaddrbits_len, config pl function plat_clint_size() -> physaddrbits = to_bits(physaddrbits_len, config platform.clint.size : int) /* Location of HTIF ports */ -val plat_htif_tohost = pure {c: "plat_htif_tohost", lem: "plat_htif_tohost"} : unit -> physaddrbits -function plat_htif_tohost () = to_bits(physaddrbits_len, elf_tohost ()) +val plat_htif_tohost = pure {c: "plat_htif_tohost", lem: "plat_htif_tohost"} : unit -> bits(64) +function htif_tohost_base() -> physaddrbits = truncate(plat_htif_tohost(), physaddrbits_len) + // todo: fromhost /* Physical memory map predicates */ @@ -101,10 +102,10 @@ function within_clint forall 'n, 0 < 'n <= max_mem_access . (Physaddr(addr) : ph } function within_htif_writable forall 'n, 0 < 'n <= max_mem_access . (Physaddr(addr) : physaddr, width : int('n)) -> bool = - plat_htif_tohost() == addr | (plat_htif_tohost() + 4 == addr & width == 4) + htif_tohost_base() == addr | (htif_tohost_base() + 4 == addr & width == 4) function within_htif_readable forall 'n, 0 < 'n <= max_mem_access . (Physaddr(addr) : physaddr, width : int('n)) -> bool = - plat_htif_tohost() == addr | (plat_htif_tohost() + 4 == addr & width == 4) + htif_tohost_base() == addr | (htif_tohost_base() + 4 == addr & width == 4) /* CLINT (Core Local Interruptor), based on Spike. */ @@ -314,11 +315,11 @@ function htif_load(t, Physaddr(paddr), width) = { if get_config_print_platform() then print_platform("htif[" ^ hex_bits_str(paddr) ^ "] -> " ^ BitStr(htif_tohost)); /* FIXME: For now, only allow the expected access widths. */ - if width == 8 & (paddr == plat_htif_tohost()) + if width == 8 & (paddr == htif_tohost_base()) then Ok(zero_extend(64, htif_tohost)) /* FIXME: Redundant zero_extend currently required by Lem backend */ - else if width == 4 & paddr == plat_htif_tohost() + else if width == 4 & paddr == htif_tohost_base() then Ok(zero_extend(32, htif_tohost[31..0])) /* FIXME: Redundant zero_extend currently required by Lem backend */ - else if width == 4 & paddr == plat_htif_tohost() + 4 + else if width == 4 & paddr == htif_tohost_base() + 4 then Ok(zero_extend(32, htif_tohost[63..32])) /* FIXME: Redundant zero_extend currently required by Lem backend */ else match t { InstructionFetch() => Err(E_Fetch_Access_Fault()), @@ -336,12 +337,12 @@ function htif_store(Physaddr(paddr), width, data) = { then { htif_cmd_write = bitone; htif_payload_writes = htif_payload_writes + 1; htif_tohost = zero_extend(data) } - else if width == 4 & paddr == plat_htif_tohost() + else if width == 4 & paddr == htif_tohost_base() then { if data == htif_tohost[31 .. 0] then htif_payload_writes = htif_payload_writes + 1 else htif_payload_writes = 0x1; htif_tohost = vector_update_subrange(htif_tohost, 31, 0, data) } - else if width == 4 & paddr == plat_htif_tohost() + 4 + else if width == 4 & paddr == htif_tohost_base() + 4 then { if data[15 .. 0] == htif_tohost[47 .. 32] then htif_payload_writes = htif_payload_writes + 1 else htif_payload_writes = 0x1; diff --git a/model/riscv_xlen.sail b/model/riscv_xlen.sail index 7b51f3f8d..6b83489a8 100644 --- a/model/riscv_xlen.sail +++ b/model/riscv_xlen.sail @@ -6,18 +6,32 @@ /* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ -type log2_xlen : Int = log2_xlen_bytes + 3 -type xlen_bytes : Int = 2 ^ log2_xlen_bytes -type xlen : Int = xlen_bytes * 8 -type xlenbits = bits(xlen) +// Define the XLEN value for the architecture. +// This is done using the smallest/most logarithmic possible value since Sail's +// type system works well for multiply and 2^ but not divide and log2. + +type xlen : Int = config base.xlen +constraint xlen in {32, 64} + +type log2_xlen : Int = if xlen == 32 then 5 else 6 +type xlen_bytes : Int = if xlen == 32 then 4 else 8 + +// TODO: Allow configuring a lower number of physical address bits. +// For example it is unlikely that serious RV64 implementations really +// have 64 physical address bits. +type physaddrbits_len : Int = if xlen == 32 then 34 else 64 + +// This is the maximum; designs can implement shorter ASIDLENs. +// TODO: Allow configuring shorter ASIDLENs. +type asidlen : Int = if xlen == 32 then 9 else 16 // Variable versions of the above types. Variables and types // are disjoint in Sail so they are allowed to have the same name. // This saves typing `sizeof()` everywhere. let log2_xlen = sizeof(log2_xlen) -let log2_xlen_bytes = sizeof(log2_xlen_bytes) let xlen_bytes = sizeof(xlen_bytes) let xlen = sizeof(xlen) +let asidlen = sizeof(asidlen) -let asidlen = sizeof(asidlen) -type asidbits = bits(asidlen) +type xlenbits = bits(xlen) +type asidbits = bits(asidlen) diff --git a/model/riscv_xlen32.sail b/model/riscv_xlen32.sail deleted file mode 100644 index 38dc8c6ce..000000000 --- a/model/riscv_xlen32.sail +++ /dev/null @@ -1,17 +0,0 @@ -/*=======================================================================================*/ -/* This Sail RISC-V architecture model, comprising all files and */ -/* directories except where otherwise noted is subject the BSD */ -/* two-clause license in the LICENSE file. */ -/* */ -/* SPDX-License-Identifier: BSD-2-Clause */ -/*=======================================================================================*/ - -// Define the XLEN value for the architecture. -// This is done using the smallest/most logarithmic possible value since Sail's -// type system works well for multiply and 2^ but not divide and log2. -type log2_xlen_bytes : Int = 2 - -type physaddrbits_len : Int = 34 - -// This is the maximum; designs can implement shorter ASIDLENs. -type asidlen : Int = 9 diff --git a/model/riscv_xlen64.sail b/model/riscv_xlen64.sail deleted file mode 100644 index 5d92cb625..000000000 --- a/model/riscv_xlen64.sail +++ /dev/null @@ -1,17 +0,0 @@ -/*=======================================================================================*/ -/* This Sail RISC-V architecture model, comprising all files and */ -/* directories except where otherwise noted is subject the BSD */ -/* two-clause license in the LICENSE file. */ -/* */ -/* SPDX-License-Identifier: BSD-2-Clause */ -/*=======================================================================================*/ - -// Define the XLEN value for the architecture. -// This is done using the smallest/most logarithmic possible value since Sail's -// type system works well for multiply and 2^ but not divide and log2. -type log2_xlen_bytes : Int = 3 - -type physaddrbits_len : Int = 64 - -// This is the maximum; designs can implement shorter ASIDLENs. -type asidlen : Int = 16 diff --git a/test/first_party/CMakeLists.txt b/test/first_party/CMakeLists.txt index bc6ad56a5..f169af02f 100644 --- a/test/first_party/CMakeLists.txt +++ b/test/first_party/CMakeLists.txt @@ -89,16 +89,18 @@ set(tests ) foreach (xlen IN ITEMS 32 64) + set(default_config "${CMAKE_SOURCE_DIR}/config/rv${xlen}d.json") + foreach (test_source IN LISTS tests) - set(arch "rv${xlen}d") + set(arch "rv") if (xlen EQUAL 32) set(mabi "ilp32") else() set(mabi "lp64") endif() - set(elf "${arch}_${test_source}.elf") - set(config "${arch}_${test_source}.json") + set(elf "${arch}_${xlen}_${test_source}.elf") + set(config "${arch}_${xlen}_${test_source}.json") add_custom_command( OUTPUT ${elf} @@ -145,11 +147,11 @@ foreach (xlen IN ITEMS 32 64) add_custom_command( OUTPUT ${config} DEPENDS - "${CMAKE_SOURCE_DIR}/config/default.json" + ${default_config} "${CMAKE_CURRENT_SOURCE_DIR}/src/${test_source}.filter" COMMAND jq -f "${CMAKE_CURRENT_SOURCE_DIR}/src/${test_source}.filter" - "${CMAKE_SOURCE_DIR}/config/default.json" + ${default_config} > ${config} VERBATIM COMMENT "Creating ${config}" @@ -158,18 +160,18 @@ foreach (xlen IN ITEMS 32 64) add_custom_command( OUTPUT ${config} DEPENDS - "${CMAKE_SOURCE_DIR}/config/default.json" + ${default_config} COMMAND ${CMAKE_COMMAND} -E copy - "${CMAKE_SOURCE_DIR}/config/default.json" + ${default_config} "${config}" VERBATIM ) endif() - add_custom_target(build_${arch}_${test_source} ALL DEPENDS ${elf} ${config}) + add_custom_target(build_${arch}_${xlen}_${test_source} ALL DEPENDS ${elf} ${config}) add_test( - NAME "first_party_${arch}_${test_source}" + NAME "first_party_${arch}_${xlen}_${test_source}" COMMAND $ --config ${config} ${elf} ) endforeach() diff --git a/test/riscv-tests/CMakeLists.txt b/test/riscv-tests/CMakeLists.txt index 031f32531..e9ab365a1 100644 --- a/test/riscv-tests/CMakeLists.txt +++ b/test/riscv-tests/CMakeLists.txt @@ -13,8 +13,8 @@ foreach (arch IN ITEMS "rv32d" "rv64d") add_test( NAME "${arch}_${elf_name}" COMMAND - $ - --config "${CMAKE_SOURCE_DIR}/config/default.json" + $ + --config "${CMAKE_SOURCE_DIR}/config/${arch}.json" ${elf} ) endforeach()