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Commit 2bc5611

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[RVP] Add missing intrinsics
1. add missing intrinsics 2. fix wrong subext for several instructions 3. fix testsuit errors
1 parent 06c8e46 commit 2bc5611

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11 files changed

+1385
-1011
lines changed

11 files changed

+1385
-1011
lines changed

gcc/config/riscv/riscv-builtins-rvp.def

Lines changed: 149 additions & 123 deletions
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gcc/config/riscv/riscv-builtins.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -101,10 +101,11 @@ struct riscv_builtin_description {
101101
AVAIL (hard_float, TARGET_HARD_FLOAT)
102102
AVAIL (zprv, TARGET_ZPRV)
103103
AVAIL (zpsf, TARGET_ZPSF)
104+
AVAIL (zpsf32, TARGET_ZPSF && !TARGET_64BIT)
105+
AVAIL (zpsf64, TARGET_ZPSF && TARGET_64BIT)
104106
AVAIL (zpn, TARGET_ZPN)
105107
AVAIL (zpn64, TARGET_ZPN && TARGET_64BIT)
106108
AVAIL (zpn32, TARGET_ZPN && !TARGET_64BIT)
107-
AVAIL (rvp, TARGET_ZPSF || TARGET_ZPN || TARGET_ZPRV)
108109

109110
AVAIL (crypto_zknd32, TARGET_ZKND && !TARGET_64BIT)
110111
AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT)
@@ -411,7 +412,7 @@ riscv_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
411412
gcc_assert (opno + call_expr_nargs (exp)
412413
== insn_data[icode].n_generator_args);
413414
for (int argno = 0; argno < call_expr_nargs (exp); argno++){
414-
if (TARGET_ZPRV || TARGET_ZPSF || TARGET_ZPN)
415+
if (TARGET_ZPN)
415416
riscv_rvp_prepare_builtin_arg (&ops[opno++], exp, argno, icode, has_target_p);
416417
else
417418
riscv_prepare_builtin_arg (&ops[opno++], exp, argno);

gcc/config/riscv/riscv-c.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
4444

4545
if (TARGET_ZPN)
4646
builtin_define ("__riscv_zpn");
47+
4748
if (TARGET_ZPRV)
4849
builtin_define ("__riscv_zprv");
50+
4951
if (TARGET_ZPSF)
5052
builtin_define ("__riscv_zpsf");
5153

gcc/config/riscv/riscv-ftypes.def

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,9 @@ DEF_RISCV_FTYPE (1, (DI, DI))
3535
DEF_RISCV_FTYPE (2, (SI, SI, SI))
3636
DEF_RISCV_FTYPE (2, (DI, DI, DI))
3737
DEF_RISCV_FTYPE (2, (DI, DI, SI))
38+
DEF_RISCV_FTYPE (2, (DI, SI, SI))
39+
DEF_RISCV_FTYPE (2, (DI, USI, USI))
40+
DEF_RISCV_FTYPE (2, (UDI, USI, USI))
3841

3942
/* p extension function types */
4043
DEF_RISCV_FTYPE (1, (UIXLEN, USI))

gcc/config/riscv/riscv.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5273,20 +5273,20 @@ riscv_vector_mode_supported_p (enum machine_mode mode)
52735273
{
52745274
if (mode == V4QImode
52755275
|| mode == V2HImode)
5276-
return (TARGET_ZPRV || TARGET_ZPSF || TARGET_ZPN) && !TARGET_64BIT;
5276+
return TARGET_ZPN && !TARGET_64BIT;
52775277

52785278
if (mode == V8QImode
52795279
|| mode == V4HImode
52805280
|| mode == V2SImode)
5281-
return (TARGET_ZPRV || TARGET_ZPSF || TARGET_ZPN) && TARGET_64BIT;
5281+
return TARGET_ZPN && TARGET_64BIT;
52825282

52835283
return false;
52845284
}
52855285

52865286
static enum machine_mode
52875287
riscv_vectorize_preferred_simd_mode (scalar_mode mode)
52885288
{
5289-
if (!(TARGET_ZPRV || TARGET_ZPSF || TARGET_ZPN))
5289+
if (!TARGET_ZPN)
52905290
return word_mode;
52915291

52925292
switch (mode)

gcc/config/riscv/riscv.md

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -166,8 +166,7 @@
166166
"unknown,branch,jump,call,load,fpload,store,fpstore,
167167
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
168168
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,
169-
dalu,dalu64,daluround,dcmp,dclip,dmul,dmac,dinsb,dpack,dbpick,dwext,
170-
simd"
169+
dalu,dalu64,daluround,dcmp,dclip,dmul,dmac,dinsb,dpack,dbpick,dwext"
171170
(cond [(eq_attr "got" "load") (const_string "load")
172171

173172
;; If a doubleword move uses these expensive instructions,

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