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RISC-V: Correct and improve the "-mabi" documentation
The documentation for the "-mabi" argument on RISC-V was incorrect. We chose to treat this as a documentation bug rather than a code bug, and to make the documentation match what GCC currently does. In the process, I also improved the documentation a bit. Thanks to Alex Bradbury for finding the bug! PR target/82717: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82717 gcc/ChangeLog 2017-10-26 Palmer Dabbelt <[email protected]> PR target/82717 * doc/invoke.texi (RISC-V) <-mabi>: Correct and improve.
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gcc/doc/invoke.texi

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@@ -21669,9 +21669,26 @@ When generating PIC code, allow the use of PLTs. Ignored for non-PIC.
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@item -mabi=@var{ABI-string}
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@opindex mabi
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Specify integer and floating-point calling convention. This defaults to the
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natural calling convention: e.g.@ LP64 for RV64I, ILP32 for RV32I, LP64D for
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RV64G.
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@item -mabi=@var{ABI-string}
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@opindex mabi
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Specify integer and floating-point calling convention. @var{ABI-string}
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contains two parts: the size of integer types and the registers used for
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floating-point types. For example @samp{-march=rv64ifd -mabi=lp64d} means that
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@samp{long} and pointers are 64-bit (implicitly defining @samp{int} to be
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32-bit), and that floating-point values up to 64 bits wide are passed in F
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registers. Contrast this with @samp{-march=rv64ifd -mabi=lp64f}, which still
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allows the compiler to generate code that uses the F and D extensions but only
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allows floating-point values up to 32 bits long to be passed in registers; or
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@samp{-march=rv64ifd -mabi=lp64}, in which no floating-point arguments will be
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passed in registers.
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The default for this argument is system dependent, users who want a specific
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calling convention should specify one explicitly. The valid calling
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conventions are: @samp{ilp32}, @samp{ilp32f}, @samp{ilp32d}, @samp{lp64},
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@samp{lp64f}, and @samp{lp64d}. Some calling conventions are impossible to
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implement on some ISAs: for example, @samp{-march=rv32if -mabi=ilp32d} is
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invalid because the ABI requires 64-bit values be passed in F registers, but F
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registers are only 32 bits wide.
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@item -mfdiv
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@itemx -mno-fdiv

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