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Commit cd35a41

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linsinan1995linsinan1995
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rvp: use gcc standard name for rv32p mac operation
1 parent f4b6264 commit cd35a41

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2 files changed

+63
-92
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2 files changed

+63
-92
lines changed

‎gcc/config/riscv/riscv-builtins-rvp.def

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -863,28 +863,28 @@ DIRECT_BUILTIN_NO_PREFIX (rsubdi3, rsub64, RISCV_DI_FTYPE_DI_DI, zpsf),
863863
DIRECT_BUILTIN_NO_PREFIX (ursubdi3, ursub64, RISCV_UDI_FTYPE_UDI_UDI, zpsf),
864864
DIRECT_BUILTIN_NO_PREFIX (rvp_ksubdi3, ksub64, RISCV_DI_FTYPE_DI_DI, zpsf),
865865
DIRECT_BUILTIN_NO_PREFIX (rvp_uksubdi3, uksub64, RISCV_UDI_FTYPE_UDI_UDI, zpsf),
866-
DIRECT_BUILTIN_NO_PREFIX (smar64_1, smar64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf32),
866+
DIRECT_BUILTIN_NO_PREFIX (maddsidi4, smar64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf32),
867867
DIRECT_BUILTIN_NO_PREFIX (vsmar64_1, smar64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf64),
868868
DIRECT_BUILTIN_NO_PREFIX (vsmar64_1, v_smar64, RISCV_DI_FTYPE_DI_V2SI_V2SI, zpsf64),
869-
DIRECT_BUILTIN_NO_PREFIX (smsr64, smsr64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf32),
869+
DIRECT_BUILTIN_NO_PREFIX (msubsidi4, smsr64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf32),
870870
DIRECT_BUILTIN_NO_PREFIX (vsmsr64, smsr64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf64),
871871
DIRECT_BUILTIN_NO_PREFIX (vsmsr64, v_smsr64, RISCV_DI_FTYPE_DI_V2SI_V2SI, zpsf64),
872-
DIRECT_BUILTIN_NO_PREFIX (umar64_1, umar64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf32),
872+
DIRECT_BUILTIN_NO_PREFIX (umaddsidi4, umar64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf32),
873873
DIRECT_BUILTIN_NO_PREFIX (vumar64_1, umar64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf64),
874874
DIRECT_BUILTIN_NO_PREFIX (vumar64_1, v_umar64, RISCV_UDI_FTYPE_UDI_UV2SI_UV2SI, zpsf64),
875-
DIRECT_BUILTIN_NO_PREFIX (umsr64, umsr64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf32),
875+
DIRECT_BUILTIN_NO_PREFIX (umsubsidi4, umsr64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf32),
876876
DIRECT_BUILTIN_NO_PREFIX (vumsr64, umsr64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf64),
877877
DIRECT_BUILTIN_NO_PREFIX (vumsr64, v_umsr64, RISCV_UDI_FTYPE_UDI_UV2SI_UV2SI, zpsf64),
878-
DIRECT_BUILTIN_NO_PREFIX (kmar64, kmar64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf32),
878+
DIRECT_BUILTIN_NO_PREFIX (ssmaddsidi4, kmar64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf32),
879879
DIRECT_BUILTIN_NO_PREFIX (vkmar64, kmar64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf64),
880880
DIRECT_BUILTIN_NO_PREFIX (vkmar64, v_kmar64, RISCV_DI_FTYPE_DI_V2SI_V2SI, zpsf64),
881-
DIRECT_BUILTIN_NO_PREFIX (ukmar64_1, ukmar64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf32),
881+
DIRECT_BUILTIN_NO_PREFIX (usmaddsidi4, ukmar64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf32),
882882
DIRECT_BUILTIN_NO_PREFIX (vukmar64, ukmar64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf64),
883883
DIRECT_BUILTIN_NO_PREFIX (vukmar64, v_ukmar64, RISCV_UDI_FTYPE_UDI_UV2SI_UV2SI, zpsf64),
884-
DIRECT_BUILTIN_NO_PREFIX (kmsr64, kmsr64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf32),
884+
DIRECT_BUILTIN_NO_PREFIX (ssmsubsidi4, kmsr64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf32),
885885
DIRECT_BUILTIN_NO_PREFIX (vkmsr64, kmsr64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf64),
886886
DIRECT_BUILTIN_NO_PREFIX (vkmsr64, v_kmsr64, RISCV_DI_FTYPE_DI_V2SI_V2SI, zpsf64),
887-
DIRECT_BUILTIN_NO_PREFIX (ukmsr64, ukmsr64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf32),
887+
DIRECT_BUILTIN_NO_PREFIX (usmsubsidi4, ukmsr64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf32),
888888
DIRECT_BUILTIN_NO_PREFIX (vukmsr64, ukmsr64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf64),
889889
DIRECT_BUILTIN_NO_PREFIX (vukmsr64, v_ukmsr64, RISCV_UDI_FTYPE_UDI_UV2SI_UV2SI, zpsf64),
890890
DIRECT_BUILTIN_NO_PREFIX (smalbb, smalbb, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf32),

‎gcc/config/riscv/rvp.md

Lines changed: 55 additions & 84 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,8 @@
4848
(define_code_iterator all_minus [minus ss_minus us_minus])
4949
(define_code_iterator saturation_plus [ss_plus us_plus])
5050
(define_code_iterator saturation_minus [ss_minus us_minus])
51+
(define_code_iterator ssat_op [ss_plus ss_minus])
52+
(define_code_iterator usat_op [us_plus us_minus])
5153
(define_code_iterator plus_minus [plus minus])
5254

5355
;; smax[8|16] and umax[8|16]
@@ -58,12 +60,22 @@
5860
(define_code_attr shift [(ashift "ashl") (ashiftrt "ashr") (lshiftrt "lshr")])
5961

6062
;; smalxd[s|a] smald[s|a]
61-
(define_code_attr add_sub [(plus "a") (minus "s")])
63+
(define_code_attr add_sub [(plus "a")
64+
(ss_plus "a")
65+
(us_plus "a")
66+
(ss_minus "s")
67+
(us_minus "s")
68+
(minus "s")])
69+
6270
;; (un)signed unpacking patterns
6371
(define_code_attr zs [(sign_extend "s") (zero_extend "z")])
6472

6573
(define_code_attr opcode [(plus "add")
6674
(minus "sub")
75+
(ss_plus "add")
76+
(us_plus "add")
77+
(ss_minus "sub")
78+
(us_minus "sub")
6779
(smax "smax")
6880
(umax "umax")
6981
(smin "smin")
@@ -1774,21 +1786,7 @@
17741786
"kmaxds\t%0, %2, %3"
17751787
[(set_attr "type" "simd")])
17761788

1777-
;; KMAR64
1778-
(define_insn "kmar64"
1779-
[(set (match_operand:DI 0 "register_operand" "=r")
1780-
(ss_plus:DI
1781-
(match_operand:DI 1 "register_operand" " 0")
1782-
(mult:DI
1783-
(sign_extend:DI
1784-
(match_operand:SI 2 "register_operand" " r"))
1785-
(sign_extend:DI
1786-
(match_operand:SI 3 "register_operand" " r")))))]
1787-
"TARGET_ZPSF && !TARGET_64BIT"
1788-
"kmar64\t%0, %2, %3"
1789-
[(set_attr "type" "dsp64")
1790-
(set_attr "mode" "DI")])
1791-
1789+
;; RV64P KMAR64
17921790
(define_insn "vkmar64"
17931791
[(set (match_operand:DI 0 "register_operand" "=r")
17941792
(ss_plus:DI (match_operand:DI 1 "register_operand" " 0")
@@ -2544,21 +2542,7 @@
25442542
"kmsxda\t%0, %2, %3"
25452543
[(set_attr "type" "simd")])
25462544

2547-
;; KMSR64
2548-
(define_insn "kmsr64"
2549-
[(set (match_operand:DI 0 "register_operand" "=r")
2550-
(ss_minus:DI
2551-
(match_operand:DI 1 "register_operand" " 0")
2552-
(mult:DI
2553-
(sign_extend:DI
2554-
(match_operand:SI 2 "register_operand" " r"))
2555-
(sign_extend:DI
2556-
(match_operand:SI 3 "register_operand" " r")))))]
2557-
"TARGET_ZPN && !TARGET_64BIT"
2558-
"kmsr64\t%0, %2, %3"
2559-
[(set_attr "type" "dsp64")
2560-
(set_attr "mode" "DI")])
2561-
2545+
;; RV64P KMSR64
25622546
(define_insn "vkmsr64"
25632547
[(set (match_operand:DI 0 "register_operand" "=r")
25642548
(ss_minus:DI
@@ -4121,21 +4105,52 @@
41214105
"smaldrs\t%0, %2, %3"
41224106
[(set_attr "type" "dsp64")])
41234107

4124-
;; SMAR64, UMAR64
4125-
(define_insn "<su>mar64_1"
4108+
;; RV32P KMAR64, KMSR64
4109+
(define_insn "ssm<opcode>sidi4"
41264110
[(set (match_operand:DI 0 "register_operand" "=r")
4127-
(plus:DI
4128-
(match_operand:DI 1 "register_operand" " 0")
4111+
(ssat_op:DI
4112+
(mult:DI
4113+
(sign_extend:DI
4114+
(match_operand:SI 1 "register_operand" " r"))
4115+
(sign_extend:DI
4116+
(match_operand:SI 2 "register_operand" " r")))
4117+
(match_operand:DI 3 "register_operand" " 0")))]
4118+
"TARGET_ZPSF && !TARGET_64BIT"
4119+
"km<add_sub>r64\t%0, %1, %2"
4120+
[(set_attr "type" "dsp64")
4121+
(set_attr "mode" "DI")])
4122+
4123+
;; RV32P UKMSR64, UKMAR64
4124+
(define_insn "usm<opcode>sidi4"
4125+
[(set (match_operand:DI 0 "register_operand" "=r")
4126+
(usat_op:DI
4127+
(mult:DI
4128+
(zero_extend:DI
4129+
(match_operand:SI 1 "register_operand" " r"))
4130+
(zero_extend:DI
4131+
(match_operand:SI 2 "register_operand" " r")))
4132+
(match_operand:DI 3 "register_operand" " 0")))]
4133+
"TARGET_ZPSF && !TARGET_64BIT"
4134+
"ukm<add_sub>r64\t%0, %1, %2"
4135+
[(set_attr "type" "dsp64")
4136+
(set_attr "mode" "DI")])
4137+
4138+
;; RV32P KMSR64, KMAR64
4139+
(define_insn "<u>m<opcode>sidi4"
4140+
[(set (match_operand:DI 0 "register_operand" "=r")
4141+
(plus_minus:DI
41294142
(mult:DI
41304143
(any_extend:DI
4131-
(match_operand:SI 2 "register_operand" " r"))
4144+
(match_operand:SI 1 "register_operand" " r"))
41324145
(any_extend:DI
4133-
(match_operand:SI 3 "register_operand" " r")))))]
4146+
(match_operand:SI 2 "register_operand" " r")))
4147+
(match_operand:DI 3 "register_operand" " 0")))]
41344148
"TARGET_ZPSF && !TARGET_64BIT"
4135-
"<su>mar64\t%0, %2, %3"
4149+
"<su>m<add_sub>r64\t%0, %1, %2"
41364150
[(set_attr "type" "dsp64")
41374151
(set_attr "mode" "DI")])
41384152

4153+
;; SMAR64, UMAR64
41394154
(define_insn "v<su>mar64_1"
41404155
[(set (match_operand:DI 0 "register_operand" "=r")
41414156
(plus:DI (match_operand:DI 1 "register_operand" " 0")
@@ -5161,20 +5176,6 @@
51615176
[(set_attr "type" "dsp64")])
51625177

51635178
;; SMSR64, UMSR64
5164-
(define_insn "<su>msr64"
5165-
[(set (match_operand:DI 0 "register_operand" "=r")
5166-
(minus:DI
5167-
(match_operand:DI 1 "register_operand" " 0")
5168-
(mult:DI
5169-
(any_extend:DI
5170-
(match_operand:SI 2 "register_operand" " r"))
5171-
(any_extend:DI
5172-
(match_operand:SI 3 "register_operand" " r")))))]
5173-
"TARGET_ZPSF && !TARGET_64BIT"
5174-
"<su>msr64\t%0, %2, %3"
5175-
[(set_attr "type" "dsp64")
5176-
(set_attr "mode" "DI")])
5177-
51785179
(define_insn "v<su>msr64"
51795180
[(set (match_operand:DI 0 "register_operand" "=r")
51805181
(minus:DI
@@ -6011,22 +6012,7 @@
60116012
[(set_attr "type" "simd")
60126013
(set_attr "mode" "SI")])
60136014

6014-
;; ukmar64
6015-
(define_insn "ukmar64_1"
6016-
[(set (match_operand:DI 0 "register_operand" "=r")
6017-
(us_plus:DI
6018-
(match_operand:DI 1 "register_operand" " 0")
6019-
(mult:DI
6020-
(zero_extend:DI
6021-
(match_operand:SI 2 "register_operand" " r"))
6022-
(zero_extend:DI
6023-
(match_operand:SI 3 "register_operand" " r")))))]
6024-
"TARGET_ZPSF && !TARGET_64BIT"
6025-
"ukmar64\t%0, %2, %3"
6026-
[(set_attr "type" "dsp64")
6027-
(set_attr "mode" "DI")])
6028-
6029-
;; RV64P
6015+
;; RV64P ukmar64
60306016
(define_insn "vukmar64"
60316017
[(set (match_operand:DI 0 "register_operand" "=r")
60326018
(us_plus:DI (match_operand:DI 1 "register_operand" " 0")
@@ -6050,22 +6036,7 @@
60506036
[(set_attr "type" "dsp64")
60516037
(set_attr "mode" "DI")])
60526038

6053-
;; ukmsr64
6054-
(define_insn "ukmsr64"
6055-
[(set (match_operand:DI 0 "register_operand" "=r")
6056-
(us_minus:DI
6057-
(match_operand:DI 1 "register_operand" " 0")
6058-
(mult:DI
6059-
(zero_extend:DI
6060-
(match_operand:SI 2 "register_operand" " r"))
6061-
(zero_extend:DI
6062-
(match_operand:SI 3 "register_operand" " r")))))]
6063-
"TARGET_ZPSF && !TARGET_64BIT"
6064-
"ukmsr64\t%0, %2, %3"
6065-
[(set_attr "type" "dsp64")
6066-
(set_attr "mode" "DI")])
6067-
6068-
;; RV64P
6039+
;; RV64P ukmsr64
60696040
(define_insn "vukmsr64"
60706041
[(set (match_operand:DI 0 "register_operand" "=r")
60716042
(us_minus:DI

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