updated Quartus project file.

Author: rkrajnc

fpga/de10_nano/mandelbrot_fpga_de10_nano.qsf

@@ -247,7 +247,9 @@ set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS
 set_instance_assignment -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS -to "mandelbrot_fpga_top:mandelbrot_fpga_top|async_fifo:mandelbrot_fifo|in_rcnt1[*]"
 set_global_assignment -name QII_AUTO_PACKED_REGISTERS "SPARSE AUTO"
 set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
-set_global_assignment -name VERILOG_FILE ../../rtl/qmem/qmem_decoder.v
+set_global_assignment -name VERILOG_FILE ../../rtl/stream/stream_reg.v
+set_global_assignment -name VERILOG_FILE ../../rtl/stream/stream_distributor.v
+set_global_assignment -name VERILOG_FILE ../../rtl/stream/stream_collector.v
 set_global_assignment -name VERILOG_FILE ../../rtl/or1200/timescale.v
 set_global_assignment -name VERILOG_FILE ../../rtl/or1200/or1200_xcv_ram32x8d.v
 set_global_assignment -name VERILOG_FILE ../../rtl/or1200/or1200_wbmux.v
@@ -310,12 +312,14 @@ set_global_assignment -name VERILOG_FILE ../../rtl/or1200/or1200_amultp2_32x32.v
 set_global_assignment -name VERILOG_FILE ../../rtl/or1200/or1200_alu.v
 set_global_assignment -name VERILOG_FILE ../../rtl/memory/ram_generic_dp_bs.v
 set_global_assignment -name VERILOG_FILE ../../rtl/ctrl/ctrl_regs.v
+set_global_assignment -name VERILOG_FILE ../../rtl/qmem/qmem_decoder.v
 set_global_assignment -name VERILOG_FILE ../../rtl/ctrl/ctrl_bus.v
 set_global_assignment -name VERILOG_FILE ../../rtl/ctrl/ctrl_top.v
 set_global_assignment -name VERILOG_FILE ../../rtl/fifo/async_fifo.v
 set_global_assignment -name VERILOG_FILE ../../rtl/fifo/sync_fifo.v
 set_global_assignment -name VERILOG_FILE ../../rtl/mandelbrot/mandelbrot_coords.v
 set_global_assignment -name VERILOG_FILE ../../rtl/mandelbrot/mandelbrot_calc.v
+set_global_assignment -name VERILOG_FILE ../../rtl/mandelbrot/mandelbrot_calc_wrap.v
 set_global_assignment -name VERILOG_FILE ../../rtl/mandelbrot/mandelbrot_top.v
 set_global_assignment -name VERILOG_FILE ../../rtl/memory/rom_generic_sp.v
 set_global_assignment -name VERILOG_FILE ../../rtl/memory/ram_generic_tp.v
@@ -338,4 +342,16 @@ set_global_assignment -name CDF_FILE mandelbrot_fpga_de10_nano.cdf
 set_global_assignment -name SDC_FILE mandelbrot_fpga_de10_nano.SDC
 set_global_assignment -name SIGNALTAP_FILE stp1.stp
 set_global_assignment -name QIP_FILE ../../rtl/cyclonev_memory/cyclonev_ram_2kx32_dp_bs.qip
+set_global_assignment -name ENABLE_OCT_DONE OFF
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top