DMA Timing Issue

[A-Small-Mice]

When building my ATX Turbo XT, I faced significant challenges in adjusting the DMA timing. The motherboard built according to the BoM you provided works well at 4.77 MHz, but at 8 MHz, issues arise, such as the floppy disk not reading correctly or digitized sound not playing properly. I received help from CHARLIE IM, known for assembling a Soviet Poisk-2 with American parts, and managed to resolve the DMA timing issue by making adjustments according to the following table. I hope this information will be helpful to others as well.

Part#	Orginal	New
U1	uPD70108C-8	uPD70108C-8
U2	HCT573	CD74HCT573E
U3	LS245	SN74HCT245N
U4	HCT573	CD74HCT573E
U5	HCT245	SN74HCT245N
U6	LS245	SN74F245N
U7	LS245	SN74F245N
U8	LS245	SN74F245N
U9	HCT245	SN74LS245N
U10	HCT245	SN74LS245N
U11	N/A
U12	TMS27C010A	TMS27C010A
U13	K6T4008C1B	AS6C4008-55PCN
U14	K6T4008C1B	AS6C4008-55PCN
U15	I8087	C8087
U16	CP82C88	CP82C88
U17	LS245	SN74ALS245AN
U18	N/A
U19	M82C84A-2	M82C84A-2
U20	HCT04	SN74HCT04N
U21	LS92	SN74LS92N
U22	uPD8237AC-5	uPD8237AC-5
U23	LS670	SN74LS670N
U24	HCT573	SN74ALS573CN
U25	LS138	HD74LS138P
U26	uPD8253C-2	uPD8253C-2
U27	uPD71055C	uPD71055C
U28	LS322	SN74LS322AN
U29	LS244	SN74LS244N
U30	uPD8259AC-2	uPD8259AC-2
U31	uPD8259AC-2	uPD8259AC-2
U32	GM82C765B	GM82C765B
U33	LS138	DM74LS138N
U34	LS125	SN74LS125AN
U35	N/A
U36	LS32	SN74LS32N
U37	LS04	SN74LS04N
U38	NE555P	NE555P
U39	HCT74	SN74HCT74N
U40	CD4020BE	CD4020BE
U41	CD4020BE	CD4020BE
U42	N/A
U43	HCT245	SN74LS245N
U44	HCT139	GD74LS139
U45	LS174	SN74LS174N
U46	HCT574	MM74HCT574N
U47	HCT245	SN74LS245N
U48	HCT32	SN74F32N
U49	LS06	SN74LS06N
U50	N/A
U51	N/A
U52	N/A
U53	N/A
U54	HCT04	SN74HCT04N
U55	HC08	SN74F08N
U56	HCT74	SN74HCT74N
U57	N/A
U58	HCT74	74ALS74AN
U59	HCT00	SN74F00N
U60	HCT74	SN74F74N
U61	HC08	SN74LS08N
U62	HCT74	SN74LS74AN
U63	N/A
U64	LS74	SN74LS74AN
U65	LS74	SN74LS74AN
U66	LS06	SN74LS06N
U67	N/A
U68	LS125	SN74LS125AN
U69	LS125	SN74LS125AN
U70	LS125	SN74LS125AN
U71	HCT04	SN74HCT04N
U72	N/A
U73	LS245	SN74HCT245N
U74	HCT573	CD74HCT573E
U75	HCT573	CD74HCT573E
U76	HCT245	SN74HCT245N
U77	N/A
U78	LS138	DM74LS138N
U79	LS04	SN74LS04N
U80	HCT04	SN74HCT04N
U81	LS32	HD74LS32P
U82	N/A
U83	LS138	SN74HCT138N
U84	LS138	SN74HCT138N
U85	HCT139	CD74HCT139E
U86	HCT32	MM74HCT32N
U87	LS138	DM74LS138N
U88	HC08	SN74LS08N
U89	HC08	SN74LS08N
U90	HCT32	HD74LS32P
U91	GM16C550	TI16C550AN
U92	N/A
U93	GD75232	GD75232
U94	N/A
U95	HCT04	74HCT04N
U96	HCT74	SN74HCT74N
U97	RTL8019AS	RTL8019AS
U98	HT93LC46	93LC46B-I/P
U99	53C400	53C400
U100	HCT245	SN74LS245N

[rodneyknaap]

Hi A-Small-Mice,
I have read your component list which lead you to a successful assembly, congratulations on your work.

It has been a while since I worked on this last. When I worked on my prototype, which is clocked at 8MHz, I also spent time debugging the system. The way I went about it is very similar to what you have done, by swapping logic types in certain key locations, the timing of the system is shifted. Some locations are much more critical than others, for example the 74HC74 D-latches and 74HC08 AND gates in the DMA arbitration circuits are particularly sensitive. Also changing the 74LS138 decoder logic types will shift the chip selects which may help shifting the timing in the right spot. After you have solved the timing issues now, you may in fact find that you can swap back other IC locations to the original values and the system will continue to work fine. It's quite possible that only one or two IC locations are the most critical changes which made the most difference. The DMA arbitration circuits are an influence, and also the chip select decoding logic is another side. If these are too fast it also may shorten the window of the other DMA logic where this still is able to work.

Indeed it is helpful to have some 74Fxx logic ICs on hand for the areas which need to be the fastest. The photo you posted looks to me like the IOCHRDY processing may have been the issue judging from the character errors. I didn't have this problem myself on the XT, but on my AT design this was the initial issue causing VGA screen memory updates to get missed in many locations. I shifted the ready enable timing to resolve it in the AT. Similar things could be going on in the XT.

The problem is, when you use these TTL ICs, some may have significant different timing from the ones I used. Even if the type indication is identical, the timing will be different because the different manufacturers used different chip fabrication methods. These also continued to develop over the years and a newer part may have different timing, even from the same brand. Also the DMA controller timing will vary in my experience, which will in turn influence the DMA arbitration timing because the controller has a different response time.

On the other hand, having so many logic areas does at least provide more ways to shift the timing where you want with different logic families. So anyone constructing this design will do well to keep a stock of different logic types especially for the 74HC08, 74HC74, and the data transceivers. The address latches are much less sensitive parts in my experience.

Another example is the XT-IDE design which may be somewhat relevant for this project. There, swapping logic types for the decoders and delay circuits makes all the difference between a working and not working IDE interface.

Great job, and thank you for sharing the list and information, no doubt this may help others.

After overcoming your initial struggles, your system will now surely feel even more precious to you. :)
And you learned a lot about system timing on the way there!

I have similar sentiments after a long period of development. I had a lot of struggles with bad IC sockets from Chinese sellers. One was so loose that some of the keystrokes didn't even arrive on the bus. One should not buy cheap IC sockets! ;)

Kind regards,

Rodney