Added Verilog Programming Language

Author: Undalevein

verilog/clockhands.sv

@@ -0,0 +1,22 @@
+module ClockHands;
+  integer i, t, h, m, s;
+  function reg [1:2*8] pad;
+    input integer n;
+    reg [1:2*8] format;
+    begin
+      format[1:8] = n / 10 + 48;
+      format[9:16] = n % 10 + 48;
+      pad = format;
+    end
+  endfunction
+  
+  initial begin
+    for (i = 0 ; i < 11 ; i++) begin
+      t = (43200 * i + 21600) / 11;
+      h = t / 3600;
+      m = t / 60 % 60;
+      s = t % 60;
+      $display("%s:%s:%s", pad(h ? h : 12), pad(m), pad(s));
+    end
+  end
+endmodule

verilog/hello.sv

@@ -0,0 +1,4 @@
+module HelloWorld;
+  initial
+    $display("Hello, world!");
+endmodule

verilog/test.ps1

@@ -0,0 +1,33 @@
+function Assert-MatchTests {
+    param (
+        [Parameter(Mandatory = $true, ValueFromPipeline)] $TestResult
+    )
+
+    if ($TestResult) {
+        Write-Error "Output does not match expected results."
+    }
+}
+
+$bin = "$PSScriptRoot\bin"
+
+# First check if folder bin exists. If not, make a new bin folder.
+if (!(Test-Path -Path $bin)) {
+    New-Item -Path $bin -Type Directory
+} 
+
+$Error.clear()
+iverilog -o "$bin\clockhands" "$PSScriptRoot\clockhands.sv" && vvp "$bin\clockhands" | 
+    Compare-Object (Get-Content "$PSScriptRoot\..\test\clockhands_expected") |
+    Assert-MatchTests &&
+iverilog -o "$bin\hello" "$PSScriptRoot\hello.sv" && vvp "$bin\hello" &&
+iverilog -o "$bin\triple" "$PSScriptRoot\triple.sv" && vvp "$bin\triple" | 
+    Compare-Object (Get-Content "$PSScriptRoot\..\test\triple_expected") | 
+    Assert-MatchTests &&
+ForEach-Object 'foo'
+
+if ($Error -or !$?) {
+    "*** VERILOG TESTS FAILED ***"
+}
+else {
+    "VERILOG TESTS PASSED"
+}

verilog/triple.sv

@@ -0,0 +1,9 @@
+module Triple;
+  integer a, b, c;
+  initial
+    for (c = 1 ; c < 41 ; c++)
+      for (b = 1 ; b < c ; b++)
+        for (a = 1 ; a < b ; a++)
+          if (a * a + b * b == c * c)
+            $display("%0d, %0d, %0d", a, b, c);
+endmodule