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rui314rui314
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Rename a function
1 parent 721eafc commit 3b1e2a9

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9 files changed

+37
-37
lines changed

9 files changed

+37
-37
lines changed

‎lib/common.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -372,9 +372,9 @@ inline u64 bits(u64 val, u64 hi, u64 lo) {
372372
return (val >> lo) & ((1LL << (hi - lo + 1)) - 1);
373373
}
374374

375-
// Cast val to a signed N bit integer. I.e., int_cast(x, 32) == (i32)x
376-
// for any integer x.
377-
inline i64 int_cast(u64 val, i64 n) {
375+
// Cast val to a signed N bit integer.
376+
// For example, sign_extend(x, 32) == (i32)x for any integer x.
377+
inline i64 sign_extend(u64 val, i64 n) {
378378
return (i64)(val << (64 - n)) >> (64 - n);
379379
}
380380

‎src/arch-arm32.cc‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ i64 get_addend(u8 *loc, const ElfRel<E> &rel) {
5757
case R_ARM_TARGET2:
5858
return *(il32 *)loc;
5959
case R_ARM_THM_JUMP11:
60-
return int_cast(*(ul16 *)loc, 11) << 1;
60+
return sign_extend(*(ul16 *)loc, 11) << 1;
6161
case R_ARM_THM_CALL:
6262
case R_ARM_THM_JUMP24:
6363
case R_ARM_THM_TLS_CALL: {
@@ -69,23 +69,23 @@ i64 get_addend(u8 *loc, const ElfRel<E> &rel) {
6969
u32 imm10 = bits(*(ul16 *)loc, 9, 0);
7070
u32 imm11 = bits(*(ul16 *)(loc + 2), 10, 0);
7171
u32 val = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
72-
return int_cast(val, 25);
72+
return sign_extend(val, 25);
7373
}
7474
case R_ARM_CALL:
7575
case R_ARM_JUMP24:
7676
case R_ARM_PLT32:
7777
case R_ARM_TLS_CALL:
78-
return int_cast(*(ul32 *)loc, 24) << 2;
78+
return sign_extend(*(ul32 *)loc, 24) << 2;
7979
case R_ARM_MOVW_PREL_NC:
8080
case R_ARM_MOVW_ABS_NC:
8181
case R_ARM_MOVT_PREL:
8282
case R_ARM_MOVT_ABS: {
8383
u32 imm12 = bits(*(ul32 *)loc, 11, 0);
8484
u32 imm4 = bits(*(ul32 *)loc, 19, 16);
85-
return int_cast((imm4 << 12) | imm12, 16);
85+
return sign_extend((imm4 << 12) | imm12, 16);
8686
}
8787
case R_ARM_PREL31:
88-
return int_cast(*(ul32 *)loc, 31);
88+
return sign_extend(*(ul32 *)loc, 31);
8989
case R_ARM_THM_MOVW_PREL_NC:
9090
case R_ARM_THM_MOVW_ABS_NC:
9191
case R_ARM_THM_MOVT_PREL:
@@ -95,7 +95,7 @@ i64 get_addend(u8 *loc, const ElfRel<E> &rel) {
9595
u32 imm3 = bits(*(ul16 *)(loc + 2), 14, 12);
9696
u32 imm8 = bits(*(ul16 *)(loc + 2), 7, 0);
9797
u32 val = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8;
98-
return int_cast(val, 16);
98+
return sign_extend(val, 16);
9999
}
100100
default:
101101
return 0;
@@ -782,7 +782,7 @@ std::vector<u8> Arm32ExidxSection::get_contents(Context<E> &ctx) {
782782

783783
tbb::parallel_for((i64)0, num_entries, [&](i64 i) {
784784
i64 offset = sizeof(Entry) * i;
785-
ent[i].addr = int_cast(ent[i].addr, 31) + offset;
785+
ent[i].addr = sign_extend(ent[i].addr, 31) + offset;
786786
if (is_relative(ent[i].val))
787787
ent[i].val = 0x7fff'ffff & (ent[i].val + offset);
788788
});

‎src/arch-arm64.cc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -238,7 +238,7 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
238238
i + 1 < rels.size()) {
239239
i64 val = S + A - P - 4;
240240
const ElfRel<E> &rel2 = rels[i + 1];
241-
if (int_cast(val, 21) == val &&
241+
if (sign_extend(val, 21) == val &&
242242
rel2.r_type == R_AARCH64_ADD_ABS_LO12_NC &&
243243
rel2.r_sym == rel.r_sym &&
244244
rel2.r_offset == rel.r_offset + 4 &&

‎src/arch-loongarch.cc‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -369,7 +369,7 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
369369
// It is contrary to the psABI document, but GNU ld has special
370370
// code to handle it, so we accept it too.
371371
if ((*(ul32 *)loc & 0xfc00'0000) == 0x4c00'0000)
372-
write_k16(loc, int_cast(S + A, 12) >> 2);
372+
write_k16(loc, sign_extend(S + A, 12) >> 2);
373373
else
374374
write_k12(loc, S + A);
375375
break;
@@ -600,7 +600,7 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
600600
case R_LARCH_TLS_DESC_PC_LO12:
601601
if (sym.has_tlsdesc(ctx) && removed_bytes == 0) {
602602
i64 dist = sym.get_tlsdesc_addr(ctx) + A - P;
603-
if (int_cast(dist, 22) == dist) {
603+
if (sign_extend(dist, 22) == dist) {
604604
// If we can directly materialize the PC-relative address
605605
// with pcaddi, do that.
606606
*(ul32 *)loc = 0x1800'0000 | get_rd(*(ul32 *)loc); // pcaddi
@@ -649,7 +649,7 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
649649

650650
// Rewrite `addi.d $t0, $t0, <offset>` with `addi.d $t0, $tp, <offset>`
651651
// if the offset is directly accessible using tp. tp is r2.
652-
if (int_cast(val, 12) == val)
652+
if (sign_extend(val, 12) == val)
653653
set_rj(loc, 2);
654654
break;
655655
}
@@ -931,7 +931,7 @@ void shrink_section(Context<E> &ctx, InputSection<E> &isec) {
931931
//
932932
// addi.d $t0, $tp, <tp-offset>
933933
if (i64 val = sym.get_addr(ctx) + r.r_addend - ctx.tp_addr;
934-
int_cast(val, 12) == val)
934+
sign_extend(val, 12) == val)
935935
remove(4);
936936
break;
937937
case R_LARCH_PCALA_HI20:
@@ -954,7 +954,7 @@ void shrink_section(Context<E> &ctx, InputSection<E> &isec) {
954954
u32 insn2 = *(ul32 *)(buf + rels[i].r_offset + 4);
955955
bool is_addi_d = (insn2 & 0xffc0'0000) == 0x02c0'0000;
956956

957-
if ((dist & 0b11) == 0 && int_cast(dist, 22) == dist &&
957+
if ((dist & 0b11) == 0 && sign_extend(dist, 22) == dist &&
958958
is_addi_d && get_rd(insn1) == get_rd(insn2) &&
959959
get_rd(insn2) == get_rj(insn2))
960960
remove(4);
@@ -970,7 +970,7 @@ void shrink_section(Context<E> &ctx, InputSection<E> &isec) {
970970
// If the displacement is PC ± 128 MiB, we can use B or BL instead.
971971
// Note that $zero is $r0 and $ra is $r1.
972972
if (i64 dist = compute_distance(ctx, sym, isec, r);
973-
int_cast(dist, 28) == dist)
973+
sign_extend(dist, 28) == dist)
974974
if (u32 jirl = *(ul32 *)(buf + rels[i].r_offset + 4);
975975
get_rd(jirl) == 0 || get_rd(jirl) == 1)
976976
remove(4);
@@ -988,15 +988,15 @@ void shrink_section(Context<E> &ctx, InputSection<E> &isec) {
988988
// pcaddi $t0, <offset>
989989
if (is_relaxable_got_load(ctx, isec, i)) {
990990
i64 dist = compute_distance(ctx, sym, isec, r);
991-
if ((dist & 0b11) == 0 && int_cast(dist, 22) == dist)
991+
if ((dist & 0b11) == 0 && sign_extend(dist, 22) == dist)
992992
remove(4);
993993
}
994994
break;
995995
case R_LARCH_TLS_DESC_PC_HI20:
996996
if (sym.has_tlsdesc(ctx)) {
997997
u64 P = isec.get_addr() + r.r_offset;
998998
i64 dist = sym.get_tlsdesc_addr(ctx) + r.r_addend - P;
999-
if (int_cast(dist, 22) == dist)
999+
if (sign_extend(dist, 22) == dist)
10001000
remove(4);
10011001
} else {
10021002
remove(4);

‎src/arch-ppc32.cc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -213,14 +213,14 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
213213
case R_PPC_REL24:
214214
case R_PPC_LOCAL24PC: {
215215
i64 val = S + A - P;
216-
if (int_cast(val, 26) != val)
216+
if (sign_extend(val, 26) != val)
217217
val = sym.get_thunk_addr(ctx, P) - P;
218218
*(ub32 *)loc |= bits(val, 25, 2) << 2;
219219
break;
220220
}
221221
case R_PPC_PLTREL24: {
222222
i64 val = S - P;
223-
if (sym.has_plt(ctx) || int_cast(val, 26) != val)
223+
if (sym.has_plt(ctx) || sign_extend(val, 26) != val)
224224
val = sym.get_thunk_addr(ctx, P) - P;
225225
*(ub32 *)loc |= bits(val, 25, 2) << 2;
226226
break;

‎src/arch-ppc64v1.cc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -194,7 +194,7 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
194194
break;
195195
case R_PPC64_REL24: {
196196
i64 val = sym.get_addr(ctx, NO_OPD) + A - P;
197-
if (sym.has_plt(ctx) || int_cast(val, 26) != val)
197+
if (sym.has_plt(ctx) || sign_extend(val, 26) != val)
198198
val = sym.get_thunk_addr(ctx, P) + A - P;
199199

200200
check(val, -(1 << 25), 1 << 25);

‎src/arch-ppc64v2.cc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -227,7 +227,7 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
227227
*(ul32 *)(loc + 4) = 0xe841'0018; // ld r2, 24(r1)
228228
} else {
229229
i64 val = S + get_local_entry_offset(ctx, sym) + A - P;
230-
if (int_cast(val, 26) != val)
230+
if (sign_extend(val, 26) != val)
231231
val = no_r2save_thunk_addr() + A - P;
232232
*(ul32 *)loc |= bits(val, 25, 2) << 2;
233233
}
@@ -238,7 +238,7 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
238238
*(ul32 *)loc |= bits(val, 25, 2) << 2;
239239
} else {
240240
i64 val = S + A - P;
241-
if (int_cast(val, 26) != val)
241+
if (sign_extend(val, 26) != val)
242242
val = no_r2save_thunk_addr() + A - P;
243243
*(ul32 *)loc |= bits(val, 25, 2) << 2;
244244
}

‎src/arch-riscv.cc‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -433,7 +433,7 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
433433
// Rewrite `lw t1, 0(t0)` with `lw t1, 0(x0)` if the address is
434434
// accessible relative to the zero register because if that's the
435435
// case, corresponding LUI might have been removed by relaxation.
436-
if (int_cast(S + A, 12) == S + A)
436+
if (sign_extend(S + A, 12) == S + A)
437437
set_rs1(loc, 0);
438438
break;
439439
case R_RISCV_TPREL_HI20:
@@ -457,7 +457,7 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
457457

458458
// Rewrite `lw t1, 0(t0)` with `lw t1, 0(tp)` if the address is
459459
// directly accessible using tp. tp is x4.
460-
if (int_cast(val, 12) == val)
460+
if (sign_extend(val, 12) == val)
461461
set_rs1(loc, 4);
462462
break;
463463
}
@@ -540,7 +540,7 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
540540
write_itype(loc, sym2.get_gottp_addr(ctx) + A - P);
541541
} else {
542542
i64 val = S + A - ctx.tp_addr;
543-
if (int_cast(val, 12) == val)
543+
if (sign_extend(val, 12) == val)
544544
*(ul32 *)loc = 0x513; // addi a0,zero,<lo12>
545545
else
546546
*(ul32 *)loc = 0x50513; // addi a0,a0,<lo12>
@@ -888,15 +888,15 @@ void shrink_section(Context<E> &ctx, InputSection<E> &isec) {
888888

889889
i64 rd = get_rd(buf + r.r_offset + 4);
890890

891-
if (use_rvc && rd == 0 && int_cast(dist, 12) == dist) {
891+
if (use_rvc && rd == 0 && sign_extend(dist, 12) == dist) {
892892
// If rd is x0 and the jump target is within ±2 KiB, we can use
893893
// C.J, saving 6 bytes.
894894
remove(6);
895-
} else if (use_rvc && !E::is_64 && rd == 1 && int_cast(dist, 12) == dist) {
895+
} else if (use_rvc && !E::is_64 && rd == 1 && sign_extend(dist, 12) == dist) {
896896
// If rd is x1 and the jump target is within ±2 KiB, we can use
897897
// C.JAL. This is RV32 only because C.JAL is RV32-only instruction.
898898
remove(6);
899-
} else if (int_cast(dist, 21) == dist) {
899+
} else if (sign_extend(dist, 21) == dist) {
900900
// If the jump target is within ±1 MiB, we can use JAL.
901901
remove(4);
902902
}
@@ -919,10 +919,10 @@ void shrink_section(Context<E> &ctx, InputSection<E> &isec) {
919919
if (rd == get_rd(buf + r.r_offset + 4)) {
920920
u64 val = sym.get_addr(ctx) + r.r_addend;
921921

922-
if (use_rvc && rd != 0 && int_cast(val, 6) == val) {
922+
if (use_rvc && rd != 0 && sign_extend(val, 6) == val) {
923923
// Replace AUIPC + LD with C.LI.
924924
remove(6);
925-
} else if (int_cast(val, 12) == val) {
925+
} else if (sign_extend(val, 12) == val) {
926926
// Replace AUIPC + LD with ADDI.
927927
remove(4);
928928
}
@@ -934,13 +934,13 @@ void shrink_section(Context<E> &ctx, InputSection<E> &isec) {
934934
u64 val = sym.get_addr(ctx) + r.r_addend;
935935
i64 rd = get_rd(buf + r.r_offset);
936936

937-
if (int_cast(val, 12) == val) {
937+
if (sign_extend(val, 12) == val) {
938938
// We can replace `lui t0, %hi(foo)` and `add t0, t0, %lo(foo)`
939939
// instruction pair with `add t0, x0, %lo(foo)` if foo's bits
940940
// [32:11] are all one or all zero.
941941
remove(4);
942942
} else if (use_rvc && rd != 0 && rd != 2 &&
943-
int_cast(val + 0x800, 18) == val + 0x800) {
943+
sign_extend(val + 0x800, 18) == val + 0x800) {
944944
// If the upper 20 bits can actually be represented in 6 bits,
945945
// we can use C.LUI instead of LUI.
946946
remove(2);
@@ -969,7 +969,7 @@ void shrink_section(Context<E> &ctx, InputSection<E> &isec) {
969969
//
970970
// Here, we remove `lui` and `add` if the offset is within ±2 KiB.
971971
if (i64 val = sym.get_addr(ctx) + r.r_addend - ctx.tp_addr;
972-
int_cast(val, 12) == val)
972+
sign_extend(val, 12) == val)
973973
remove(4);
974974
break;
975975
case R_RISCV_TLSDESC_HI20:
@@ -988,7 +988,7 @@ void shrink_section(Context<E> &ctx, InputSection<E> &isec) {
988988
assert(r.r_type == R_RISCV_TLSDESC_ADD_LO12);
989989
if (!sym2.has_tlsdesc(ctx) && !sym2.has_gottp(ctx))
990990
if (i64 val = sym2.get_addr(ctx) + rel2.r_addend - ctx.tp_addr;
991-
int_cast(val, 12) == val)
991+
sign_extend(val, 12) == val)
992992
remove(4);
993993
}
994994
break;

‎src/arch-s390x.cc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -257,7 +257,7 @@ void InputSection<E>::apply_reloc_alloc(Context<E> &ctx, u8 *base) {
257257
u64 op = *(ub16 *)(loc - 2);
258258
u64 val = S + A - P;
259259
if ((op & 0xff0f) == 0xc408 && A == 2 && (val & 1) == 0 &&
260-
int_cast(val, 33) == val) {
260+
sign_extend(val, 33) == val) {
261261
*(ub16 *)(loc - 2) = 0xc000 | (op & 0x00f0);
262262
*(ub32 *)loc = val >> 1;
263263
break;

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