@@ -834,6 +834,7 @@ template <>
834834void shrink_section (Context<E> &ctx, InputSection<E> &isec) {
835835 std::span<const ElfRel<E>> rels = isec.get_rels (ctx);
836836 std::vector<RelocDelta> &deltas = isec.extra .r_deltas ;
837+ i64 r_delta = 0 ;
837838 u8 *buf = (u8 *)isec.contents .data ();
838839
839840 // True if we can use 2-byte instructions. This is usually true on
@@ -844,9 +845,9 @@ void shrink_section(Context<E> &ctx, InputSection<E> &isec) {
844845 const ElfRel<E> &r = rels[i];
845846 Symbol<E> &sym = *isec.file .symbols [r.r_sym ];
846847
847- auto remove = [&](i64 d ) {
848- i64 sum = deltas. empty () ? 0 : deltas. back (). delta ;
849- deltas.push_back (RelocDelta{r.r_offset , sum + d });
848+ auto remove = [&](i64 i ) {
849+ r_delta += i ;
850+ deltas.push_back (RelocDelta{r.r_offset , r_delta });
850851 };
851852
852853 // Handling R_RISCV_ALIGN is mandatory.
@@ -857,7 +858,6 @@ void shrink_section(Context<E> &ctx, InputSection<E> &isec) {
857858 if (r.r_type == R_RISCV_ALIGN) {
858859 // The total bytes of NOPs is stored to r_addend, so the next
859860 // instruction is r_addend away.
860- u64 r_delta = deltas.empty () ? 0 : deltas.back ().delta ;
861861 u64 P = isec.get_addr () + r.r_offset - r_delta;
862862 u64 desired = align_to (P, bit_ceil (r.r_addend ));
863863 u64 actual = P + r.r_addend ;
@@ -999,8 +999,7 @@ void shrink_section(Context<E> &ctx, InputSection<E> &isec) {
999999 }
10001000 }
10011001
1002- if (!deltas.empty ())
1003- isec.sh_size -= deltas.back ().delta ;
1002+ isec.sh_size -= r_delta;
10041003}
10051004
10061005// ISA name handlers
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