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Release v04062019 3.5.0
See Changelog Allow for manual definition of HAVE___SYNC_SYNCHRONIZE, HAVE__MM_MFENCE, or HAVE__MM_SFENCE if the current compile-time probes fail. This really should be put into configure (TODO).
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ChangeLog

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@@ -1,7 +1,7 @@
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ChangeLog file for safeclib
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Changes in v07062019 3.5.0
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Changes in v04062019 3.5.0
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- Updated towctrans case-mappings and normalization to Unicode 12.1
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Even the canon tables on windows need now a special bsearch in an
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exception list, previously only the compat tables.

configure.ac

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@@ -815,9 +815,12 @@ AC_CHECK_FUNCS([__memcpy_chk __memmove_chk __memset_chk \
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__strcpy_chk __strncpy_chk __strcat_chk __strncat_chk \
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__printf_chk __sprintf_chk __snprintf_chk __swprintf_chk \
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__vfprintf_chk __vfwprintf_chk __vsprintf_chk __vsnprintf_chk \
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__vsscanf_chk __vswscanf_chk
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])
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__vsscanf_chk __vswscanf_chk ])
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#done
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dnl They need to include the relevant intrin header first
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dnl TODO: probe for MEMORY_BARRIER and COMPILER_BARRIER here
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dnl AC_CHECK_FUNCS([ __sync_synchronize MemoryBarrier _mm_mfence _mm_sfence \
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dnl __machine_rw_barrier ])
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AC_FUNC_MEMCMP
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dnl no header needed as is checks if the linker can find it
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dnl mbstowcs missing on cygwin64

src/mem/mem_primitives_lib.h

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@@ -127,7 +127,8 @@
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#if defined __KERNEL__
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#define MEMORY_BARRIER mb()
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#elif defined(HAVE_X86_XMM) || defined(HAVE_X86_INTRIN) || defined(HAVE_X86_X86)
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#elif defined(HAVE_X86_XMM) || defined(HAVE_X86_INTRIN) || \
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defined(HAVE_X86_X86) || defined(HAVE__MM_MFENCE)
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#define MEMORY_BARRIER _mm_mfence()
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#elif defined(HAVE_ARM_DMB) && defined(_MSC_VER)
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#define MEMORY_BARRIER __dmb(_ARM_BARRIER_OSH)
@@ -144,14 +145,14 @@
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#define MEMORY_BARRIER ASM_VOLATILE("lock; addl $0,0(%%esp)" ::: "memory")
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#elif defined(ASM_INLINE) && (defined(HAVE_ARM_NEON) || defined(HAVE_ARM_NEON))
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#define MEMORY_BARRIER ASM_VOLATILE("dmb; dsb; isb" ::: "memory")
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#elif defined(__GNUC__) && __GNUC__ >= 4
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#elif (defined(__GNUC__) && __GNUC__ >= 4) || defined(HAVE___SYNC_SYNCHRONIZE)
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#define MEMORY_BARRIER __sync_synchronize()
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/* new gcc-5 memory_barrier insn for most archs:
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x86, mips, nios2, riscv, rs6000, s390, ia64, avr, alpha,
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arc, tilepro, xtensa, ..., but not in the arm-linux-gnueabihf-gcc 8.3 cross
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compiler */
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/* #define MEMORY_BARRIER ASM_VOLATILE("memory_barrier" ::: "memory") */
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#elif defined(HAVE_COMPAT_XMM)
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#elif defined(HAVE_COMPAT_XMM) || defined(HAVE__MM_SFENCE)
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/* x86-compat headers (e.g. rs6000, arm, ...) have no mfence */
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#define MEMORY_BARRIER _mm_sfence()
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#else

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