avoid manual bitshifting for MMU API

Author: robamu

cortex-ar/src/mmu.rs

@@ -20,10 +20,15 @@ pub enum AccessPermissions {
 }
 
 impl AccessPermissions {
+    #[inline]
+    pub const fn new(apx: bool, ap: u2) -> Self {
+        Self::new_with_raw_value(u3::new(((apx as u8) << 2) | ap.value()))
+    }
+
     /// AP bit for the given access permission.
     #[inline]
-    pub const fn ap(&self) -> u8 {
-        (*self as u8) & 0b11
+    pub const fn ap(&self) -> u2 {
+        u2::new((*self as u8) & 0b11)
     }
 
     /// APX bit for the given access permission.
@@ -152,49 +157,46 @@ pub struct SectionAttributes {
 }
 
 impl SectionAttributes {
-    /// Lower 18 bits of the L1 section entry.
-    #[inline]
-    pub const fn raw(&self) -> u32 {
-        ((self.non_global as u32) << 17)
-            | ((self.shareable as u32) << 16)
-            | ((self.access.apx() as u32) << 15)
-            | ((self.memory_attrs.type_extensions.value() as u32) << 12)
-            | ((self.access.ap() as u32) << 10)
-            | ((self.p_bit as u32) << 9)
-            | ((self.domain.value() as u32) << 5)
-            | ((self.execute_never as u32) << 4)
-            | ((self.memory_attrs.c as u32) << 3)
-            | ((self.memory_attrs.b as u32) << 2)
-            | L1EntryType::Section as u32
-    }
-
     /// Extract the section attributes from a raw L1 section entry.
     #[inline]
-    pub fn from_raw(raw: u32) -> Result<Self, InvalidL1EntryType> {
+    fn from_raw(raw: u32) -> Result<Self, InvalidL1EntryType> {
         let section_type = L1EntryType::new_with_raw_value(u2::new((raw & 0b11) as u8));
         if section_type != L1EntryType::Section {
             return Err(InvalidL1EntryType(section_type));
         }
         Ok(Self::from_raw_unchecked(raw))
     }
 
+    /// Retrieves the corresponding L1 section part without the section base address being set.
+    const fn l1_section_part(&self) -> L1Section {
+        L1Section::builder()
+            .with_base_addr(u12::new(0))
+            .with_ng(self.non_global)
+            .with_s(self.shareable)
+            .with_apx(self.access.apx())
+            .with_tex(self.memory_attrs.type_extensions)
+            .with_ap(self.access.ap())
+            .with_p_bit(self.p_bit)
+            .with_domain(self.domain)
+            .with_xn(self.execute_never)
+            .with_c(self.memory_attrs.c)
+            .with_b(self.memory_attrs.b)
+            .with_entry_type(L1EntryType::Section)
+            .build()
+    }
+
     /// Extract the section attributes without checking the entry type bits.
     #[inline]
-    pub const fn from_raw_unchecked(raw: u32) -> Self {
+    const fn from_raw_unchecked(raw: u32) -> Self {
+        let l1 = L1Section::new_with_raw_value(raw);
         Self {
-            non_global: (raw >> 17) & 0x1 != 0,
-            shareable: (raw >> 16) & 0x1 != 0,
-            p_bit: (raw >> 9) & 0x1 != 0,
-            access: AccessPermissions::new_with_raw_value(u3::new(
-                ((((raw >> 15) & 0b1) as u8) << 2) | (((raw >> 10) & 0b11) as u8),
-            )),
-            memory_attrs: MemoryRegionAttributesRaw::new(
-                u3::new(((raw >> 12) & 0b111) as u8),
-                ((raw >> 3) & 0b1) != 0,
-                ((raw >> 2) & 0b1) as u8 != 0,
-            ),
-            domain: u4::new(((raw >> 5) & 0b1111) as u8),
-            execute_never: ((raw >> 4) & 0b1) != 0,
+            non_global: l1.ng(),
+            shareable: l1.s(),
+            p_bit: l1.p_bit(),
+            access: AccessPermissions::new(l1.apx(), l1.ap()),
+            memory_attrs: MemoryRegionAttributesRaw::new(l1.tex(), l1.c(), l1.b()),
+            domain: l1.domain(),
+            execute_never: l1.xn(),
         }
     }
 }
@@ -203,14 +205,14 @@ impl SectionAttributes {
 ///
 /// The ARM Cortex-A architecture programmers manual chapter 9.4 (p.163) specifies these attributes
 /// in more detail.
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, default = 0x00)]
 #[derive(PartialEq, Eq)]
 pub struct L1Section {
     /// Section base address.
     #[bits(20..=31, rw)]
     base_addr: u12,
     /// Non-global bit.
-    #[bit(16, rw)]
+    #[bit(17, rw)]
     ng: bool,
     /// Shareable bit.
     #[bit(16, rw)]
@@ -265,12 +267,25 @@ impl L1Section {
     /// # Panics
     ///
     /// Physcal address not aligned to 1 MB.
-    pub const fn new(phys_addr: u32, section_attrs: SectionAttributes) -> Self {
+    pub const fn new_with_addr_and_attrs(phys_addr: u32, section_attrs: SectionAttributes) -> Self {
         // Must be aligned to 1 MB
         if phys_addr & 0x000F_FFFF != 0 {
             panic!("physical base address for L1 section must be aligned to 1 MB");
         }
         let higher_bits = phys_addr >> 20;
-        Self::new_with_raw_value((higher_bits << 20) | section_attrs.raw())
+        Self::new_with_raw_value((higher_bits << 20) | section_attrs.l1_section_part().raw_value())
+    }
+
+    /// Retrieve the section attributes.
+    #[inline]
+    pub fn section_attrs(&self) -> Result<SectionAttributes, InvalidL1EntryType> {
+        SectionAttributes::from_raw(self.raw_value())
+    }
+
+    /// Set the section attributes without changing the address.
+    #[inline]
+    pub const fn set_section_attrs(&mut self, section_attrs: SectionAttributes) {
+        self.raw_value =
+            ((self.base_addr().value() as u32) << 20) | section_attrs.l1_section_part().raw_value();
     }
 }