[FEATURE REQUEST] Prepare+Execute semantics for SPI/I2C/I3C/UART/etc. #714
Description
In short: I would like to propose - or ask why it hasn't been added yet, if there was an attempt already - a semantic that allows splitting a transaction into a prepare and an execute step.
Background
I am working on a nrf52 based device that pulls data from an IMU. I want the maximum possible sample rate and thus have to utilize the SPI bus as efficient as possible. For that I have set up the IMU in FIFO mode with a watermark interrupt so that I know exactly how many bytes I have to/can transfer from the FIFO in a single read operation.
On the nrf52 this is all implemented via DMA, which takes time to set up.
Proposal
If you know how many bytes you need to transfer but you "don't know" the exact time to start, having prepared the DMA request and the channel set up would allow to trigger the transfer after an GPIO interrupt (in software or via event peripheral) and await that DMA transfer complete event.
DMA setup + trigger + complete-event is a - as far as I have seen - very common architecture which would lend itself to a generic trait.
I am not sure whether such a trait would be a SPI/I2C/UART specific thing or a higher-level Stream-trait that needs some added methods in a bus-trait.