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Remove weak symbols, use abort for defaults.
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3 files changed

+11
-18
lines changed

3 files changed

+11
-18
lines changed

riscv-rt/CHANGELOG.md

+2
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@@ -41,6 +41,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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allow users get the initial address of the heap when initializing an allocator.
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- Update documentation.
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- Removed `.init.rust` section, as it is no longer required.
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- Add global `_abort` symbol, `PROVIDE(abort = _abort)`, and replace `DefaultHandler` and
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`ExceptionHandler` with `PROVIDE(... = abort)`.
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## [v0.13.0] - 2024-10-19
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riscv-rt/link.x.in

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@@ -30,6 +30,10 @@ PROVIDE(_heap_size = 0);
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/** TRAP ENTRY POINTS **/
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/* Default abort entry point. If no abort symbol is provided, then abort maps to _abort. */
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EXTERN(_abort);
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PROVIDE(abort = _abort);
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/* Default trap entry point. The riscv-rt crate provides a weak alias of this function,
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which saves caller saved registers, calls _start_trap_rust, restores caller saved registers
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and then returns. Users can override this alias by defining the symbol themselves */
@@ -54,7 +58,7 @@ PROVIDE(_start_MachineExternal_trap = _start_DefaultHandler_trap);
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/* Default exception handler. The riscv-rt crate provides a weak alias of this function,
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which is a busy loop. Users can override this alias by defining the symbol themselves */
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EXTERN(ExceptionHandler);
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PROVIDE(ExceptionHandler = abort);
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/* It is possible to define a special handler for each exception type.
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By default, all exceptions are handled by ExceptionHandler. However, users can
@@ -76,13 +80,10 @@ PROVIDE(StorePageFault = ExceptionHandler);
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/** INTERRUPT HANDLERS **/
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/* Default interrupt handler. The riscv-rt crate provides a weak alias of this function,
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which is a busy loop. Users can override this alias by defining the symbol themselves */
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EXTERN(DefaultHandler);
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/* It is possible to define a special handler for each interrupt type.
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By default, all interrupts are handled by DefaultHandler. However, users can
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override these alias by defining the symbol themselves */
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PROVIDE(DefaultHandler = abort);
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PROVIDE(SupervisorSoft = DefaultHandler);
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PROVIDE(MachineSoft = DefaultHandler);
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PROVIDE(SupervisorTimer = DefaultHandler);

riscv-rt/src/asm.rs

+3-13
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@@ -251,16 +251,6 @@ _setup_interrupts:",
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#[cfg(not(feature = "s-mode"))]
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"csrw mtvec, t0",
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"ret",
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// Default implementation of `ExceptionHandler` is an infinite loop.
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// Users can override this function by defining their own `ExceptionHandler`
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".weak ExceptionHandler
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ExceptionHandler:
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j ExceptionHandler",
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// Default implementation of `DefaultHandler` is an infinite loop.
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// Users can override this function by defining their own `DefaultHandler`
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".weak DefaultHandler
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DefaultHandler:
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j DefaultHandler",
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// Default implementation of `_pre_init_trap` is an infinite loop.
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// Users can override this function by defining their own `_pre_init_trap`
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// If the execution reaches this point, it means that there is a bug in the boot code.
@@ -278,7 +268,7 @@ riscv_rt_macros::vectored_interrupt_trap!();
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#[rustfmt::skip]
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global_asm!(
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".section .text.abort
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.weak abort
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abort: // make sure there is an abort symbol when linking
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j abort"
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.global _abort
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_abort: // make sure there is an abort symbol when linking
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j _abort"
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);

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