@@ -264,13 +264,13 @@ where
264264 /// has completed
265265 pub ( crate ) fn lora_check_transmit ( & mut self ) -> Result < bool , Error < CommsError , PinError > > {
266266 let irq = self . lora_get_interrupts ( true ) ?;
267- debug ! ( "Poll check send, irq: {:?}" , irq) ;
267+ trace ! ( "Poll check send, irq: {:?}" , irq) ;
268268
269269 if irq. contains ( Irq :: TX_DONE ) {
270270 debug ! ( "Send complete!" ) ;
271271 Ok ( true )
272272 } else {
273- debug ! ( "Send pending" ) ;
273+ trace ! ( "Send pending" ) ;
274274 Ok ( false )
275275 }
276276 }
@@ -344,7 +344,7 @@ where
344344 let mut res = Ok ( false ) ;
345345
346346 if !irq. is_empty ( ) {
347- debug ! ( "Poll check receive, irq: {:?}" , irq) ;
347+ trace ! ( "Poll check receive, irq: {:?}" , irq) ;
348348 }
349349
350350 // Process flags
@@ -392,7 +392,7 @@ where
392392 info. rssi = rssi;
393393 info. snr = Some ( snr) ;
394394
395- debug ! ( "FIFO RX {} bytes with fifo rx ptr: {}" , n, r) ;
395+ trace ! ( "FIFO RX {} bytes with fifo rx ptr: {}" , n, r) ;
396396
397397 // Update FIFO pointer to current RX address
398398 self . write_reg ( regs:: LoRa :: FIFOADDRPTR , r) ?;
@@ -410,7 +410,7 @@ where
410410 // Read data from FIFO
411411 self . hal . read_buff ( & mut data[ 0 ..n] ) ?;
412412
413- debug ! ( "Read data: {:?}" , & data[ 0 ..n] ) ;
413+ debug ! ( "Received data: {:?} info: {:?} " , & data[ 0 ..n] , & info ) ;
414414
415415 Ok ( n)
416416 }
0 commit comments