Skip to content

Commit 2f2c458

Browse files
authored
Merge pull request #3 from ryankurte/fix/gfsk-mode
Fix/gfsk mode
2 parents a680f40 + fd82fc1 commit 2f2c458

File tree

7 files changed

+133
-59
lines changed

7 files changed

+133
-59
lines changed

Cargo.toml

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,9 @@ authors = ["Ryan Kurte <ryankurte@gmail.com>"]
66
repository = "https://github.com/ryankurte/rust-radio-sx127x"
77
license = "MPL-2.0"
88

9+
[package.metadata.commands]
10+
docker-build = "docker run --rm -it -v`pwd`:/work -v$HOME/.cargo/registry:/root/.cargo/registry ryankurte/rust-embedded /bin/bash -c \"cd /work && cargo build --target armv7-unknown-linux-gnueabihf\""
11+
912
[features]
1013
util = [ "structopt", "linux-embedded-hal", "simplelog", "humantime" ]
1114
default = [ "util" ]
@@ -21,7 +24,7 @@ serde = { version = "1.0", default-features = false, features = ["derive"] }
2124

2225
structopt = { version = "0.2.15", optional = true }
2326
linux-embedded-hal = { version = "0.2.2", optional = true }
24-
simplelog = { version = "0.5.3", optional = true }
27+
simplelog = { version = "0.7.3", optional = true }
2528
humantime = { version = "1.2.0", optional = true }
2629

2730
[dev-dependencies]

src/device/fsk.rs

Lines changed: 29 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -68,8 +68,8 @@ impl Default for FskConfig {
6868
Self {
6969
preamble_len: 0x8,
7070
payload_len: PayloadLength::Variable,
71-
dc_free: DcFree::Off,
72-
crc: Crc::Off,
71+
dc_free: DcFree::Whitening,
72+
crc: Crc::On,
7373
crc_autoclear: CrcAutoClear::Off,
7474
address_filter: AddressFilter::Off,
7575
crc_whitening: CrcWhitening::Ccitt,
@@ -78,7 +78,7 @@ impl Default for FskConfig {
7878
beacon: Beacon::Off,
7979
rx_afc: RxAfc::On,
8080
rx_agc: RxAgc::On,
81-
rx_trigger: RxTrigger::Off,
81+
rx_trigger: RxTrigger::PreambleDetect,
8282
node_address: 0,
8383
broadcast_address: 0,
8484
invert_iq: false,
@@ -95,7 +95,7 @@ pub struct FskChannel {
9595
/// (G)FSK frequency in Hz (defaults to 434 MHz)
9696
pub freq: u32,
9797

98-
/// (G)FSK channel baud-rate (defaults to 4.8kbps)
98+
/// (G)FSK channel baud-rate (defaults to 5kbps)
9999
pub br: u32,
100100

101101
/// (G)FSK channel bandwidth
@@ -111,11 +111,11 @@ pub struct FskChannel {
111111
impl Default for FskChannel {
112112
fn default() -> Self {
113113
Self {
114-
freq: 434e6 as u32,
115-
br: 4.8e3 as u32,
114+
freq: 434_000_000,
115+
br: 4_800,
116116
bw: Bandwidth::Bw12500,
117117
bw_afc: Bandwidth::Bw12500,
118-
fdev: 5_000_000,
118+
fdev: 5_000,
119119
}
120120
}
121121
}
@@ -194,8 +194,8 @@ pub const CRC_AUTOCLEAR_MASK: u8 = 0x08;
194194

195195
#[derive(Copy, Clone, PartialEq, Debug, Serialize, Deserialize)]
196196
pub enum CrcAutoClear {
197-
Off = 0x00,
198-
On = 0x08,
197+
Off = 0x08,
198+
On = 0x00,
199199
}
200200

201201
pub const ADDRESS_FILTER_MASK: u8 = 0x08;
@@ -258,14 +258,12 @@ pub const RXCONFIG_RESTARTRXONCOLLISION_MASK: u8 = 0x7F;
258258
pub const RXCONFIG_RESTARTRXONCOLLISION_ON: u8 = 0x80;
259259
pub const RXCONFIG_RESTARTRXONCOLLISION_OFF: u8 = 0x00; // Default
260260

261+
pub const RXCONFIG_RESTARTRX_PLL_MASK: u8 = 0b0110_0000;
261262
pub const RXCONFIG_RESTARTRXWITHOUTPLLLOCK: u8 = 0x40; // Write only
262-
263263
pub const RXCONFIG_RESTARTRXWITHPLLLOCK: u8 = 0x20; // Write only
264264

265265
pub const RXCONFIG_AFCAUTO_MASK: u8 = 0xEF;
266-
267266
pub const RXCONFIG_AGCAUTO_MASK: u8 = 0xF7;
268-
269267
pub const RXCONFIG_RXTRIGER_MASK: u8 = 0xF8;
270268

271269
/// Receive mode Auto Frequency Calibration (AFC)
@@ -291,6 +289,25 @@ pub enum RxTrigger {
291289
RssiPreambleDetect = 0x07,
292290
}
293291

292+
/// Control preamble detector state
293+
#[derive(Copy, Clone, PartialEq, Debug, Serialize, Deserialize)]
294+
pub enum PreambleDetect {
295+
On = 0x80,
296+
Off = 0x00,
297+
}
298+
299+
#[derive(Copy, Clone, PartialEq, Debug, Serialize, Deserialize)]
300+
pub enum PreambleDetectSize {
301+
/// Interrupt on one byte
302+
Ps1 = 0b0000_0000,
303+
/// Interrupt on two bytes
304+
Ps2 = 0b0010_0000,
305+
/// Interrupt on three bytes
306+
Ps3 = 0b0100_0000,
307+
}
308+
309+
pub const PREAMBLE_DETECTOR_TOL: u8 = 0x0A;
310+
294311
bitflags! {
295312
/// Interrupt flags register 1
296313
pub struct Irq1: u8 {

src/device/mod.rs

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,14 @@ pub enum LongRangeMode {
142142
On = 0x80,
143143
}
144144

145+
pub const OPMODE_MODULATION_MASK: u8 = 0b0110_0000;
146+
147+
#[derive(Copy, Clone, PartialEq, Debug)]
148+
pub enum ModulationType {
149+
Fsk = 0b0000_0000,
150+
Ook = 0b0010_0000,
151+
}
152+
145153
#[derive(Copy, Clone, PartialEq, Debug)]
146154
pub enum ModemMode {
147155
Standard,

src/fsk.rs

Lines changed: 27 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ where
3030
config: &FskConfig,
3131
channel: &FskChannel,
3232
) -> Result<(), Error<CommsError, PinError>> {
33-
debug!("Configuring FSK/OOK mode");
33+
debug!("Configuring FSK/OOK mode: {:?} {:?}", config, channel);
3434

3535
// Switch to sleep to change modem mode
3636
self.set_state(State::Sleep)?;
@@ -41,6 +41,9 @@ where
4141
// Set channel configuration
4242
self.fsk_set_channel(channel)?;
4343

44+
// Revert to standby mode
45+
self.set_state(State::Standby)?;
46+
4447
// Set preamble length
4548
self.write_reg(regs::Fsk::PREAMBLEMSB, (config.preamble_len >> 8) as u8)?;
4649
self.write_reg(regs::Fsk::PREAMBLELSB, (config.preamble_len & 0xFF) as u8)?;
@@ -81,9 +84,16 @@ where
8184
self.write_reg(regs::Fsk::PREAMBLEMSB, (config.preamble >> 8) as u8)?;
8285
self.write_reg(regs::Fsk::PREAMBLELSB, config.preamble as u8)?;
8386

87+
// Configure preamble detector
88+
self.write_reg(regs::Fsk::PREAMBLEDETECT,
89+
PreambleDetect::On as u8 |
90+
PreambleDetectSize::Ps2 as u8 |
91+
PREAMBLE_DETECTOR_TOL
92+
)?;
93+
8494
// Configure TXStart
85-
self.hal.write_reg(
86-
regs::Fsk::FIFOTHRESH as u8,
95+
self.write_reg(
96+
regs::Fsk::FIFOTHRESH,
8797
TX_START_FIFOLEVEL | (TX_FIFOTHRESH_MASK & 0x02),
8898
)?;
8999

@@ -111,14 +121,16 @@ where
111121
let irq1 = Irq1::from_bits(reg).unwrap();
112122

113123
if clear {
114-
self.write_reg(regs::Fsk::IRQFLAGS1, reg)?;
124+
self.write_reg(regs::Fsk::IRQFLAGS1,
125+
(irq1 & (Irq1::RSSI | Irq1::PREAMBLED_DETECT)).bits())?;
115126
}
116127

117128
let reg = self.read_reg(regs::Fsk::IRQFLAGS2)?;
118129
let irq2 = Irq2::from_bits(reg).unwrap();
119130

120131
if clear {
121-
self.write_reg(regs::Fsk::IRQFLAGS2, reg)?;
132+
self.write_reg(regs::Fsk::IRQFLAGS2,
133+
(irq2 & (Irq2::LOW_BAT)).bits())?;
122134
}
123135

124136
Ok((irq1, irq2))
@@ -132,13 +144,16 @@ where
132144
// Set frequency
133145
self.set_frequency(channel.freq)?;
134146

147+
// Calculate channel configuration
148+
let fdev = ((channel.fdev as f32) / device::FREQ_STEP).round() as u32;
149+
let datarate = (self.config.xtal_freq as f32 / channel.br as f32).round() as u32;
150+
trace!("fdev: {} bitrate: {}", fdev, datarate);
151+
135152
// Set frequency deviation
136-
let fdev = ((channel.fdev as f32) / device::FREQ_STEP) as u32;
137153
self.write_reg(regs::Fsk::FDEVMSB, (fdev >> 8) as u8)?;
138154
self.write_reg(regs::Fsk::FDEVLSB, (fdev & 0xFF) as u8)?;
139155

140156
// Set bitrate
141-
let datarate = self.config.xtal_freq / channel.br;
142157
self.write_reg(regs::Fsk::BITRATEMSB, (datarate >> 8) as u8)?;
143158
self.write_reg(regs::Fsk::BITRATELSB, (datarate & 0xFF) as u8)?;
144159

@@ -207,8 +222,9 @@ where
207222
let (i1, i2) = self.fsk_get_interrupts(true)?;
208223
debug!("clearing interrupts (irq1: {:?} irq2: {:?})", i1, i2);
209224

210-
// Enter Rx mode
211-
self.set_state_checked(State::Rx)?;
225+
// Enter Rx mode (unchecked as we enter FsRx by default)
226+
// And RX on PreambleDetect (also by default)
227+
self.set_state(State::Rx)?;
212228

213229
debug!("started receive");
214230

@@ -229,7 +245,7 @@ where
229245
let s = self.get_state()?;
230246
let mut res = Ok(false);
231247

232-
debug!(
248+
trace!(
233249
"check receive (state: {:?}, irq1: {:?} irq2: {:?})",
234250
s, i1, i2
235251
);
@@ -281,7 +297,7 @@ where
281297
/// Poll for the current channel RSSI
282298
/// This should only be called in receive mode
283299
pub(crate) fn fsk_poll_rssi(&mut self) -> Result<i16, Error<CommsError, PinError>> {
284-
let raw = self.read_reg(regs::LoRa::RSSIVALUE)? as i8;
300+
let raw = self.read_reg(regs::Fsk::RSSIVALUE)? as i8;
285301

286302
let rssi = (raw / 2) as i16;
287303

src/lib.rs

Lines changed: 25 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ extern crate serde;
1818

1919
use core::convert::TryFrom;
2020
use core::marker::PhantomData;
21+
use core::fmt::Debug;
2122

2223
extern crate embedded_hal as hal;
2324
use hal::blocking::delay;
@@ -234,10 +235,11 @@ where
234235
&mut self,
235236
state: State,
236237
) -> Result<(), Error<CommsError, PinError>> {
237-
trace!("Set state to: {:?}", state);
238+
trace!("Set state to: {:?} (0x{:02x})", state, state as u8);
238239
self.set_state(state)?;
239240
loop {
240241
let s = self.get_state()?;
242+
trace!("Received: {:?}", s);
241243
if state == s {
242244
break;
243245
}
@@ -269,8 +271,8 @@ where
269271
self.set_state(State::Sleep)?;
270272
self.update_reg(
271273
regs::Common::OPMODE,
272-
device::OPMODE_LONGRANGEMODE_MASK,
273-
device::LongRangeMode::Off as u8,
274+
device::OPMODE_LONGRANGEMODE_MASK | device::OPMODE_MODULATION_MASK,
275+
device::LongRangeMode::Off as u8 | device::ModulationType::Fsk as u8,
274276
)?;
275277
}
276278
ModemMode::LoRa => {
@@ -296,6 +298,8 @@ where
296298
(channel >> 0) as u8,
297299
];
298300

301+
debug!("Set channel to index: {:?} (freq: {:?})", channel, freq);
302+
299303
self.hal.write_regs(regs::Common::FRFMSB as u8, &outgoing)?;
300304

301305
Ok(())
@@ -317,6 +321,8 @@ where
317321
/// Calibrate the device RF chain
318322
/// This MUST be called directly after resetting the module
319323
pub(crate) fn rf_chain_calibration(&mut self) -> Result<(), Error<CommsError, PinError>> {
324+
debug!("Running calibration");
325+
320326
// Load initial PA config
321327
let frequency = self.get_frequency()?;
322328
let pa_config = self.read_reg(regs::Common::PACONFIG)?;
@@ -332,6 +338,7 @@ where
332338
)?;
333339

334340
// Block on calibration complete
341+
// TODO: make this fallible with a timeout?
335342
while self.read_reg(regs::Fsk::IMAGECAL)? & (regs::RF_IMAGECAL_IMAGECAL_RUNNING as u8) != 0
336343
{
337344
}
@@ -347,6 +354,7 @@ where
347354
)?;
348355

349356
// Block on calibration complete
357+
// TODO: make this fallible with a timeout?
350358
while self.read_reg(regs::Fsk::IMAGECAL)? & (regs::RF_IMAGECAL_IMAGECAL_RUNNING as u8) != 0
351359
{
352360
}
@@ -355,6 +363,8 @@ where
355363
self.set_frequency(frequency)?;
356364
self.write_reg(regs::Common::PACONFIG, pa_config)?;
357365

366+
debug!("Calibration done");
367+
358368
Ok(())
359369
}
360370
}
@@ -368,10 +378,6 @@ where
368378
hal,
369379
config,
370380
mode: Mode::Unconfigured,
371-
#[cfg(feature = "ffi")]
372-
c: None,
373-
#[cfg(feature = "ffi")]
374-
err: None,
375381
_ce: PhantomData,
376382
_pe: PhantomData,
377383
}
@@ -394,16 +400,22 @@ where
394400
/// Read a u8 value from the specified register
395401
pub fn read_reg<R>(&mut self, reg: R) -> Result<u8, Error<CommsError, PinError>>
396402
where
397-
R: Copy + Clone + Into<u8>,
403+
R: Copy + Clone + Debug + Into<u8>,
398404
{
399-
self.hal.read_reg(reg.into())
405+
let value = self.hal.read_reg(reg.into())?;
406+
407+
trace!("Read reg: {:?} (0x{:02x}): 0x{:02x}", reg, reg.into(), value);
408+
409+
Ok(value)
400410
}
401411

402412
/// Write a u8 value to the specified register
403413
pub fn write_reg<R>(&mut self, reg: R, value: u8) -> Result<(), Error<CommsError, PinError>>
404414
where
405-
R: Copy + Clone + Into<u8>,
415+
R: Copy + Clone + Debug + Into<u8>,
406416
{
417+
trace!("Write reg: {:?} (0x{:02x}): 0x{:02x}", reg, reg.into(), value);
418+
407419
self.hal.write_reg(reg.into(), value)
408420
}
409421

@@ -415,8 +427,10 @@ where
415427
value: u8,
416428
) -> Result<u8, Error<CommsError, PinError>>
417429
where
418-
R: Copy + Clone + Into<u8>,
430+
R: Copy + Clone + Debug + Into<u8>,
419431
{
432+
trace!("Update reg: {:?} (0x{:02x}): 0x{:02x} (0x{:02x})", reg, reg.into(), value, mask);
433+
420434
self.hal.update_reg(reg.into(), mask, value)
421435
}
422436
}

src/lora.rs

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -347,6 +347,12 @@ where
347347
trace!("Poll check receive, irq: {:?}", irq);
348348
}
349349

350+
let state = self.get_state()?;
351+
if state != State::Rx {
352+
warn!("Check receive unexpected state: {:?}", state);
353+
res = Err(Error::Aborted);
354+
}
355+
350356
// Process flags
351357

352358
if irq.contains(Irq::RX_DONE) {

0 commit comments

Comments
 (0)