make x86-64 asm more consistent

Author: RalfJung

ci/run.sh

@@ -33,7 +33,11 @@ case ${TARGET} in
     # Some x86_64 targets enable by default more features beyond SSE2,
     # which cause some instruction assertion checks to fail.
     x86_64-*)
-        export RUSTFLAGS="${RUSTFLAGS} -C target-feature=-sse3"
+        # We want frame pointers to be consistent across targets. On the ios_macabi target
+        # we cannot turn them off, so let's turn them on everywhere.
+        # If we ever turn these off, a bunch of `limit(...)` clauses should be reduced to
+        # avoid tests becoming less strict!
+        export RUSTFLAGS="${RUSTFLAGS} -C target-feature=-sse3 -Cforce-frame-pointers=on"
         ;;
     #Unoptimized build uses fast-isel which breaks with msa
     mips-* | mipsel-*)

crates/core_arch/src/x86/avx2.rs

@@ -2321,7 +2321,7 @@ pub const fn _mm256_or_si256(a: __m256i, b: __m256i) -> __m256i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packs_epi16)
 #[inline]
 #[target_feature(enable = "avx2")]
-#[cfg_attr(test, assert_instr(vpacksswb, limit(2)))]
+#[cfg_attr(test, assert_instr(vpacksswb, limit(5)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(packsswb(a.as_i16x16(), b.as_i16x16())) }
@@ -2333,7 +2333,7 @@ pub fn _mm256_packs_epi16(a: __m256i, b: __m256i) -> __m256i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packs_epi32)
 #[inline]
 #[target_feature(enable = "avx2")]
-#[cfg_attr(test, assert_instr(vpackssdw, limit(2)))]
+#[cfg_attr(test, assert_instr(vpackssdw, limit(5)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(packssdw(a.as_i32x8(), b.as_i32x8())) }
@@ -2345,7 +2345,7 @@ pub fn _mm256_packs_epi32(a: __m256i, b: __m256i) -> __m256i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packus_epi16)
 #[inline]
 #[target_feature(enable = "avx2")]
-#[cfg_attr(test, assert_instr(vpackuswb, limit(2)))]
+#[cfg_attr(test, assert_instr(vpackuswb, limit(5)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(packuswb(a.as_i16x16(), b.as_i16x16())) }
@@ -2357,7 +2357,7 @@ pub fn _mm256_packus_epi16(a: __m256i, b: __m256i) -> __m256i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packus_epi32)
 #[inline]
 #[target_feature(enable = "avx2")]
-#[cfg_attr(test, assert_instr(vpackusdw, limit(2)))]
+#[cfg_attr(test, assert_instr(vpackusdw, limit(5)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm256_packus_epi32(a: __m256i, b: __m256i) -> __m256i {
     unsafe { transmute(packusdw(a.as_i32x8(), b.as_i32x8())) }

crates/core_arch/src/x86/sse2.rs

@@ -1496,7 +1496,7 @@ pub const fn _mm_move_epi64(a: __m128i) -> __m128i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packs_epi16)
 #[inline]
 #[target_feature(enable = "sse2")]
-#[cfg_attr(test, assert_instr(packsswb, limit(2), not(pminsw), not(pmaxsw)))]
+#[cfg_attr(test, assert_instr(packsswb, limit(5), not(pminsw), not(pmaxsw)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(packsswb(a.as_i16x8(), b.as_i16x8())) }
@@ -1508,7 +1508,7 @@ pub fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packs_epi32)
 #[inline]
 #[target_feature(enable = "sse2")]
-#[cfg_attr(test, assert_instr(packssdw, limit(2)))]
+#[cfg_attr(test, assert_instr(packssdw, limit(5)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(packssdw(a.as_i32x4(), b.as_i32x4())) }
@@ -1520,7 +1520,7 @@ pub fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packus_epi16)
 #[inline]
 #[target_feature(enable = "sse2")]
-#[cfg_attr(test, assert_instr(packuswb, limit(2), not(pminsw), not(pmaxsw)))]
+#[cfg_attr(test, assert_instr(packuswb, limit(5), not(pminsw), not(pmaxsw)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_packus_epi16(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(packuswb(a.as_i16x8(), b.as_i16x8())) }

crates/core_arch/src/x86/sse41.rs

@@ -424,7 +424,7 @@ pub const fn _mm_min_epu32(a: __m128i, b: __m128i) -> __m128i {
 /// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packus_epi32)
 #[inline]
 #[target_feature(enable = "sse4.1")]
-#[cfg_attr(test, assert_instr(packusdw, limit(2)))]
+#[cfg_attr(test, assert_instr(packusdw, limit(5)))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
 pub fn _mm_packus_epi32(a: __m128i, b: __m128i) -> __m128i {
     unsafe { transmute(packusdw(a.as_i32x4(), b.as_i32x4())) }