edit index - we are founded baby!

Author: tansiret

about.md

@@ -5,14 +5,14 @@ layout: about
 # About Us
 
 ## Our Vision
-SemiTO-V envisions a future where computing is truly democratized—a future in which both software and hardware are fully open, free from black boxes, proprietary restrictions, and vendor lock-in.
+SemiTO-V team envisions a future where computing is truly democratized—a future in which both software and hardware are fully open, free from black boxes, proprietary restrictions, and vendor lock-in.
 
 This future is made possible by RISC-V, the open standard ISA (Instruction Set Architecture), which, thanks to huge industry support, unlocks unprecedented innovation, collaboration, and accessibility in computing. As students, we aim to participate in this computing revolution.
 
 In line with this vision, we want to build our careers in RISC-V-related fields and contribute to RISC-V as undergraduates and graduates alike. To achieve this, we believe the best way to start is to form a student team dedicated to RISC-V ISA and technologies around it.
 
 ## Our Mission
-Our mission is to inform people about RISC-V and develop projects related to RISC-V. We are organizing educational events and workshops about RISC-V ISA, software and hardware development. We are designing our own application specific RISC-V cores, making our own processor designs (MCU, SoC, PPU etc), designing our own PCBs with FPGA chips, already produced RISC-V based chips and other components to run them, optimizing them for real-world applications (IMU, AI accelerator etc) while improving their software/firmware ecosystem and benchmarking them against other chips.
+Mission of SemiTO-V team is to inform people about RISC-V and develop projects related to RISC-V. We are organizing educational events and workshops about RISC-V ISA, software and hardware development. We are designing our own application specific RISC-V cores, making our own processor designs (MCU, SoC, PPU etc), designing our own PCBs with FPGA chips, already produced RISC-V based chips and other components to run them, optimizing them for real-world applications (IMU, AI accelerator etc) while improving their software/firmware ecosystem and benchmarking them against other chips.
 
 Biggest problem of existing RISC-V hardware is lack of good firmware and software compatibility. For that reason, other than making our own processor design, we also focus on maximizing performance, power efficiency, and software support for existing RISC-V chips, ensuring they are fully utilized across embedded systems, cloud, edge computing, HPC and beyond.
 

index.md

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 layout: home
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-Welcome to our website! *SemiTO-V* is an upcoming RISC-V oriented student community organized by students of [Polytechnic University of Turin](https://www.polito.it/en) that uses open standard [RISC-V ISA](https://en.wikipedia.org/wiki/RISC-V) to create custom processors, firmware, and software as well as our own PCB designs (for our own processors and ones that are already produced), and share them with the world fully open source. We’re mastering everything from circuit analysis to processor architecture, and from RTL design to low-level software development for RISC-V ISA (RV32 and potentially RV64).
+Welcome to our website! *SemiTO-V* is a RISC-V oriented student team organized in [Polytechnic University of Turin](https://www.polito.it/en) that uses open standard [RISC-V ISA](https://en.wikipedia.org/wiki/RISC-V) to create custom processors, firmware, and software as well as our own PCB designs (for our own processors and ones that are already produced), and share them with the world fully open source. We’re mastering everything from circuit analysis to processor architecture, and from RTL design to low-level software development for RISC-V ISA (RV32 and potentially RV64).
 
 Check out [about us page](about) and [projects page](projects) to learn more about our work. Check [team page](team) to see the people that are behind SemiTO-V.