[Feature suggestion] Missing information about the AXI4 System Bus in the documentation

[CyberFox001]

Hello,

First, thank you for this amazing project.

When reading the documentation and the README, it miss 2 information about the AXI4 System Bus:

• What kind of AXI4 is supported by it
• How the peripheral addresses can be set (especially for custom components)

It would be a nice to have in the documentation.

Have a great day.

[sergeykhbr]

Thank you very much for your kind words and feedback!

Adding details about the AXI4 interface would definitely improve the documentation:

• The project supports AXI4 Full; AXI4-Lite can be used but is treated as Full, and AXI4-Stream is supported on request.

• To understand how peripheral addresses are assigned (including for custom components), please take a look at the files gencpu64/types_gencpu64_bus0_pkg.sv and gencpu64/types_gencpu64_bus1_pkg.sv, which define the memory map structure.

• For additional AXI configuration parameters, the companion project rtlgen contains useful tooling and examples.

Also, the README is currently outdated. The project has undergone significant changes since it was last updated, and a thorough revision of the documentation is planned. Your suggestions are very helpful in that direction.

Have a great day!