vivado.log

#-----------------------------------------------------------
# Vivado v2016.2 (64-bit)
# SW Build 1577090 on Thu Jun  2 16:32:40 MDT 2016
# IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016
# Start of session at: Fri Feb 21 12:04:35 2025
# Process ID: 21004
# Current directory: C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent13748 C:\Users\himan\OneDrive\Desktop\finaYRpro\trafficLight - Copy\trafficLight.xpr
# Log file: C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/vivado.log
# Journal file: C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.xpr}
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Lexit
INFO: [Common 17-206] Exiting Vivado at Fri Feb 21 12:05:30 2025...
t: Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 814.438 ; gain = 150.473
update_compile_order -fileset sources_1
launch_simulation -mode post-implementation -type timing
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [Netlist 29-17] Analyzing 26 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2016.2
INFO: [Device 21-403] Loading part xc7a35tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/.Xil/Vivado-21004-LAPTOP-FMPURMC8/dcp/spi_system.xdc]
Finished Parsing XDC File [C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/.Xil/Vivado-21004-LAPTOP-FMPURMC8/dcp/spi_system.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1007.855 ; gain = 0.625
Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1007.855 ; gain = 0.625
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

open_run: Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1099.500 ; gain = 273.082
INFO: [USF-XSim-32] Writing simulation netlist file for design 'impl_1'...
INFO: [USF-XSim-92] write_verilog -mode timesim -nolib -sdf_anno true -force -file "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/impl/timing/tb_spi_system_led_single_reset_time_impl.v"
write_verilog: Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 1200.512 ; gain = 101.012
INFO: [USF-XSim-33] Writing SDF file...
INFO: [USF-XSim-93] write_sdf -mode timesim -process_corner slow -force -file "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/impl/timing/tb_spi_system_led_single_reset_time_impl.sdf"
INFO: [USF-XSim-34] Netlist generated:C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/impl/timing/tb_spi_system_led_single_reset_time_impl.v
INFO: [USF-XSim-35] SDF generated:C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/impl/timing/tb_spi_system_led_single_reset_time_impl.sdf
INFO: [USF-XSim-37] Inspecting design source files for 'tb_spi_system_led_single_reset' in fileset 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/impl/timing'
"xvlog -m64 --relax -prj tb_spi_system_led_single_reset_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/impl/timing/tb_spi_system_led_single_reset_time_impl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module spi_master_2cycle
INFO: [VRFC 10-311] analyzing module spi_slave_led
INFO: [VRFC 10-311] analyzing module spi_slave_led_0
INFO: [VRFC 10-311] analyzing module spi_slave_led_1
INFO: [VRFC 10-311] analyzing module spi_system
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sim_1/new/spi_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_spi_system_led_single_reset
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/impl/timing'
Vivado Simulator 2016.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 7a8e83f47fe24558a70c78115bfb86b1 --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot tb_spi_system_led_single_reset_time_impl -transport_int_delays -pulse_r 0 -pulse_int_r 0 xil_defaultlib.tb_spi_system_led_single_reset xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
INFO: [XSIM 43-3451] SDF backannotation process started with SDF file "tb_spi_system_led_single_reset_time_impl.sdf", for root module "tb_spi_system_led_single_reset/uut".
INFO: [XSIM 43-3452] SDF backannotation was successful for SDF file "tb_spi_system_led_single_reset_time_impl.sdf", for root module "tb_spi_system_led_single_reset/uut".
Time Resolution for simulation is 1ps
Compiling module simprims_ver.BUFG
Compiling module simprims_ver.IBUF
Compiling module simprims_ver.OBUF
Compiling module simprims_ver.LUT4
Compiling module simprims_ver.LUT5
Compiling module simprims_ver.x_lut2_mux4
Compiling module simprims_ver.LUT2
Compiling module simprims_ver.ffsrce_fdce
Compiling module simprims_ver.FDCE
Compiling module simprims_ver.LUT6
Compiling module simprims_ver.ffsrce_fdpe
Compiling module simprims_ver.FDPE
Compiling module simprims_ver.x_lut3_mux4
Compiling module simprims_ver.x_lut3_mux4_reduced_0
Compiling module simprims_ver.LUT3
Compiling module simprims_ver.MUXF7
Compiling module xil_defaultlib.spi_master_2cycle
Compiling module simprims_ver.x_lut1_mux2
Compiling module simprims_ver.LUT1
Compiling module simprims_ver.sffsrce_fdre
Compiling module simprims_ver.FDRE
Compiling module xil_defaultlib.spi_slave_led
Compiling module xil_defaultlib.spi_slave_led_0
Compiling module xil_defaultlib.spi_slave_led_1
Compiling module xil_defaultlib.spi_system
Compiling module xil_defaultlib.tb_spi_system_led_single_reset
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_spi_system_led_single_reset_time_impl
ERROR: [Common 17-165] Too many positional options when parsing '-notrace', please type 'webtalk -help' for usage info.

run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:15 . Memory (MB): peak = 1525.773 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '15' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/impl/timing'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_spi_system_led_single_reset_time_impl -key {Post-Implementation:sim_1:Timing:tb_spi_system_led_single_reset} -tclbatch {tb_spi_system_led_single_reset.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2016.2
Time resolution is 1 ps
source tb_spi_system_led_single_reset.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 100000ns
xsim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 1526.121 ; gain = 0.348
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_spi_system_led_single_reset_time_impl' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 100000ns
launch_simulation: Time (s): cpu = 00:00:37 ; elapsed = 00:01:01 . Memory (MB): peak = 1526.121 ; gain = 699.703
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_spi_system_led_single_reset' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/behav'
"xvlog -m64 --relax -prj tb_spi_system_led_single_reset_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module spi_master_2cycle
INFO: [VRFC 10-311] analyzing module spi_slave_led
INFO: [VRFC 10-311] analyzing module spi_system
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sim_1/new/spi_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_spi_system_led_single_reset
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/behav'
Vivado Simulator 2016.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 7a8e83f47fe24558a70c78115bfb86b1 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_spi_system_led_single_reset_behav xil_defaultlib.tb_spi_system_led_single_reset xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 218. Module spi_system doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 1. Module spi_master_2cycle doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 131. Module spi_slave_led doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 131. Module spi_slave_led doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 131. Module spi_slave_led doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 218. Module spi_system doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 1. Module spi_master_2cycle doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 131. Module spi_slave_led doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 131. Module spi_slave_led doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 131. Module spi_slave_led doesn't have a timescale but at least one module in design has a timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.spi_master_2cycle
Compiling module xil_defaultlib.spi_slave_led
Compiling module xil_defaultlib.spi_system
Compiling module xil_defaultlib.tb_spi_system_led_single_reset
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_spi_system_led_single_reset_behav
ERROR: [Common 17-165] Too many positional options when parsing '-notrace', please type 'webtalk -help' for usage info.

INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_spi_system_led_single_reset_behav -key {Behavioral:sim_1:Functional:tb_spi_system_led_single_reset} -tclbatch {tb_spi_system_led_single_reset.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2016.2
Time resolution is 1 ps
source tb_spi_system_led_single_reset.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 100000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_spi_system_led_single_reset_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 100000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1621.930 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [USF-XSim-27] Simulation object is 'sim_1'
INFO: [USF-XSim-37] Inspecting design source files for 'tb_spi_system_led_single_reset' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/behav'
"xvlog -m64 --relax -prj tb_spi_system_led_single_reset_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module spi_master_2cycle
INFO: [VRFC 10-311] analyzing module spi_slave_led
INFO: [VRFC 10-311] analyzing module spi_system
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sim_1/new/spi_tb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_spi_system_led_single_reset
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/behav'
Vivado Simulator 2016.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 7a8e83f47fe24558a70c78115bfb86b1 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_spi_system_led_single_reset_behav xil_defaultlib.tb_spi_system_led_single_reset xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 219. Module spi_system doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 1. Module spi_master_2cycle doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 132. Module spi_slave_led doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 132. Module spi_slave_led doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 132. Module spi_slave_led doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 219. Module spi_system doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 1. Module spi_master_2cycle doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 132. Module spi_slave_led doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 132. Module spi_slave_led doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/sources_1/new/spi.v" Line 132. Module spi_slave_led doesn't have a timescale but at least one module in design has a timescale.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.spi_master_2cycle
Compiling module xil_defaultlib.spi_slave_led
Compiling module xil_defaultlib.spi_system
Compiling module xil_defaultlib.tb_spi_system_led_single_reset
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_spi_system_led_single_reset_behav
ERROR: [Common 17-165] Too many positional options when parsing '-notrace', please type 'webtalk -help' for usage info.

run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1621.930 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '7' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
   with args "tb_spi_system_led_single_reset_behav -key {Behavioral:sim_1:Functional:tb_spi_system_led_single_reset} -tclbatch {tb_spi_system_led_single_reset.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2016.2
Time resolution is 1 ps
source tb_spi_system_led_single_reset.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 100000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_spi_system_led_single_reset_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 100000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 1621.930 ; gain = 0.000
current_sim simulation_1
restart
INFO: [Simtcl 6-17] Simulation restarted
run 10 us
current_sim simulation_3
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1630.621 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
exit
INFO: [Common 17-206] Exiting Vivado at Fri Feb 28 09:56:51 2025...