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#-----------------------------------------------------------
# Vivado v2016.2 (64-bit)
# SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016
# IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016
# Start of session at: Wed Feb 19 17:23:48 2025
# Process ID: 6976
# Current directory: C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent19780 C:\Users\himan\OneDrive\Desktop\finaYRpro\trafficLight - Copy\trafficLight.xpr
# Log file: C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/vivado.log
# Journal file: C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy\vivado.jou
#-----------------------------------------------------------sstart_guioopen_project {C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.xpr}uupdate_compile_order -fileset sources_1
update_compile_order -fileset sim_1
update_compile_order -fileset sim_1
launch_simulation
source tb_spi_system_led_single_reset.tcl
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
reset_run impl_1 -prev_step
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
update_compile_order -fileset sim_1
launch_simulation
source spi_system.tcl
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
reset_run synth_1
launch_runs synth_1
wait_on_run synth_1
open_run synth_1 -name synth_1
set_property iostandard LVCMOS33 [get_ports [list {data0[7]} {data0[6]} {data0[5]} {data0[4]} {data0[3]} {data0[2]} {data0[1]} {data0[0]} {data1[7]} {data1[6]} {data1[5]} {data1[4]} {data1[3]} {data1[2]} {data1[1]} {data1[0]} {data2[7]} {data2[6]} {data2[5]} {data2[4]} {data2[3]} {data2[2]} {data2[1]} {data2[0]} clk rst led0 led1 led2]]
set_property drive 12 [get_ports [list led0 led1 led2]]
set_property slew SLOW [get_ports [list led0 led1 led2]]
place_ports {data0[0]} A3
place_ports {data0[1]} A1
place_ports {data0[2]} A4
place_ports {data0[3]} A5
place_ports {data0[4]} A6
place_ports {data0[5]} A8
place_ports {data0[6]} A9
place_ports {data0[7]} A10
startgroup
set_property package_pin "" [get_ports [list {data0[0]}]]
place_ports {data0[1]} A3
endgroup
place_ports {data0[0]} A1
place_ports {data1[0]} A11
place_ports {data1[1]} A13
place_ports {data1[2]} A14
place_ports {data1[3]} A15
place_ports {data1[4]} A16
place_ports {data1[5]} A18
set_property package_pin "" [get_ports [list {data1[6]}]]
set_property package_pin "" [get_ports [list {data1[7]}]]
place_ports {data1[6]} B1
place_ports {data1[7]} B2
place_ports {data2[0]} B3
place_ports {data2[1]} B4
place_ports {data2[2]} B6
place_ports {data2[3]} B7
place_ports {data2[4]} B8
place_ports {data2[5]} B9
place_ports {data2[6]} B11
place_ports {data2[7]} B12
close [ open {C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/constrs_1/new/ConstraintsXDC.xdc} w ]
add_files -fileset constrs_1 {{C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/constrs_1/new/ConstraintsXDC.xdc}}
set_property target_constrs_file {C:/Users/himan/OneDrive/Desktop/finaYRpro/trafficLight - Copy/trafficLight.srcs/constrs_1/new/ConstraintsXDC.xdc} [current_fileset -constrset]
save_constraints -force
place_ports clk B13
place_ports led0 B14
place_ports led1 B17
set_property package_pin "" [get_ports [list led2]]
place_ports clk T1
place_ports led0 T3
place_ports led1 T4
place_ports led2 T5
place_ports rst T6
save_constraints
reset_run synth_1
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
save_constraints -force
reset_run impl_1
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
close_design
open_run impl_1
update_compile_order -fileset sim_1
update_compile_order -fileset sim_1
current_sim simulation_1
close_sim
launch_simulation
source tb_spi_system_led_single_reset.tcl
close_sim
launch_simulation
launch_simulation
source tb_spi_system_led_single_reset.tcl
close_sim
launch_simulation
source tb_spi_system_led_single_reset.tcl
close_sim
launch_simulation
source tb_spi_system_led_single_reset.tcl
close_sim
launch_simulation
source tb_spi_system_led_single_reset.tcl
close_sim
launch_simulation
launch_simulation
source tb_spi_system_led_single_reset.tcl
close_sim
launch_simulation
source tb_spi_system_led_single_reset.tcl
close_sim
launch_simulation
source tb_spi_system_led_single_reset.tcl
reset_run synth_1
launch_runs synth_1
wait_on_run synth_1
open_run synth_1 -name synth_1
set_property is_loc_fixed false [get_ports [list {data0[7]} {data0[6]} {data0[5]} {data0[4]} {data0[3]} {data0[2]} {data0[1]} {data0[0]}]]
set_property is_loc_fixed true [get_ports [list {data0[7]} {data0[6]} {data0[5]} {data0[4]} {data0[3]} {data0[2]} {data0[1]} {data0[0]}]]
set_property is_loc_fixed false [get_ports [list {data0[7]} {data0[6]} {data0[5]} {data0[4]} {data0[3]} {data0[2]} {data0[1]} {data0[0]}]]
set_property is_loc_fixed false [get_ports [list {data1[7]} {data1[6]} {data1[5]} {data1[4]} {data1[3]} {data1[2]} {data1[1]} {data1[0]}]]
set_property is_loc_fixed false [get_ports [list {data2[7]} {data2[6]} {data2[5]} {data2[4]} {data2[3]} {data2[2]} {data2[1]} {data2[0]}]]
set_property IOSTANDARD LVCMOS33 [get_ports [list {data0[7]} {data0[6]} {data0[5]} {data0[4]} {data0[3]} {data0[2]} {data0[1]} {data0[0]}]]
current_design impl_1
set_property is_loc_fixed false [get_ports [list {data2[7]}]]
set_property is_loc_fixed true [get_ports [list {data2[7]}]]
set_property is_loc_fixed false [get_ports [list {data0[7]} {data0[6]} {data0[5]} {data0[4]} {data0[3]} {data0[2]} {data0[1]} {data0[0]}]]
set_property is_loc_fixed false [get_ports [list {data1[7]} {data1[6]} {data1[5]} {data1[4]} {data1[3]} {data1[2]} {data1[1]} {data1[0]}]]
set_property is_loc_fixed false [get_ports [list {data2[7]} {data2[6]} {data2[5]} {data2[4]} {data2[3]} {data2[2]} {data2[1]} {data2[0]}]]
save_constraints -force
current_design synth_1
save_constraints -force
current_design impl_1
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
set_property is_loc_fixed true [get_ports [list {data0[7]} {data0[6]} {data0[5]} {data0[4]} {data0[3]} {data0[2]} {data0[1]} {data0[0]}]]
set_property is_loc_fixed true [get_ports [list {data1[7]} {data1[6]} {data1[5]} {data1[4]} {data1[3]} {data1[2]} {data1[1]} {data1[0]}]]
set_property is_loc_fixed true [get_ports [list {data2[7]} {data2[6]} {data2[5]} {data2[4]} {data2[3]} {data2[2]} {data2[1]} {data2[0]}]]
save_constraints -force
reset_run impl_1
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
close_sim
launch_simulation
source tb_spi_system_led_single_reset.tcl
close_sim
close_sim