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shufpsPmaxsd
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1373 support (#597)
* initial q1373 support --------- Co-authored-by: Pmaxsd <pmaxsd80@gmail.com>
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components/bm1397/bm1373.cpp

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#include <endian.h>
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#include <math.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <stdarg.h>
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#include <stddef.h>
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#include "esp_log.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "asic.h"
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#include "bm1373.h"
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#include "crc.h"
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#include "serial.h"
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#include "mining_utils.h"
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static const char *TAG = "bm1373Module";
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static const uint8_t chip_id[6] = {0xaa, 0x55, 0x13, 0x72, 0x00, 0x00};
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static const uint64_t BM1373_CORE_COUNT = 128;
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static const uint64_t BM1373_SMALL_CORE_COUNT = 2040;
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#define REG_NONCE_TOTAL_CNT 0x8c
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BM1373::BM1373() : BM1370() {
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// NOP
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}
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const uint8_t* BM1373::getChipId() {
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return (uint8_t*) chip_id;
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}
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uint32_t BM1373::getDefaultVrFrequency() {
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return vrRegToFreq(0x1eb5);
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};
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uint8_t BM1373::init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty, uint32_t vrFrequency)
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{
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// reset is done externally to not have board dependencies
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// enable and set version rolling mask to 0xFFFF
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send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF);
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// enable and set version rolling mask to 0xFFFF (again)
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send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF);
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// enable and set version rolling mask to 0xFFFF (again)
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send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF);
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// enable and set version rolling mask to 0xFFFF (again)
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send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF);
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int chip_counter = count_asics();
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ESP_LOGIE(chip_counter == asic_count, TAG, "%i chip(s) detected on the chain, expected %i", chip_counter, asic_count);
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// enable and set version rolling mask to 0xFFFF (again)
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send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF);
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// Reg_A8
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send6(CMD_WRITE_ALL, 0x00, 0xA8, 0x00, 0x07, 0x00, 0x00);
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// Misc Control
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send6(CMD_WRITE_ALL, 0x00, 0x18, 0xFf, 0x00, 0xC1, 0x00);
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// chain inactive
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sendChainInactive();
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// set chip address - distribute evenly across 0-255 range
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m_addressInterval = (chip_counter > 0) ? (256 / next_power_of_two(chip_counter)) : 4;
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for (uint8_t i = 0; i < chip_counter; i++) {
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setChipAddress(i * m_addressInterval);
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}
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// Core Register Control
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send6(CMD_WRITE_ALL, 0x00, 0x3C, 0x80, 0x00, 0x8B, 0x00);
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// Core Register Control
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send6(CMD_WRITE_ALL, 0x00, 0x3C, 0x80, 0x00, 0x80, 0x0C);
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setJobDifficultyMask(difficulty);
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// Set the IO Driver Strength on chip 00
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send6(CMD_WRITE_ALL, 0x00, 0x58, 0x00, 0x01, 0x11, 0x11);
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// ?
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send6(CMD_WRITE_ALL, 0x00, 0x68, 0x5A, 0xA5, 0x5A, 0xA5);
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for (uint8_t i = 0; i < chip_counter; i++) {
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uint8_t addr = i * m_addressInterval;
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// Reg_A8
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send6(CMD_WRITE_SINGLE, addr, 0xA8, 0x00, 0x07, 0x01, 0xF0);
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// Misc Control
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send6(CMD_WRITE_SINGLE, addr, 0x18, 0xFF, 0x00, 0xC1, 0x00);
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// Core Register Control
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send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x8B, 0x00);
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// Core Register Control
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send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x80, 0x0c);
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// Core Register Control
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send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x82, 0xAA);
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}
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// ?
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send6(CMD_WRITE_ALL, 0x00, 0xB9, 0x00, 0x00, 0x44, 0x80);
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// Analog Mux Control
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send6(CMD_WRITE_ALL, 0x00, 0x54, 0x00, 0x00, 0x00, 0x02);
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// ?
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send6(CMD_WRITE_ALL, 0x00, 0xB9, 0x00, 0x00, 0x44, 0x80);
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// Core Register Control
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send6(CMD_WRITE_ALL, 0x00, 0x3C, 0x80, 0x00, 0x8D, 0xEE);
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doFrequencyTransition(frequency);
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// set 0x10
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setVrFrequency(vrFrequency);
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send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF);
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return chip_counter;
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}
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uint16_t BM1373::getSmallCoreCount() {
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return BM1373_SMALL_CORE_COUNT;
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}

components/bm1397/include/bm1373.h

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#pragma once
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#include "bm1370.h"
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class BM1373 : public BM1370 {
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protected:
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virtual const uint8_t* getChipId();
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virtual uint32_t getDefaultVrFrequency();
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public:
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BM1373();
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virtual const char* getName() { return "BM1373"; };
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virtual uint8_t init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty, uint32_t vrFrequency);
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virtual uint16_t getSmallCoreCount();
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};

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