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| 1 | +#include <endian.h> |
| 2 | +#include <math.h> |
| 3 | +#include <stdint.h> |
| 4 | +#include <stdio.h> |
| 5 | +#include <stdlib.h> |
| 6 | +#include <string.h> |
| 7 | +#include <stdarg.h> |
| 8 | +#include <stddef.h> |
| 9 | + |
| 10 | +#include "esp_log.h" |
| 11 | +#include "freertos/FreeRTOS.h" |
| 12 | +#include "freertos/task.h" |
| 13 | + |
| 14 | +#include "asic.h" |
| 15 | +#include "bm1373.h" |
| 16 | + |
| 17 | +#include "crc.h" |
| 18 | +#include "serial.h" |
| 19 | +#include "mining_utils.h" |
| 20 | + |
| 21 | + |
| 22 | +static const char *TAG = "bm1373Module"; |
| 23 | + |
| 24 | +static const uint8_t chip_id[6] = {0xaa, 0x55, 0x13, 0x72, 0x00, 0x00}; |
| 25 | + |
| 26 | +static const uint64_t BM1373_CORE_COUNT = 128; |
| 27 | +static const uint64_t BM1373_SMALL_CORE_COUNT = 2040; |
| 28 | + |
| 29 | +#define REG_NONCE_TOTAL_CNT 0x8c |
| 30 | + |
| 31 | +BM1373::BM1373() : BM1370() { |
| 32 | + // NOP |
| 33 | +} |
| 34 | + |
| 35 | +const uint8_t* BM1373::getChipId() { |
| 36 | + return (uint8_t*) chip_id; |
| 37 | +} |
| 38 | + |
| 39 | +uint32_t BM1373::getDefaultVrFrequency() { |
| 40 | + return vrRegToFreq(0x1eb5); |
| 41 | +}; |
| 42 | + |
| 43 | +uint8_t BM1373::init(uint64_t frequency, uint16_t asic_count, uint32_t difficulty, uint32_t vrFrequency) |
| 44 | +{ |
| 45 | + // reset is done externally to not have board dependencies |
| 46 | + |
| 47 | + // enable and set version rolling mask to 0xFFFF |
| 48 | + send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF); |
| 49 | + |
| 50 | + // enable and set version rolling mask to 0xFFFF (again) |
| 51 | + send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF); |
| 52 | + |
| 53 | + // enable and set version rolling mask to 0xFFFF (again) |
| 54 | + send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF); |
| 55 | + |
| 56 | + // enable and set version rolling mask to 0xFFFF (again) |
| 57 | + send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF); |
| 58 | + |
| 59 | + int chip_counter = count_asics(); |
| 60 | + ESP_LOGIE(chip_counter == asic_count, TAG, "%i chip(s) detected on the chain, expected %i", chip_counter, asic_count); |
| 61 | + |
| 62 | + // enable and set version rolling mask to 0xFFFF (again) |
| 63 | + send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF); |
| 64 | + |
| 65 | + // Reg_A8 |
| 66 | + send6(CMD_WRITE_ALL, 0x00, 0xA8, 0x00, 0x07, 0x00, 0x00); |
| 67 | + |
| 68 | + // Misc Control |
| 69 | + send6(CMD_WRITE_ALL, 0x00, 0x18, 0xFf, 0x00, 0xC1, 0x00); |
| 70 | + |
| 71 | + // chain inactive |
| 72 | + sendChainInactive(); |
| 73 | + |
| 74 | + // set chip address - distribute evenly across 0-255 range |
| 75 | + m_addressInterval = (chip_counter > 0) ? (256 / next_power_of_two(chip_counter)) : 4; |
| 76 | + for (uint8_t i = 0; i < chip_counter; i++) { |
| 77 | + setChipAddress(i * m_addressInterval); |
| 78 | + } |
| 79 | + |
| 80 | + // Core Register Control |
| 81 | + send6(CMD_WRITE_ALL, 0x00, 0x3C, 0x80, 0x00, 0x8B, 0x00); |
| 82 | + |
| 83 | + // Core Register Control |
| 84 | + send6(CMD_WRITE_ALL, 0x00, 0x3C, 0x80, 0x00, 0x80, 0x0C); |
| 85 | + |
| 86 | + setJobDifficultyMask(difficulty); |
| 87 | + |
| 88 | + // Set the IO Driver Strength on chip 00 |
| 89 | + send6(CMD_WRITE_ALL, 0x00, 0x58, 0x00, 0x01, 0x11, 0x11); |
| 90 | + |
| 91 | + // ? |
| 92 | + send6(CMD_WRITE_ALL, 0x00, 0x68, 0x5A, 0xA5, 0x5A, 0xA5); |
| 93 | + |
| 94 | + for (uint8_t i = 0; i < chip_counter; i++) { |
| 95 | + uint8_t addr = i * m_addressInterval; |
| 96 | + // Reg_A8 |
| 97 | + send6(CMD_WRITE_SINGLE, addr, 0xA8, 0x00, 0x07, 0x01, 0xF0); |
| 98 | + // Misc Control |
| 99 | + send6(CMD_WRITE_SINGLE, addr, 0x18, 0xFF, 0x00, 0xC1, 0x00); |
| 100 | + // Core Register Control |
| 101 | + send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x8B, 0x00); |
| 102 | + // Core Register Control |
| 103 | + send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x80, 0x0c); |
| 104 | + // Core Register Control |
| 105 | + send6(CMD_WRITE_SINGLE, addr, 0x3C, 0x80, 0x00, 0x82, 0xAA); |
| 106 | + } |
| 107 | + |
| 108 | + // ? |
| 109 | + send6(CMD_WRITE_ALL, 0x00, 0xB9, 0x00, 0x00, 0x44, 0x80); |
| 110 | + |
| 111 | + // Analog Mux Control |
| 112 | + send6(CMD_WRITE_ALL, 0x00, 0x54, 0x00, 0x00, 0x00, 0x02); |
| 113 | + |
| 114 | + // ? |
| 115 | + send6(CMD_WRITE_ALL, 0x00, 0xB9, 0x00, 0x00, 0x44, 0x80); |
| 116 | + |
| 117 | + // Core Register Control |
| 118 | + send6(CMD_WRITE_ALL, 0x00, 0x3C, 0x80, 0x00, 0x8D, 0xEE); |
| 119 | + |
| 120 | + doFrequencyTransition(frequency); |
| 121 | + |
| 122 | + // set 0x10 |
| 123 | + setVrFrequency(vrFrequency); |
| 124 | + |
| 125 | + send6(CMD_WRITE_ALL, 0x00, 0xA4, 0x90, 0x00, 0xFF, 0xFF); |
| 126 | + |
| 127 | + return chip_counter; |
| 128 | +} |
| 129 | + |
| 130 | +uint16_t BM1373::getSmallCoreCount() { |
| 131 | + return BM1373_SMALL_CORE_COUNT; |
| 132 | +} |
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