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| 1 | +<registers> |
| 2 | + <register> |
| 3 | + <name>control</name> |
| 4 | + <description>Basic control register</description> |
| 5 | + <addressOffset>0x0</addressOffset> |
| 6 | + <fields> |
| 7 | + <field> |
| 8 | + <name>enable</name> |
| 9 | + <description>Enable hardware prefetcher</description> |
| 10 | + <bitRange>[0:0]</bitRange> |
| 11 | + <access>read-write</access> |
| 12 | + </field> |
| 13 | + <field> |
| 14 | + <name>disxpageoptm</name> |
| 15 | + <description>Cross Page optimization disable</description> |
| 16 | + <bitRange>[1:1]</bitRange> |
| 17 | + <access>read-write</access> |
| 18 | + </field> |
| 19 | + <field> |
| 20 | + <name>distance</name> |
| 21 | + <description>Prefetch distance</description> |
| 22 | + <bitRange>[7:2]</bitRange> |
| 23 | + <access>read-write</access> |
| 24 | + </field> |
| 25 | + <field> |
| 26 | + <name>maxallowdist</name> |
| 27 | + <description>Maximum allowed distance</description> |
| 28 | + <bitRange>[13:8]</bitRange> |
| 29 | + <access>read-write</access> |
| 30 | + </field> |
| 31 | + <field> |
| 32 | + <name>lineartoexpthrs</name> |
| 33 | + <description>Linear to exponential threshold</description> |
| 34 | + <bitRange>[19:14]</bitRange> |
| 35 | + <access>read-write</access> |
| 36 | + </field> |
| 37 | + <field> |
| 38 | + <name>ageoutenable</name> |
| 39 | + <description>Ageout mechanism enable</description> |
| 40 | + <bitRange>[20:20]</bitRange> |
| 41 | + <access>read-write</access> |
| 42 | + </field> |
| 43 | + <field> |
| 44 | + <name>numldtoageout</name> |
| 45 | + <description>Number of non-matching loads to edge out an entry</description> |
| 46 | + <bitRange>[27:21]</bitRange> |
| 47 | + <access>read-write</access> |
| 48 | + </field> |
| 49 | + <field> |
| 50 | + <name>xpageenable</name> |
| 51 | + <description>Enable prefetches to cross pages</description> |
| 52 | + <bitRange>[28:28]</bitRange> |
| 53 | + <access>read-write</access> |
| 54 | + </field> |
| 55 | + </fields> |
| 56 | + </register> |
| 57 | + <register> |
| 58 | + <name>user</name> |
| 59 | + <description>L2 users bits control register</description> |
| 60 | + <addressOffset>0x4</addressOffset> |
| 61 | + <fields> |
| 62 | + <field> |
| 63 | + <name>qfullnessthrs</name> |
| 64 | + <description>Threshold number of Fullness to stop sending hits</description> |
| 65 | + <bitRange>[3:0]</bitRange> |
| 66 | + <access>read-write</access> |
| 67 | + </field> |
| 68 | + <field> |
| 69 | + <name>hitcachethrs</name> |
| 70 | + <description>Threshold number of CacheHits for evicting SPF entry</description> |
| 71 | + <bitRange>[8:4]</bitRange> |
| 72 | + <access>read-write</access> |
| 73 | + </field> |
| 74 | + <field> |
| 75 | + <name>hitmshrthrs</name> |
| 76 | + <description>Threshold number of MSHR hits for increasing SPF distance</description> |
| 77 | + <bitRange>[12:9]</bitRange> |
| 78 | + <access>read-write</access> |
| 79 | + </field> |
| 80 | + <field> |
| 81 | + <name>window</name> |
| 82 | + <description>Size of the comparison window for address matching</description> |
| 83 | + <bitRange>[18:13]</bitRange> |
| 84 | + <access>read-write</access> |
| 85 | + </field> |
| 86 | + </fields> |
| 87 | + </register> |
| 88 | +</registers> |
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