Spratan 6 porting issue

[mopplayer]

Hi,
I am porting E300 SOC to Spratan 6 FPGA.
But got this error:
Place:1136 - This design contains a global buffer instance, <slow_clock_BUFG>, driving the net, <slow_clock_BUFG>, that is driving the following (first 30) non-clock load pins. < PIN: E300ArtyDevKitPlatform/sys/rtc/Mshreg_sync_0.DI1; > This is not a recommended design practice in Spartan-6 due to limitations in the global routing that may cause excessive delay, skew or unroutable situations. It is recommended to only use a BUFG resource to drive clock loads. If you wish to override this recommendation, you may use the CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote this message to a WARNING and allow your design to continue. < PIN "slow_clock_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; >

I check this connection, and I have found this:
SynchronizerShiftReg_w1_d3 rtc ( // @[ShiftReg.scala 47:23:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@294141.4] .clock(rtc_clock), .io_d(rtc_io_d), .io_q(rtc_io_q) );
assign rtc_io_d = $unsigned(aon_1_io_rtc); // @[ShiftReg.scala 49:16:sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.fir@294145.4]
.io_rtc(aon_1_io_rtc),

And io_rtc is came from aon_pins_lfextclk_i_ival (<- slow_clock) , which is inserted a BUFG between them.

How to solve it?
Thanks.