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jamesmunnsjamesmunns
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Remove Result type alias
1 parent ff961ec commit 664d245

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4 files changed

+56
-59
lines changed

4 files changed

+56
-59
lines changed

‎embassy-mcxa/src/lpuart/blocking.rs‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ impl<'a> Lpuart<'a, Blocking> {
1717
tx_pin: Peri<'a, impl TxPin<T>>,
1818
rx_pin: Peri<'a, impl RxPin<T>>,
1919
config: Config,
20-
) -> Result<Self> {
20+
) -> Result<Self, Error> {
2121
// Configure the pins for LPUART usage
2222
tx_pin.as_tx();
2323
rx_pin.as_rx();
@@ -39,7 +39,7 @@ impl<'a> Lpuart<'a, Blocking> {
3939
cts_pin: Peri<'a, impl CtsPin<T>>,
4040
rts_pin: Peri<'a, impl RtsPin<T>>,
4141
config: Config,
42-
) -> Result<Self> {
42+
) -> Result<Self, Error> {
4343
// Configure the pins for LPUART usage
4444
rx_pin.as_rx();
4545
tx_pin.as_tx();
@@ -54,21 +54,21 @@ impl<'a> Lpuart<'a, Blocking> {
5454
}
5555

5656
/// Read data from LPUART RX blocking execution until the buffer is filled
57-
pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<()> {
57+
pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<(), Error> {
5858
self.rx.blocking_read(buf)
5959
}
6060

6161
/// Read data from LPUART RX without blocking
62-
pub fn read(&mut self, buf: &mut [u8]) -> Result<()> {
62+
pub fn read(&mut self, buf: &mut [u8]) -> Result<(), Error> {
6363
self.rx.read(buf)
6464
}
6565

6666
/// Write data to LPUART TX blocking execution until all data is sent
67-
pub fn blocking_write(&mut self, buf: &[u8]) -> Result<()> {
67+
pub fn blocking_write(&mut self, buf: &[u8]) -> Result<(), Error> {
6868
self.tx.blocking_write(buf)
6969
}
7070

71-
pub fn write_byte(&mut self, byte: u8) -> Result<()> {
71+
pub fn write_byte(&mut self, byte: u8) -> Result<(), Error> {
7272
self.tx.write_byte(byte)
7373
}
7474

@@ -85,17 +85,17 @@ impl<'a> Lpuart<'a, Blocking> {
8585
}
8686

8787
/// Write data to LPUART TX without blocking
88-
pub fn write(&mut self, buf: &[u8]) -> Result<()> {
88+
pub fn write(&mut self, buf: &[u8]) -> Result<(), Error> {
8989
self.tx.write(buf)
9090
}
9191

9292
/// Flush LPUART TX blocking execution until all data has been transmitted
93-
pub fn blocking_flush(&mut self) -> Result<()> {
93+
pub fn blocking_flush(&mut self) -> Result<(), Error> {
9494
self.tx.blocking_flush()
9595
}
9696

9797
/// Flush LPUART TX without blocking
98-
pub fn flush(&mut self) -> Result<()> {
98+
pub fn flush(&mut self) -> Result<(), Error> {
9999
self.tx.flush()
100100
}
101101
}
@@ -108,7 +108,7 @@ impl<'a> LpuartTx<'a, Blocking> {
108108
_inner: Peri<'a, T>,
109109
tx_pin: Peri<'a, impl TxPin<T>>,
110110
config: Config,
111-
) -> Result<Self> {
111+
) -> Result<Self, Error> {
112112
// Configure the pins for LPUART usage
113113
tx_pin.as_tx();
114114

@@ -124,26 +124,26 @@ impl<'a> LpuartTx<'a, Blocking> {
124124
tx_pin: Peri<'a, impl TxPin<T>>,
125125
cts_pin: Peri<'a, impl CtsPin<T>>,
126126
config: Config,
127-
) -> Result<Self> {
127+
) -> Result<Self, Error> {
128128
tx_pin.as_tx();
129129
cts_pin.as_cts();
130130

131131
let wg = Lpuart::<Blocking>::init::<T>(true, false, true, false, config)?;
132132
Ok(Self::new_inner::<T>(tx_pin.into(), Some(cts_pin.into()), Blocking, wg))
133133
}
134134

135-
fn write_byte_internal(&mut self, byte: u8) -> Result<()> {
135+
fn write_byte_internal(&mut self, byte: u8) -> Result<(), Error> {
136136
self.info.regs().data().modify(|w| w.0 = u32::from(byte));
137137

138138
Ok(())
139139
}
140140

141-
fn blocking_write_byte(&mut self, byte: u8) -> Result<()> {
141+
fn blocking_write_byte(&mut self, byte: u8) -> Result<(), Error> {
142142
while self.info.regs().stat().read().tdre() == Tdre::TXDATA {}
143143
self.write_byte_internal(byte)
144144
}
145145

146-
fn write_byte(&mut self, byte: u8) -> Result<()> {
146+
fn write_byte(&mut self, byte: u8) -> Result<(), Error> {
147147
if self.info.regs().stat().read().tdre() == Tdre::TXDATA {
148148
Err(Error::TxFifoFull)
149149
} else {
@@ -152,7 +152,7 @@ impl<'a> LpuartTx<'a, Blocking> {
152152
}
153153

154154
/// Write data to LPUART TX blocking execution until all data is sent.
155-
pub fn blocking_write(&mut self, buf: &[u8]) -> Result<()> {
155+
pub fn blocking_write(&mut self, buf: &[u8]) -> Result<(), Error> {
156156
for x in buf {
157157
self.blocking_write_byte(*x)?;
158158
}
@@ -165,7 +165,7 @@ impl<'a> LpuartTx<'a, Blocking> {
165165
}
166166

167167
/// Write data to LPUART TX without blocking.
168-
pub fn write(&mut self, buf: &[u8]) -> Result<()> {
168+
pub fn write(&mut self, buf: &[u8]) -> Result<(), Error> {
169169
for x in buf {
170170
self.write_byte(*x)?;
171171
}
@@ -174,7 +174,7 @@ impl<'a> LpuartTx<'a, Blocking> {
174174
}
175175

176176
/// Flush LPUART TX blocking execution until all data has been transmitted.
177-
pub fn blocking_flush(&mut self) -> Result<()> {
177+
pub fn blocking_flush(&mut self) -> Result<(), Error> {
178178
while self.info.regs().water().read().txcount() != 0 {
179179
// Wait for TX FIFO to drain
180180
}
@@ -188,7 +188,7 @@ impl<'a> LpuartTx<'a, Blocking> {
188188
}
189189

190190
/// Flush LPUART TX.
191-
pub fn flush(&mut self) -> Result<()> {
191+
pub fn flush(&mut self) -> Result<(), Error> {
192192
// Check if TX FIFO is empty
193193
if self.info.regs().water().read().txcount() != 0 {
194194
return Err(Error::TxBusy);
@@ -211,7 +211,7 @@ impl<'a> LpuartRx<'a, Blocking> {
211211
_inner: Peri<'a, T>,
212212
rx_pin: Peri<'a, impl RxPin<T>>,
213213
config: Config,
214-
) -> Result<Self> {
214+
) -> Result<Self, Error> {
215215
rx_pin.as_rx();
216216

217217
let wg = Lpuart::<Blocking>::init::<T>(false, true, false, false, config)?;
@@ -226,19 +226,19 @@ impl<'a> LpuartRx<'a, Blocking> {
226226
rx_pin: Peri<'a, impl RxPin<T>>,
227227
rts_pin: Peri<'a, impl RtsPin<T>>,
228228
config: Config,
229-
) -> Result<Self> {
229+
) -> Result<Self, Error> {
230230
rx_pin.as_rx();
231231
rts_pin.as_rts();
232232

233233
let wg = Lpuart::<Blocking>::init::<T>(false, true, false, true, config)?;
234234
Ok(Self::new_inner::<T>(rx_pin.into(), Some(rts_pin.into()), Blocking, wg))
235235
}
236236

237-
fn read_byte_internal(&mut self) -> Result<u8> {
237+
fn read_byte_internal(&mut self) -> Result<u8, Error> {
238238
Ok((self.info.regs().data().read().0 & 0xFF) as u8)
239239
}
240240

241-
fn read_byte(&mut self) -> Result<u8> {
241+
fn read_byte(&mut self) -> Result<u8, Error> {
242242
check_and_clear_rx_errors(self.info)?;
243243

244244
if !has_rx_data_pending(self.info) {
@@ -248,7 +248,7 @@ impl<'a> LpuartRx<'a, Blocking> {
248248
self.read_byte_internal()
249249
}
250250

251-
fn blocking_read_byte(&mut self) -> Result<u8> {
251+
fn blocking_read_byte(&mut self) -> Result<u8, Error> {
252252
loop {
253253
if has_rx_data_pending(self.info) {
254254
return self.read_byte_internal();
@@ -259,15 +259,15 @@ impl<'a> LpuartRx<'a, Blocking> {
259259
}
260260

261261
/// Read data from LPUART RX without blocking.
262-
pub fn read(&mut self, buf: &mut [u8]) -> Result<()> {
262+
pub fn read(&mut self, buf: &mut [u8]) -> Result<(), Error> {
263263
for byte in buf.iter_mut() {
264264
*byte = self.read_byte()?;
265265
}
266266
Ok(())
267267
}
268268

269269
/// Read data from LPUART RX blocking execution until the buffer is filled.
270-
pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<()> {
270+
pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<(), Error> {
271271
for byte in buf.iter_mut() {
272272
*byte = self.blocking_read_byte()?;
273273
}

‎embassy-mcxa/src/lpuart/buffered.rs‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ impl<'a> Lpuart<'a, Buffered> {
2222
enable_rx: bool,
2323
enable_rts: bool,
2424
enable_cts: bool,
25-
) -> Result<Option<WakeGuard>> {
25+
) -> Result<Option<WakeGuard>, Error> {
2626
// Initialize buffers
2727
if let Some(tx_buffer) = tx_buffer {
2828
if tx_buffer.is_empty() {
@@ -78,7 +78,7 @@ impl<'a> Lpuart<'a, Buffered> {
7878
tx_buffer: &'a mut [u8],
7979
rx_buffer: &'a mut [u8],
8080
config: Config,
81-
) -> Result<Self> {
81+
) -> Result<Self, Error> {
8282
let wg = Self::init_buffered::<T>(
8383
Some(tx_buffer),
8484
Some(rx_buffer),
@@ -106,7 +106,7 @@ impl<'a> Lpuart<'a, Buffered> {
106106
tx_buffer: &'a mut [u8],
107107
rx_buffer: &'a mut [u8],
108108
config: Config,
109-
) -> Result<Self> {
109+
) -> Result<Self, Error> {
110110
tx_pin.as_tx();
111111
rx_pin.as_rx();
112112

@@ -126,7 +126,7 @@ impl<'a> Lpuart<'a, Buffered> {
126126
tx_buffer: &'a mut [u8],
127127
rx_buffer: &'a mut [u8],
128128
config: Config,
129-
) -> Result<Self> {
129+
) -> Result<Self, Error> {
130130
tx_pin.as_tx();
131131
rx_pin.as_rx();
132132
rts_pin.as_rts();
@@ -155,7 +155,7 @@ impl<'a> Lpuart<'a, Buffered> {
155155
tx_buffer: &'a mut [u8],
156156
rx_buffer: &'a mut [u8],
157157
config: Config,
158-
) -> Result<Self> {
158+
) -> Result<Self, Error> {
159159
tx_pin.as_tx();
160160
rx_pin.as_rx();
161161
rts_pin.as_rts();
@@ -183,7 +183,7 @@ impl<'a> Lpuart<'a, Buffered> {
183183
tx_buffer: &'a mut [u8],
184184
rx_buffer: &'a mut [u8],
185185
config: Config,
186-
) -> Result<Self> {
186+
) -> Result<Self, Error> {
187187
tx_pin.as_tx();
188188
rx_pin.as_rx();
189189
cts_pin.as_cts();
@@ -207,7 +207,7 @@ impl<'a> LpuartTx<'a, Buffered> {
207207
cts_pin: Option<Peri<'a, AnyPin>>,
208208
tx_buffer: &'a mut [u8],
209209
config: Config,
210-
) -> Result<Self> {
210+
) -> Result<Self, Error> {
211211
let wg = Lpuart::<'a, Buffered>::init_buffered::<T>(
212212
Some(tx_buffer),
213213
None,
@@ -230,7 +230,7 @@ impl<'a> LpuartTx<'a, Buffered> {
230230
_irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
231231
tx_buffer: &'a mut [u8],
232232
config: Config,
233-
) -> Result<Self> {
233+
) -> Result<Self, Error> {
234234
tx_pin.as_tx();
235235

236236
let res = Self::new_inner_buffered::<T>(tx_pin.into(), None, tx_buffer, config)?;
@@ -248,7 +248,7 @@ impl<'a> LpuartTx<'a, Buffered> {
248248
_irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
249249
tx_buffer: &'a mut [u8],
250250
config: Config,
251-
) -> Result<Self> {
251+
) -> Result<Self, Error> {
252252
tx_pin.as_tx();
253253
cts_pin.as_cts();
254254

@@ -264,7 +264,7 @@ impl<'a> LpuartTx<'a, Buffered> {
264264
}
265265

266266
/// Write data asynchronously
267-
pub async fn write(&mut self, buf: &[u8]) -> Result<usize> {
267+
pub async fn write(&mut self, buf: &[u8]) -> Result<usize, Error> {
268268
if buf.is_empty() {
269269
return Ok(0);
270270
}
@@ -276,7 +276,7 @@ impl<'a> LpuartTx<'a, Buffered> {
276276
}
277277

278278
/// Flush the TX buffer and wait for transmission to complete
279-
pub async fn flush(&mut self) -> Result<()> {
279+
pub async fn flush(&mut self) -> Result<(), Error> {
280280
// Wait for TX buffer to empty and transmission to complete
281281
Ok(self
282282
.state
@@ -345,7 +345,7 @@ impl<'a> LpuartRx<'a, Buffered> {
345345
rts_pin: Option<Peri<'a, AnyPin>>,
346346
rx_buffer: &'a mut [u8],
347347
config: Config,
348-
) -> Result<Self> {
348+
) -> Result<Self, Error> {
349349
let wg = Lpuart::<'a, Buffered>::init_buffered::<T>(
350350
None,
351351
Some(rx_buffer),
@@ -368,7 +368,7 @@ impl<'a> LpuartRx<'a, Buffered> {
368368
_irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
369369
rx_buffer: &'a mut [u8],
370370
config: Config,
371-
) -> Result<Self> {
371+
) -> Result<Self, Error> {
372372
rx_pin.as_rx();
373373

374374
let res = Self::new_inner_buffered::<T>(rx_pin.into(), None, rx_buffer, config)?;
@@ -392,7 +392,7 @@ impl<'a> LpuartRx<'a, Buffered> {
392392
_irq: impl interrupt::typelevel::Binding<T::Interrupt, BufferedInterruptHandler<T>> + 'a,
393393
rx_buffer: &'a mut [u8],
394394
config: Config,
395-
) -> Result<Self> {
395+
) -> Result<Self, Error> {
396396
rx_pin.as_rx();
397397
rts_pin.as_rts();
398398

@@ -408,7 +408,7 @@ impl<'a> LpuartRx<'a, Buffered> {
408408
}
409409

410410
/// Read data asynchronously
411-
pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize> {
411+
pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
412412
if buf.is_empty() {
413413
return Ok(0);
414414
}

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