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simd128: fix AltiVec version guards for POWER8-only intrinsics
Five functions in wasm/simd128.h use SIMDE_POWER_ALTIVEC_P7_NATIVE to guard code paths that emit 64-bit integer SIMD operations: - simde_wasm_i64x2_all_true(): vec_all_ne on int64 (vcmpequd_p) - simde_wasm_i32x4_extend_low_i16x8(): vec_sra on long long (vsrad) - simde_wasm_i32x4_extend_high_i16x8(): vec_sra on long long (vsrad) - simde_wasm_i64x2_extmul_low_i32x4(): vec_mule producing int64 - simde_wasm_i64x2_extmul_high_i32x4(): vec_mule producing int64 - simde_wasm_u64x2_extmul_low_u32x4(): vec_mule producing uint64 - simde_wasm_u64x2_extmul_high_u32x4(): vec_mule producing uint64 All of these require POWER8. The extmul functions additionally cause a GCC 14 internal compiler error (ICE at optabs.cc:326) when compiled with -mcpu=power7, because the compiler attempts to expand a widen-multiply pattern that has no POWER7 implementation. Change all guards from P7_NATIVE to P8_NATIVE. For the extmul_low signed/unsigned variants, also collapse the now-redundant inner P8/P7 branch (the outer guard already guarantees P8).
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Lines changed: 13 additions & 40 deletions

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‎simde/wasm/simd128.h‎

Lines changed: 13 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -4082,7 +4082,7 @@ simde_wasm_i64x2_all_true (simde_v128_t a) {
40824082
return _mm_test_all_zeros(_mm_cmpeq_epi64(a_.sse_m128i, _mm_setzero_si128()), _mm_set1_epi32(~INT32_C(0)));
40834083
#elif defined(SIMDE_X86_SSE2_NATIVE)
40844084
return _mm_movemask_pd(_mm_cmpeq_pd(a_.sse_m128d, _mm_setzero_pd())) == 0;
4085-
#elif defined(SIMDE_POWER_ALTIVEC_P7_NATIVE)
4085+
#elif defined(SIMDE_POWER_ALTIVEC_P8_NATIVE)
40864086
return HEDLEY_STATIC_CAST(simde_bool, vec_all_ne(a_.altivec_i64, HEDLEY_REINTERPRET_CAST(__typeof__(a_.altivec_i64), vec_splats(0))));
40874087
#else
40884088
int64_t r = !INT32_C(0);
@@ -6822,7 +6822,7 @@ simde_wasm_i64x2_extend_low_i32x4 (simde_v128_t a) {
68226822
r_.sse_m128i = _mm_cvtepi32_epi64(a_.sse_m128i);
68236823
#elif defined(SIMDE_X86_SSE2_NATIVE)
68246824
r_.sse_m128i = _mm_unpacklo_epi32(a_.sse_m128i, _mm_cmpgt_epi32(_mm_setzero_si128(), a_.sse_m128i));
6825-
#elif defined(SIMDE_POWER_ALTIVEC_P7_NATIVE)
6825+
#elif defined(SIMDE_POWER_ALTIVEC_P8_NATIVE)
68266826
r_.altivec_i64 =
68276827
vec_sra(HEDLEY_REINTERPRET_CAST(SIMDE_POWER_ALTIVEC_VECTOR(long long), vec_mergeh(a_.altivec_i32, a_.altivec_i32)),
68286828
vec_splats(HEDLEY_STATIC_CAST(unsigned long long, 32))
@@ -7096,7 +7096,7 @@ simde_wasm_i64x2_extend_high_i32x4 (simde_v128_t a) {
70967096
r_.sse_m128i = _mm_cvtepi32_epi64(_mm_shuffle_epi32(a_.sse_m128i, _MM_SHUFFLE(3, 2, 3, 2)));
70977097
#elif defined(SIMDE_X86_SSE2_NATIVE)
70987098
r_.sse_m128i = _mm_unpackhi_epi32(a_.sse_m128i, _mm_cmpgt_epi32(_mm_setzero_si128(), a_.sse_m128i));
7099-
#elif defined(SIMDE_POWER_ALTIVEC_P7_NATIVE)
7099+
#elif defined(SIMDE_POWER_ALTIVEC_P8_NATIVE)
71007100
r_.altivec_i64 =
71017101
vec_sra(HEDLEY_REINTERPRET_CAST(SIMDE_POWER_ALTIVEC_VECTOR(long long), vec_mergel(a_.altivec_i32, a_.altivec_i32)),
71027102
vec_splats(HEDLEY_STATIC_CAST(unsigned long long, 32))
@@ -7377,21 +7377,12 @@ simde_wasm_i64x2_extmul_low_i32x4 (simde_v128_t a, simde_v128_t b) {
73777377

73787378
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
73797379
r_.neon_i64 = vmull_s32(vget_low_s32(a_.neon_i32), vget_low_s32(b_.neon_i32));
7380-
#elif defined(SIMDE_POWER_ALTIVEC_P7_NATIVE)
7380+
#elif defined(SIMDE_POWER_ALTIVEC_P8_NATIVE)
73817381
SIMDE_POWER_ALTIVEC_VECTOR(signed int) ashuf;
73827382
SIMDE_POWER_ALTIVEC_VECTOR(signed int) bshuf;
73837383

7384-
#if defined(SIMDE_POWER_ALTIVEC_P8_NATIVE)
7385-
ashuf = vec_mergeh(a_.altivec_i32, a_.altivec_i32);
7386-
bshuf = vec_mergeh(b_.altivec_i32, b_.altivec_i32);
7387-
#else
7388-
SIMDE_POWER_ALTIVEC_VECTOR(unsigned char) perm = {
7389-
0, 1, 2, 3, 0, 1, 2, 3,
7390-
4, 5, 6, 7, 4, 5, 6, 7
7391-
};
7392-
ashuf = vec_perm(a_.altivec_i32, a_.altivec_i32, perm);
7393-
bshuf = vec_perm(b_.altivec_i32, b_.altivec_i32, perm);
7394-
#endif
7384+
ashuf = vec_mergeh(a_.altivec_i32, a_.altivec_i32);
7385+
bshuf = vec_mergeh(b_.altivec_i32, b_.altivec_i32);
73957386

73967387
r_.altivec_i64 = vec_mule(ashuf, bshuf);
73977388
#elif defined(SIMDE_X86_SSE4_1_NATIVE)
@@ -7555,21 +7546,12 @@ simde_wasm_u64x2_extmul_low_u32x4 (simde_v128_t a, simde_v128_t b) {
75557546

75567547
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
75577548
r_.neon_u64 = vmull_u32(vget_low_u32(a_.neon_u32), vget_low_u32(b_.neon_u32));
7558-
#elif defined(SIMDE_POWER_ALTIVEC_P7_NATIVE)
7549+
#elif defined(SIMDE_POWER_ALTIVEC_P8_NATIVE)
75597550
SIMDE_POWER_ALTIVEC_VECTOR(unsigned int) ashuf;
75607551
SIMDE_POWER_ALTIVEC_VECTOR(unsigned int) bshuf;
75617552

7562-
#if defined(SIMDE_POWER_ALTIVEC_P8_NATIVE)
7563-
ashuf = vec_mergeh(a_.altivec_u32, a_.altivec_u32);
7564-
bshuf = vec_mergeh(b_.altivec_u32, b_.altivec_u32);
7565-
#else
7566-
SIMDE_POWER_ALTIVEC_VECTOR(unsigned char) perm = {
7567-
0, 1, 2, 3, 0, 1, 2, 3,
7568-
4, 5, 6, 7, 4, 5, 6, 7
7569-
};
7570-
ashuf = vec_perm(a_.altivec_u32, a_.altivec_u32, perm);
7571-
bshuf = vec_perm(b_.altivec_u32, b_.altivec_u32, perm);
7572-
#endif
7553+
ashuf = vec_mergeh(a_.altivec_u32, a_.altivec_u32);
7554+
bshuf = vec_mergeh(b_.altivec_u32, b_.altivec_u32);
75737555

75747556
r_.altivec_u64 = vec_mule(ashuf, bshuf);
75757557
#elif defined(SIMDE_X86_SSE2_NATIVE)
@@ -7724,21 +7706,12 @@ simde_wasm_i64x2_extmul_high_i32x4 (simde_v128_t a, simde_v128_t b) {
77247706
r_.neon_i64 = vmull_high_s32(a_.neon_i32, b_.neon_i32);
77257707
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
77267708
r_.neon_i64 = vmull_s32(vget_high_s32(a_.neon_i32), vget_high_s32(b_.neon_i32));
7727-
#elif defined(SIMDE_POWER_ALTIVEC_P7_NATIVE)
7709+
#elif defined(SIMDE_POWER_ALTIVEC_P8_NATIVE)
77287710
SIMDE_POWER_ALTIVEC_VECTOR(signed int) ashuf;
77297711
SIMDE_POWER_ALTIVEC_VECTOR(signed int) bshuf;
77307712

7731-
#if defined(SIMDE_POWER_ALTIVEC_P8_NATIVE)
7732-
ashuf = vec_mergel(a_.altivec_i32, a_.altivec_i32);
7733-
bshuf = vec_mergel(b_.altivec_i32, b_.altivec_i32);
7734-
#else
7735-
SIMDE_POWER_ALTIVEC_VECTOR(unsigned char) perm = {
7736-
8, 9, 10, 11, 8, 9, 10, 11,
7737-
12, 13, 14, 15, 12, 13, 14, 15
7738-
};
7739-
ashuf = vec_perm(a_.altivec_i32, a_.altivec_i32, perm);
7740-
bshuf = vec_perm(b_.altivec_i32, b_.altivec_i32, perm);
7741-
#endif
7713+
ashuf = vec_mergel(a_.altivec_i32, a_.altivec_i32);
7714+
bshuf = vec_mergel(b_.altivec_i32, b_.altivec_i32);
77427715

77437716
r_.altivec_i64 = vec_mule(ashuf, bshuf);
77447717
#elif defined(SIMDE_X86_SSE4_1_NATIVE)
@@ -7885,7 +7858,7 @@ simde_wasm_u64x2_extmul_high_u32x4 (simde_v128_t a, simde_v128_t b) {
78857858
r_.neon_u64 = vmull_high_u32(a_.neon_u32, b_.neon_u32);
78867859
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
78877860
r_.neon_u64 = vmull_u32(vget_high_u32(a_.neon_u32), vget_high_u32(b_.neon_u32));
7888-
#elif defined(SIMDE_POWER_ALTIVEC_P7_NATIVE)
7861+
#elif defined(SIMDE_POWER_ALTIVEC_P8_NATIVE)
78897862
r_.altivec_u64 =
78907863
vec_mule(
78917864
vec_mergel(a_.altivec_u32, a_.altivec_u32),

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