@@ -20,18 +20,32 @@ short add_with_assembly(short a, short b) {
2020 short result ;
2121
2222 #if __aarch64__ // ARM 64-bit
23- asm volatile ("add %w[a], %w[a], %w[b]; mov %w[a], %w[result]"
23+ // add the two source W (32-bit) registers, writing the sum to the result register
24+ asm ("add %w[result], %w[a], %w[b]"
2425 : [result ] "=r" (result )
25- : [a ] "r" (a ), [b ] "r" (b )
26- : "cc" );
26+ : [a ] "r" (a ), [b ] "r" (b ));
2727 #elif __i386__ // Intel 32-bit
28- result = a + b ;
28+ // tie `a` into the result register, then add `b` into it (AT&T order: addw src, dst)
29+ asm ("addw %[b], %[result]"
30+ : [result ] "=r" (result )
31+ : [b ] "r" (b ), "0" (a )
32+ : "cc" );
2933 #elif __x86_64__ // Intel 64-bit
30- result = a + b ;
34+ // tie `a` into the result register, then add `b` into it (AT&T order: addw src, dst)
35+ asm ("addw %[b], %[result]"
36+ : [result ] "=r" (result )
37+ : [b ] "r" (b ), "0" (a )
38+ : "cc" );
3139 #elif __arm__ // ARM 32-bit
32- result = a + b ;
33- #elif __riscv_64 // RISC-V 64-bit (future)
34- result = a + b ;
40+ // add Rn (a) and Rm (b), writing the sum to Rd (result)
41+ asm ("add %[result], %[a], %[b]"
42+ : [result ] "=r" (result )
43+ : [a ] "r" (a ), [b ] "r" (b ));
44+ #elif defined(__riscv ) && (__riscv_xlen == 64 ) // RISC-V 64-bit (future)
45+ // add rs1 (a) and rs2 (b), writing the sum to rd (result)
46+ asm ("add %[result], %[a], %[b]"
47+ : [result ] "=r" (result )
48+ : [a ] "r" (a ), [b ] "r" (b ));
3549 #else
3650 #error "Unsupported architecture"
3751 #endif
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