Basketball/FSM_COM.vhd at main · skwcrd/Basketball · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity FSM_COM is
Port(
	CLK,Rstb : in std_logic;
	i1s : in std_logic;
	I : in std_logic;
	iCOM : in std_logic_vector(3 downto 0);
	com : out std_logic_vector(3 downto 0)
);
End FSM_COM;

Architecture Behavioral of FSM_COM is
	type State_Type is (S1,S2);
	signal curr_state,next_state : State_Type;
	signal rCnt : std_logic := '0';
	signal wCom : std_logic_vector(3 downto 0);
Begin

	---------- REGISTOR STATE ----------
	u_rState : Process(CLK,Rstb)
	Begin
		if(Rstb='0') then
			curr_state <= S1;
		elsif(rising_edge(CLK)) then
			curr_state <= next_state;
		else
			curr_state <= curr_state;
		end if;
	End Process;

	---------- CHANGE STATE ----------
	u_State : Process(curr_state,I)
	Begin
		case curr_state is
			when S1 => 	if(I='1') then
								next_state <= S2;
							else
								next_state <= S1;
							end if;

			when S2 => 	if(I='1') then
								next_state <= S1;
							else
								next_state <= S2;
							end if;

			when others => next_state <= S1;
		end case;
	End Process;

	---------- OUTPUT STATE DIGIT ----------
	com <= wCom;

	u_oState : Process(CLK,Rstb)
	Begin
		if(Rstb='0') then
			rCnt <= '0';
			wCom <= (others => '0');
		elsif(rising_edge(CLK)) then
			case curr_state is
				when S1 =>	if(rCnt='0') then
									wCom <= iCOM(3 downto 2) & "11";
									if(i1s='1') then
										rCnt <= '1';
									else
										rCnt <= '0';
									end if;
								elsif(rCnt='1') then
									wCom <= iCOM;
									if(i1s='1') then
										rCnt <= '0';
									else
										rCnt <= '1';
									end if;
								else
									rCnt <= rCnt;
									wCom <= wCom;
								end if;

				when S2 =>	if(rCnt='0') then
									wCom <= "11" & iCOM(1 downto 0);
									if(i1s='1') then
										rCnt <= '1';
									else
										rCnt <= '0';
									end if;
								elsif(rCnt='1') then
									wCom <= iCOM;
									if(i1s='1') then
										rCnt <= '0';
									else
										rCnt <= '1';
									end if;
								else
									rCnt <= rCnt;
									wCom <= wCom;
								end if;
			end case;
		end if;
	End Process;

End Behavioral;