config.yaml

# This can be set to a floating-point number for repeatable results, or "random"
# for a new randomized run. I could have different random configuration for the different random
# functions, but it's good enough to just have a global setting.
random_seed_value: 0.0
itf:
  file: freepdk3_rctyp.itf
  units: um
units:
  distance: um
  capacitance: ff
  resistance: ohms
  time: ps
# This is the distance from the bottom of the lowest layer of metal to the bulk silicon and nwells.
feol_thickness: 0.200
standard_cells:
  - name: BUFX12
    # 7 track
    height: 0.315
    # 15*CPPs
    width: 0.675
    pins:
      - name: A
        type: signal
        direction: input
        location: left
      - name: Y
        type: signal
        direction: output
        location: right
      - name: VDD
        type: power
        location: top
      - name: VSS
        type: ground
        location: bottom
    spice_netlist_file: BUFX12.spi
    unateness: positive
  - name: DCAPX32
    height: 0.315
    width: 1.755
    pins:
      - name: VDD
        type: power
        location: top
      - name: VSS
        type: ground
        location: bottom
    spice_netlist_file: DCAPX32.spi
# Pad location points
ploc:
  pitch: 10
  staggered: true
  offset_from_origin:
    x: 5
    y: 5
  visualizer_render_diameter: 1
visualizer:
  initial_visible_objects: ["Dcap Cells", Cells, M0, V0, M1]
spice_netlist:
  scaling:
    resistance: 1.0
    capacitance: 1.0
  cell_chains:
    cell: BUFX12
    interconnect:
      resistance: 200
      capacitance: 100
      number_pi_segments: 2
    end_of_chain_load:
      resistance: 200
      capacitance: 500
    chain_input_stimulus:
      period: 500
      # From 0% to 100%
      transition_time:
        nominal: 100
        sigma: 5
        floor: 20
        ceiling: 200
      initial_delay:
        nominal: 100
        sigma: 10
        floor: 0
        ceiling: 1000
    max_instance_count_per_chain: 5
  ir_drop_measurement:
    averaging_window:
      # % of input transition
      start: 10
      # % of output transition
      end: 75
  user_defined_lines:
    - ".include \"spice_models.sp\""
    - ".tran 5p 2000p"
standard_cell_placement:
  # 7 tracks
  row_height: 0.315
  # 1 CPP
  site_width: 0.045
  min_space:
    x: 4.0
    y: 0.0
  # Set the range to 0.0 to disable staggered start points
  # If random=false, then alternate between 0.0 offset and the value of range offset
  stagger_row_start:
    range: 5.0
    random: true
  dcap_cells:
    enabled: true
    cell: DCAPX32
    max_density_pct: 50
pg_nets:
  power:
    name: "VDD"
    voltage: 0.825
  ground:
    name: "VSS"
grid:
  # If the ITF file does not specify min spacing for VIAs. Set the min-space to
  # be the length of a via edge * via_min_space_factor
  via_min_space_factor: 1.5
  size:
    rows: 50
    sites: 500
  # The width and pitch are in terms of WMIN, and SMIN.
  # For example, if width=1.0, then the actual width in distance units is 1.0 * WMIN.
  # For example, if pitch=1.0, then the actual pitch in distance units is 1.0 * WMIN+SMIN.
  # The lowest layer in the ITF file is implicitly:
  #   horizontal, type=grid, width=2.0, pitch=standard_cells.height
  # Layers alternate between horizontal and vertical moving up from the lowest layer.
  layer_usage:
    RDL: {type: grid, width: 1.0, pitch: 1.0}
    M13: {type: grid, width: 1.0, pitch: 1.0}
    M12: {type: staple, width: 1.0, pitch: 1.0}
    M11: {type: staple, width: 1.0, pitch: 1.0}
    M10: {type: staple, width: 1.0, pitch: 1.0}
    M9: {type: staple, width: 1.0, pitch: 1.0}
    M8: {type: grid, width: 1.0, pitch: 5.0}
    M7: {type: grid, width: 1.0, pitch: 5.0}
    M6: {type: staple, width: 1.0, pitch: 1.0}
    M5: {type: staple, width: 1.0, pitch: 1.0}
    M4: {type: staple, width: 1.0, pitch: 1.0}
    M3: {type: staple, width: 1.0, pitch: 1.0}
    M2: {type: grid, width: 1.0, pitch: 5.0}
    M1: {type: grid, width: 1.0, pitch: 5.0}