disasem.txt


C:\Users\Colton\Documents\OS3M-Mouse\Firmware\OS3M_Mouse\build\OS3M_Mouse.elf:     file format elf32-littlearm


Disassembly of section .text:

080000c0 <__udivsi3>:
 80000c0:	2200      	movs	r2, #0
 80000c2:	0843      	lsrs	r3, r0, #1
 80000c4:	428b      	cmp	r3, r1
 80000c6:	d374      	bcc.n	80001b2 <__udivsi3+0xf2>
 80000c8:	0903      	lsrs	r3, r0, #4
 80000ca:	428b      	cmp	r3, r1
 80000cc:	d35f      	bcc.n	800018e <__udivsi3+0xce>
 80000ce:	0a03      	lsrs	r3, r0, #8
 80000d0:	428b      	cmp	r3, r1
 80000d2:	d344      	bcc.n	800015e <__udivsi3+0x9e>
 80000d4:	0b03      	lsrs	r3, r0, #12
 80000d6:	428b      	cmp	r3, r1
 80000d8:	d328      	bcc.n	800012c <__udivsi3+0x6c>
 80000da:	0c03      	lsrs	r3, r0, #16
 80000dc:	428b      	cmp	r3, r1
 80000de:	d30d      	bcc.n	80000fc <__udivsi3+0x3c>
 80000e0:	22ff      	movs	r2, #255	; 0xff
 80000e2:	0209      	lsls	r1, r1, #8
 80000e4:	ba12      	rev	r2, r2
 80000e6:	0c03      	lsrs	r3, r0, #16
 80000e8:	428b      	cmp	r3, r1
 80000ea:	d302      	bcc.n	80000f2 <__udivsi3+0x32>
 80000ec:	1212      	asrs	r2, r2, #8
 80000ee:	0209      	lsls	r1, r1, #8
 80000f0:	d065      	beq.n	80001be <__udivsi3+0xfe>
 80000f2:	0b03      	lsrs	r3, r0, #12
 80000f4:	428b      	cmp	r3, r1
 80000f6:	d319      	bcc.n	800012c <__udivsi3+0x6c>
 80000f8:	e000      	b.n	80000fc <__udivsi3+0x3c>
 80000fa:	0a09      	lsrs	r1, r1, #8
 80000fc:	0bc3      	lsrs	r3, r0, #15
 80000fe:	428b      	cmp	r3, r1
 8000100:	d301      	bcc.n	8000106 <__udivsi3+0x46>
 8000102:	03cb      	lsls	r3, r1, #15
 8000104:	1ac0      	subs	r0, r0, r3
 8000106:	4152      	adcs	r2, r2
 8000108:	0b83      	lsrs	r3, r0, #14
 800010a:	428b      	cmp	r3, r1
 800010c:	d301      	bcc.n	8000112 <__udivsi3+0x52>
 800010e:	038b      	lsls	r3, r1, #14
 8000110:	1ac0      	subs	r0, r0, r3
 8000112:	4152      	adcs	r2, r2
 8000114:	0b43      	lsrs	r3, r0, #13
 8000116:	428b      	cmp	r3, r1
 8000118:	d301      	bcc.n	800011e <__udivsi3+0x5e>
 800011a:	034b      	lsls	r3, r1, #13
 800011c:	1ac0      	subs	r0, r0, r3
 800011e:	4152      	adcs	r2, r2
 8000120:	0b03      	lsrs	r3, r0, #12
 8000122:	428b      	cmp	r3, r1
 8000124:	d301      	bcc.n	800012a <__udivsi3+0x6a>
 8000126:	030b      	lsls	r3, r1, #12
 8000128:	1ac0      	subs	r0, r0, r3
 800012a:	4152      	adcs	r2, r2
 800012c:	0ac3      	lsrs	r3, r0, #11
 800012e:	428b      	cmp	r3, r1
 8000130:	d301      	bcc.n	8000136 <__udivsi3+0x76>
 8000132:	02cb      	lsls	r3, r1, #11
 8000134:	1ac0      	subs	r0, r0, r3
 8000136:	4152      	adcs	r2, r2
 8000138:	0a83      	lsrs	r3, r0, #10
 800013a:	428b      	cmp	r3, r1
 800013c:	d301      	bcc.n	8000142 <__udivsi3+0x82>
 800013e:	028b      	lsls	r3, r1, #10
 8000140:	1ac0      	subs	r0, r0, r3
 8000142:	4152      	adcs	r2, r2
 8000144:	0a43      	lsrs	r3, r0, #9
 8000146:	428b      	cmp	r3, r1
 8000148:	d301      	bcc.n	800014e <__udivsi3+0x8e>
 800014a:	024b      	lsls	r3, r1, #9
 800014c:	1ac0      	subs	r0, r0, r3
 800014e:	4152      	adcs	r2, r2
 8000150:	0a03      	lsrs	r3, r0, #8
 8000152:	428b      	cmp	r3, r1
 8000154:	d301      	bcc.n	800015a <__udivsi3+0x9a>
 8000156:	020b      	lsls	r3, r1, #8
 8000158:	1ac0      	subs	r0, r0, r3
 800015a:	4152      	adcs	r2, r2
 800015c:	d2cd      	bcs.n	80000fa <__udivsi3+0x3a>
 800015e:	09c3      	lsrs	r3, r0, #7
 8000160:	428b      	cmp	r3, r1
 8000162:	d301      	bcc.n	8000168 <__udivsi3+0xa8>
 8000164:	01cb      	lsls	r3, r1, #7
 8000166:	1ac0      	subs	r0, r0, r3
 8000168:	4152      	adcs	r2, r2
 800016a:	0983      	lsrs	r3, r0, #6
 800016c:	428b      	cmp	r3, r1
 800016e:	d301      	bcc.n	8000174 <__udivsi3+0xb4>
 8000170:	018b      	lsls	r3, r1, #6
 8000172:	1ac0      	subs	r0, r0, r3
 8000174:	4152      	adcs	r2, r2
 8000176:	0943      	lsrs	r3, r0, #5
 8000178:	428b      	cmp	r3, r1
 800017a:	d301      	bcc.n	8000180 <__udivsi3+0xc0>
 800017c:	014b      	lsls	r3, r1, #5
 800017e:	1ac0      	subs	r0, r0, r3
 8000180:	4152      	adcs	r2, r2
 8000182:	0903      	lsrs	r3, r0, #4
 8000184:	428b      	cmp	r3, r1
 8000186:	d301      	bcc.n	800018c <__udivsi3+0xcc>
 8000188:	010b      	lsls	r3, r1, #4
 800018a:	1ac0      	subs	r0, r0, r3
 800018c:	4152      	adcs	r2, r2
 800018e:	08c3      	lsrs	r3, r0, #3
 8000190:	428b      	cmp	r3, r1
 8000192:	d301      	bcc.n	8000198 <__udivsi3+0xd8>
 8000194:	00cb      	lsls	r3, r1, #3
 8000196:	1ac0      	subs	r0, r0, r3
 8000198:	4152      	adcs	r2, r2
 800019a:	0883      	lsrs	r3, r0, #2
 800019c:	428b      	cmp	r3, r1
 800019e:	d301      	bcc.n	80001a4 <__udivsi3+0xe4>
 80001a0:	008b      	lsls	r3, r1, #2
 80001a2:	1ac0      	subs	r0, r0, r3
 80001a4:	4152      	adcs	r2, r2
 80001a6:	0843      	lsrs	r3, r0, #1
 80001a8:	428b      	cmp	r3, r1
 80001aa:	d301      	bcc.n	80001b0 <__udivsi3+0xf0>
 80001ac:	004b      	lsls	r3, r1, #1
 80001ae:	1ac0      	subs	r0, r0, r3
 80001b0:	4152      	adcs	r2, r2
 80001b2:	1a41      	subs	r1, r0, r1
 80001b4:	d200      	bcs.n	80001b8 <__udivsi3+0xf8>
 80001b6:	4601      	mov	r1, r0
 80001b8:	4152      	adcs	r2, r2
 80001ba:	4610      	mov	r0, r2
 80001bc:	4770      	bx	lr
 80001be:	e7ff      	b.n	80001c0 <__udivsi3+0x100>
 80001c0:	b501      	push	{r0, lr}
 80001c2:	2000      	movs	r0, #0
 80001c4:	f000 f806 	bl	80001d4 <__aeabi_idiv0>
 80001c8:	bd02      	pop	{r1, pc}
 80001ca:	46c0      	nop			; (mov r8, r8)

080001cc <__aeabi_uidivmod>:
 80001cc:	2900      	cmp	r1, #0
 80001ce:	d0f7      	beq.n	80001c0 <__udivsi3+0x100>
 80001d0:	e776      	b.n	80000c0 <__udivsi3>
 80001d2:	4770      	bx	lr

080001d4 <__aeabi_idiv0>:
 80001d4:	4770      	bx	lr
 80001d6:	46c0      	nop			; (mov r8, r8)

080001d8 <__do_global_dtors_aux>:
 80001d8:	b510      	push	{r4, lr}
 80001da:	4c06      	ldr	r4, [pc, #24]	; (80001f4 <__do_global_dtors_aux+0x1c>)
 80001dc:	7823      	ldrb	r3, [r4, #0]
 80001de:	2b00      	cmp	r3, #0
 80001e0:	d107      	bne.n	80001f2 <__do_global_dtors_aux+0x1a>
 80001e2:	4b05      	ldr	r3, [pc, #20]	; (80001f8 <__do_global_dtors_aux+0x20>)
 80001e4:	2b00      	cmp	r3, #0
 80001e6:	d002      	beq.n	80001ee <__do_global_dtors_aux+0x16>
 80001e8:	4804      	ldr	r0, [pc, #16]	; (80001fc <__do_global_dtors_aux+0x24>)
 80001ea:	e000      	b.n	80001ee <__do_global_dtors_aux+0x16>
 80001ec:	bf00      	nop
 80001ee:	2301      	movs	r3, #1
 80001f0:	7023      	strb	r3, [r4, #0]
 80001f2:	bd10      	pop	{r4, pc}
 80001f4:	2000000c 	.word	0x2000000c
 80001f8:	00000000 	.word	0x00000000
 80001fc:	0800167c 	.word	0x0800167c

08000200 <frame_dummy>:
 8000200:	4b04      	ldr	r3, [pc, #16]	; (8000214 <frame_dummy+0x14>)
 8000202:	b510      	push	{r4, lr}
 8000204:	2b00      	cmp	r3, #0
 8000206:	d003      	beq.n	8000210 <frame_dummy+0x10>
 8000208:	4903      	ldr	r1, [pc, #12]	; (8000218 <frame_dummy+0x18>)
 800020a:	4804      	ldr	r0, [pc, #16]	; (800021c <frame_dummy+0x1c>)
 800020c:	e000      	b.n	8000210 <frame_dummy+0x10>
 800020e:	bf00      	nop
 8000210:	bd10      	pop	{r4, pc}
 8000212:	46c0      	nop			; (mov r8, r8)
 8000214:	00000000 	.word	0x00000000
 8000218:	20000010 	.word	0x20000010
 800021c:	0800167c 	.word	0x0800167c

08000220 <MX_GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
 8000220:	b082      	sub	sp, #8
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOF_CLK_ENABLE();
 8000222:	4b0a      	ldr	r3, [pc, #40]	; (800024c <MX_GPIO_Init+0x2c>)
 8000224:	695a      	ldr	r2, [r3, #20]
 8000226:	2180      	movs	r1, #128	; 0x80
 8000228:	03c9      	lsls	r1, r1, #15
 800022a:	430a      	orrs	r2, r1
 800022c:	615a      	str	r2, [r3, #20]
 800022e:	695a      	ldr	r2, [r3, #20]
 8000230:	400a      	ands	r2, r1
 8000232:	9200      	str	r2, [sp, #0]
 8000234:	9a00      	ldr	r2, [sp, #0]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8000236:	695a      	ldr	r2, [r3, #20]
 8000238:	2180      	movs	r1, #128	; 0x80
 800023a:	0289      	lsls	r1, r1, #10
 800023c:	430a      	orrs	r2, r1
 800023e:	615a      	str	r2, [r3, #20]
 8000240:	695b      	ldr	r3, [r3, #20]
 8000242:	400b      	ands	r3, r1
 8000244:	9301      	str	r3, [sp, #4]
 8000246:	9b01      	ldr	r3, [sp, #4]

/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
 8000248:	b002      	add	sp, #8
 800024a:	4770      	bx	lr
 800024c:	40021000 	.word	0x40021000

08000250 <Error_Handler>:
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
 8000250:	b672      	cpsid	i
void Error_Handler(void)
{
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
 8000252:	e7fe      	b.n	8000252 <Error_Handler+0x2>

08000254 <MX_I2C1_Init>:
{
 8000254:	b510      	push	{r4, lr}
  hi2c1.Instance = I2C1;
 8000256:	4812      	ldr	r0, [pc, #72]	; (80002a0 <MX_I2C1_Init+0x4c>)
 8000258:	4b12      	ldr	r3, [pc, #72]	; (80002a4 <MX_I2C1_Init+0x50>)
 800025a:	6003      	str	r3, [r0, #0]
  hi2c1.Init.Timing = 0x20303E5D;
 800025c:	4b12      	ldr	r3, [pc, #72]	; (80002a8 <MX_I2C1_Init+0x54>)
 800025e:	6043      	str	r3, [r0, #4]
  hi2c1.Init.OwnAddress1 = 0;
 8000260:	2300      	movs	r3, #0
 8000262:	6083      	str	r3, [r0, #8]
  hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
 8000264:	2201      	movs	r2, #1
 8000266:	60c2      	str	r2, [r0, #12]
  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
 8000268:	6103      	str	r3, [r0, #16]
  hi2c1.Init.OwnAddress2 = 0;
 800026a:	6143      	str	r3, [r0, #20]
  hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
 800026c:	6183      	str	r3, [r0, #24]
  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
 800026e:	61c3      	str	r3, [r0, #28]
  hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
 8000270:	6203      	str	r3, [r0, #32]
  if (HAL_I2C_Init(&hi2c1) != HAL_OK)
 8000272:	f000 fa5f 	bl	8000734 <HAL_I2C_Init>
 8000276:	2800      	cmp	r0, #0
 8000278:	d10c      	bne.n	8000294 <MX_I2C1_Init+0x40>
  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
 800027a:	4809      	ldr	r0, [pc, #36]	; (80002a0 <MX_I2C1_Init+0x4c>)
 800027c:	2100      	movs	r1, #0
 800027e:	f000 fabf 	bl	8000800 <HAL_I2CEx_ConfigAnalogFilter>
 8000282:	2800      	cmp	r0, #0
 8000284:	d108      	bne.n	8000298 <MX_I2C1_Init+0x44>
  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
 8000286:	4806      	ldr	r0, [pc, #24]	; (80002a0 <MX_I2C1_Init+0x4c>)
 8000288:	2100      	movs	r1, #0
 800028a:	f000 fae5 	bl	8000858 <HAL_I2CEx_ConfigDigitalFilter>
 800028e:	2800      	cmp	r0, #0
 8000290:	d104      	bne.n	800029c <MX_I2C1_Init+0x48>
}
 8000292:	bd10      	pop	{r4, pc}
    Error_Handler();
 8000294:	f7ff ffdc 	bl	8000250 <Error_Handler>
    Error_Handler();
 8000298:	f7ff ffda 	bl	8000250 <Error_Handler>
    Error_Handler();
 800029c:	f7ff ffd8 	bl	8000250 <Error_Handler>
 80002a0:	200000b0 	.word	0x200000b0
 80002a4:	40005400 	.word	0x40005400
 80002a8:	20303e5d 	.word	0x20303e5d

080002ac <MX_USART2_UART_Init>:
{
 80002ac:	b510      	push	{r4, lr}
  huart2.Instance = USART2;
 80002ae:	480b      	ldr	r0, [pc, #44]	; (80002dc <MX_USART2_UART_Init+0x30>)
 80002b0:	4b0b      	ldr	r3, [pc, #44]	; (80002e0 <MX_USART2_UART_Init+0x34>)
 80002b2:	6003      	str	r3, [r0, #0]
  huart2.Init.BaudRate = 115200;
 80002b4:	23e1      	movs	r3, #225	; 0xe1
 80002b6:	025b      	lsls	r3, r3, #9
 80002b8:	6043      	str	r3, [r0, #4]
  huart2.Init.WordLength = UART_WORDLENGTH_8B;
 80002ba:	2300      	movs	r3, #0
 80002bc:	6083      	str	r3, [r0, #8]
  huart2.Init.StopBits = UART_STOPBITS_1;
 80002be:	60c3      	str	r3, [r0, #12]
  huart2.Init.Parity = UART_PARITY_NONE;
 80002c0:	6103      	str	r3, [r0, #16]
  huart2.Init.Mode = UART_MODE_TX_RX;
 80002c2:	220c      	movs	r2, #12
 80002c4:	6142      	str	r2, [r0, #20]
  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 80002c6:	6183      	str	r3, [r0, #24]
  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
 80002c8:	61c3      	str	r3, [r0, #28]
  huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
 80002ca:	6203      	str	r3, [r0, #32]
  huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
 80002cc:	6243      	str	r3, [r0, #36]	; 0x24
  if (HAL_UART_Init(&huart2) != HAL_OK)
 80002ce:	f001 f931 	bl	8001534 <HAL_UART_Init>
 80002d2:	2800      	cmp	r0, #0
 80002d4:	d100      	bne.n	80002d8 <MX_USART2_UART_Init+0x2c>
}
 80002d6:	bd10      	pop	{r4, pc}
    Error_Handler();
 80002d8:	f7ff ffba 	bl	8000250 <Error_Handler>
 80002dc:	20000028 	.word	0x20000028
 80002e0:	40004400 	.word	0x40004400

080002e4 <SystemClock_Config>:
{
 80002e4:	b500      	push	{lr}
 80002e6:	b099      	sub	sp, #100	; 0x64
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 80002e8:	2234      	movs	r2, #52	; 0x34
 80002ea:	2100      	movs	r1, #0
 80002ec:	a80b      	add	r0, sp, #44	; 0x2c
 80002ee:	f001 f998 	bl	8001622 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 80002f2:	2210      	movs	r2, #16
 80002f4:	2100      	movs	r1, #0
 80002f6:	a807      	add	r0, sp, #28
 80002f8:	f001 f993 	bl	8001622 <memset>
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 80002fc:	2218      	movs	r2, #24
 80002fe:	2100      	movs	r1, #0
 8000300:	a801      	add	r0, sp, #4
 8000302:	f001 f98e 	bl	8001622 <memset>
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
 8000306:	2320      	movs	r3, #32
 8000308:	930b      	str	r3, [sp, #44]	; 0x2c
  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
 800030a:	3b1f      	subs	r3, #31
 800030c:	9313      	str	r3, [sp, #76]	; 0x4c
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 800030e:	a80b      	add	r0, sp, #44	; 0x2c
 8000310:	f000 facc 	bl	80008ac <HAL_RCC_OscConfig>
 8000314:	2800      	cmp	r0, #0
 8000316:	d117      	bne.n	8000348 <SystemClock_Config+0x64>
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8000318:	2307      	movs	r3, #7
 800031a:	9307      	str	r3, [sp, #28]
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI48;
 800031c:	3b04      	subs	r3, #4
 800031e:	9308      	str	r3, [sp, #32]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8000320:	2300      	movs	r3, #0
 8000322:	9309      	str	r3, [sp, #36]	; 0x24
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 8000324:	930a      	str	r3, [sp, #40]	; 0x28
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
 8000326:	2101      	movs	r1, #1
 8000328:	a807      	add	r0, sp, #28
 800032a:	f000 fd9d 	bl	8000e68 <HAL_RCC_ClockConfig>
 800032e:	2800      	cmp	r0, #0
 8000330:	d10c      	bne.n	800034c <SystemClock_Config+0x68>
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
 8000332:	2320      	movs	r3, #32
 8000334:	9301      	str	r3, [sp, #4]
  PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_SYSCLK;
 8000336:	3b10      	subs	r3, #16
 8000338:	9304      	str	r3, [sp, #16]
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 800033a:	a801      	add	r0, sp, #4
 800033c:	f000 fe4c 	bl	8000fd8 <HAL_RCCEx_PeriphCLKConfig>
 8000340:	2800      	cmp	r0, #0
 8000342:	d105      	bne.n	8000350 <SystemClock_Config+0x6c>
}
 8000344:	b019      	add	sp, #100	; 0x64
 8000346:	bd00      	pop	{pc}
    Error_Handler();
 8000348:	f7ff ff82 	bl	8000250 <Error_Handler>
    Error_Handler();
 800034c:	f7ff ff80 	bl	8000250 <Error_Handler>
    Error_Handler();
 8000350:	f7ff ff7e 	bl	8000250 <Error_Handler>

08000354 <main>:
{
 8000354:	b510      	push	{r4, lr}
  HAL_Init();
 8000356:	f000 f8b9 	bl	80004cc <HAL_Init>
  SystemClock_Config();
 800035a:	f7ff ffc3 	bl	80002e4 <SystemClock_Config>
  MX_GPIO_Init();
 800035e:	f7ff ff5f 	bl	8000220 <MX_GPIO_Init>
  MX_I2C1_Init();
 8000362:	f7ff ff77 	bl	8000254 <MX_I2C1_Init>
  MX_USART2_UART_Init();
 8000366:	f7ff ffa1 	bl	80002ac <MX_USART2_UART_Init>
  while (1)
 800036a:	e7fe      	b.n	800036a <main+0x16>

0800036c <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 800036c:	b082      	sub	sp, #8
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 800036e:	4b0a      	ldr	r3, [pc, #40]	; (8000398 <HAL_MspInit+0x2c>)
 8000370:	6999      	ldr	r1, [r3, #24]
 8000372:	2201      	movs	r2, #1
 8000374:	4311      	orrs	r1, r2
 8000376:	6199      	str	r1, [r3, #24]
 8000378:	6999      	ldr	r1, [r3, #24]
 800037a:	400a      	ands	r2, r1
 800037c:	9200      	str	r2, [sp, #0]
 800037e:	9a00      	ldr	r2, [sp, #0]
  __HAL_RCC_PWR_CLK_ENABLE();
 8000380:	69da      	ldr	r2, [r3, #28]
 8000382:	2180      	movs	r1, #128	; 0x80
 8000384:	0549      	lsls	r1, r1, #21
 8000386:	430a      	orrs	r2, r1
 8000388:	61da      	str	r2, [r3, #28]
 800038a:	69db      	ldr	r3, [r3, #28]
 800038c:	400b      	ands	r3, r1
 800038e:	9301      	str	r3, [sp, #4]
 8000390:	9b01      	ldr	r3, [sp, #4]
  /* System interrupt init*/

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8000392:	b002      	add	sp, #8
 8000394:	4770      	bx	lr
 8000396:	46c0      	nop			; (mov r8, r8)
 8000398:	40021000 	.word	0x40021000

0800039c <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
 800039c:	b510      	push	{r4, lr}
 800039e:	b088      	sub	sp, #32
 80003a0:	0004      	movs	r4, r0
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80003a2:	2214      	movs	r2, #20
 80003a4:	2100      	movs	r1, #0
 80003a6:	a803      	add	r0, sp, #12
 80003a8:	f001 f93b 	bl	8001622 <memset>
  if(hi2c->Instance==I2C1)
 80003ac:	6822      	ldr	r2, [r4, #0]
 80003ae:	4b12      	ldr	r3, [pc, #72]	; (80003f8 <HAL_I2C_MspInit+0x5c>)
 80003b0:	429a      	cmp	r2, r3
 80003b2:	d001      	beq.n	80003b8 <HAL_I2C_MspInit+0x1c>
  /* USER CODE BEGIN I2C1_MspInit 1 */

  /* USER CODE END I2C1_MspInit 1 */
  }

}
 80003b4:	b008      	add	sp, #32
 80003b6:	bd10      	pop	{r4, pc}
    __HAL_RCC_GPIOF_CLK_ENABLE();
 80003b8:	4c10      	ldr	r4, [pc, #64]	; (80003fc <HAL_I2C_MspInit+0x60>)
 80003ba:	6963      	ldr	r3, [r4, #20]
 80003bc:	2280      	movs	r2, #128	; 0x80
 80003be:	03d2      	lsls	r2, r2, #15
 80003c0:	4313      	orrs	r3, r2
 80003c2:	6163      	str	r3, [r4, #20]
 80003c4:	6963      	ldr	r3, [r4, #20]
 80003c6:	4013      	ands	r3, r2
 80003c8:	9301      	str	r3, [sp, #4]
 80003ca:	9b01      	ldr	r3, [sp, #4]
    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
 80003cc:	2303      	movs	r3, #3
 80003ce:	9303      	str	r3, [sp, #12]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
 80003d0:	2212      	movs	r2, #18
 80003d2:	9204      	str	r2, [sp, #16]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 80003d4:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Alternate = GPIO_AF1_I2C1;
 80003d6:	3b02      	subs	r3, #2
 80003d8:	9307      	str	r3, [sp, #28]
    HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 80003da:	a903      	add	r1, sp, #12
 80003dc:	4808      	ldr	r0, [pc, #32]	; (8000400 <HAL_I2C_MspInit+0x64>)
 80003de:	f000 f8eb 	bl	80005b8 <HAL_GPIO_Init>
    __HAL_RCC_I2C1_CLK_ENABLE();
 80003e2:	69e3      	ldr	r3, [r4, #28]
 80003e4:	2280      	movs	r2, #128	; 0x80
 80003e6:	0392      	lsls	r2, r2, #14
 80003e8:	4313      	orrs	r3, r2
 80003ea:	61e3      	str	r3, [r4, #28]
 80003ec:	69e3      	ldr	r3, [r4, #28]
 80003ee:	4013      	ands	r3, r2
 80003f0:	9302      	str	r3, [sp, #8]
 80003f2:	9b02      	ldr	r3, [sp, #8]
}
 80003f4:	e7de      	b.n	80003b4 <HAL_I2C_MspInit+0x18>
 80003f6:	46c0      	nop			; (mov r8, r8)
 80003f8:	40005400 	.word	0x40005400
 80003fc:	40021000 	.word	0x40021000
 8000400:	48001400 	.word	0x48001400

08000404 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 8000404:	b510      	push	{r4, lr}
 8000406:	b088      	sub	sp, #32
 8000408:	0004      	movs	r4, r0
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 800040a:	2214      	movs	r2, #20
 800040c:	2100      	movs	r1, #0
 800040e:	a803      	add	r0, sp, #12
 8000410:	f001 f907 	bl	8001622 <memset>
  if(huart->Instance==USART2)
 8000414:	6822      	ldr	r2, [r4, #0]
 8000416:	4b12      	ldr	r3, [pc, #72]	; (8000460 <HAL_UART_MspInit+0x5c>)
 8000418:	429a      	cmp	r2, r3
 800041a:	d001      	beq.n	8000420 <HAL_UART_MspInit+0x1c>
  /* USER CODE BEGIN USART2_MspInit 1 */

  /* USER CODE END USART2_MspInit 1 */
  }

}
 800041c:	b008      	add	sp, #32
 800041e:	bd10      	pop	{r4, pc}
    __HAL_RCC_USART2_CLK_ENABLE();
 8000420:	4b10      	ldr	r3, [pc, #64]	; (8000464 <HAL_UART_MspInit+0x60>)
 8000422:	69d9      	ldr	r1, [r3, #28]
 8000424:	2280      	movs	r2, #128	; 0x80
 8000426:	0292      	lsls	r2, r2, #10
 8000428:	4311      	orrs	r1, r2
 800042a:	61d9      	str	r1, [r3, #28]
 800042c:	69d9      	ldr	r1, [r3, #28]
 800042e:	4011      	ands	r1, r2
 8000430:	9101      	str	r1, [sp, #4]
 8000432:	9901      	ldr	r1, [sp, #4]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8000434:	6959      	ldr	r1, [r3, #20]
 8000436:	4311      	orrs	r1, r2
 8000438:	6159      	str	r1, [r3, #20]
 800043a:	695b      	ldr	r3, [r3, #20]
 800043c:	4013      	ands	r3, r2
 800043e:	9302      	str	r3, [sp, #8]
 8000440:	9b02      	ldr	r3, [sp, #8]
    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
 8000442:	230c      	movs	r3, #12
 8000444:	9303      	str	r3, [sp, #12]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000446:	3b0a      	subs	r3, #10
 8000448:	9304      	str	r3, [sp, #16]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 800044a:	3301      	adds	r3, #1
 800044c:	9306      	str	r3, [sp, #24]
    GPIO_InitStruct.Alternate = GPIO_AF1_USART2;
 800044e:	3b02      	subs	r3, #2
 8000450:	9307      	str	r3, [sp, #28]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000452:	2090      	movs	r0, #144	; 0x90
 8000454:	a903      	add	r1, sp, #12
 8000456:	05c0      	lsls	r0, r0, #23
 8000458:	f000 f8ae 	bl	80005b8 <HAL_GPIO_Init>
}
 800045c:	e7de      	b.n	800041c <HAL_UART_MspInit+0x18>
 800045e:	46c0      	nop			; (mov r8, r8)
 8000460:	40004400 	.word	0x40004400
 8000464:	40021000 	.word	0x40021000

08000468 <NMI_Handler>:
{
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  while (1)
 8000468:	e7fe      	b.n	8000468 <NMI_Handler>

0800046a <HardFault_Handler>:
void HardFault_Handler(void)
{
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 800046a:	e7fe      	b.n	800046a <HardFault_Handler>

0800046c <SVC_Handler>:

  /* USER CODE END SVC_IRQn 0 */
  /* USER CODE BEGIN SVC_IRQn 1 */

  /* USER CODE END SVC_IRQn 1 */
}
 800046c:	4770      	bx	lr

0800046e <PendSV_Handler>:

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 800046e:	4770      	bx	lr

08000470 <SysTick_Handler>:

/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
 8000470:	b510      	push	{r4, lr}
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8000472:	f000 f83b 	bl	80004ec <HAL_IncTick>
  /* USER CODE BEGIN SysTick_IRQn 1 */

  /* USER CODE END SysTick_IRQn 1 */
}
 8000476:	bd10      	pop	{r4, pc}

08000478 <SystemInit>:
                         before branch to main program. This call is made inside
                         the "startup_stm32f0xx.s" file.
                         User can setups the default system clock (System clock source, PLL Multiplier
                         and Divider factors, AHB/APBx prescalers and Flash settings).
   */
}
 8000478:	4770      	bx	lr
	...

0800047c <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 800047c:	b510      	push	{r4, lr}
 800047e:	0004      	movs	r4, r0
  /*Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 8000480:	4b0f      	ldr	r3, [pc, #60]	; (80004c0 <HAL_InitTick+0x44>)
 8000482:	7819      	ldrb	r1, [r3, #0]
 8000484:	20fa      	movs	r0, #250	; 0xfa
 8000486:	0080      	lsls	r0, r0, #2
 8000488:	f7ff fe1a 	bl	80000c0 <__udivsi3>
 800048c:	0001      	movs	r1, r0
 800048e:	4b0d      	ldr	r3, [pc, #52]	; (80004c4 <HAL_InitTick+0x48>)
 8000490:	6818      	ldr	r0, [r3, #0]
 8000492:	f7ff fe15 	bl	80000c0 <__udivsi3>
 8000496:	f000 f88b 	bl	80005b0 <HAL_SYSTICK_Config>
 800049a:	2800      	cmp	r0, #0
 800049c:	d10d      	bne.n	80004ba <HAL_InitTick+0x3e>
  {
    return HAL_ERROR;
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 800049e:	2c03      	cmp	r4, #3
 80004a0:	d901      	bls.n	80004a6 <HAL_InitTick+0x2a>
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
    uwTickPrio = TickPriority;
  }
  else
  {
    return HAL_ERROR;
 80004a2:	2001      	movs	r0, #1
 80004a4:	e00a      	b.n	80004bc <HAL_InitTick+0x40>
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 80004a6:	3001      	adds	r0, #1
 80004a8:	2200      	movs	r2, #0
 80004aa:	0021      	movs	r1, r4
 80004ac:	4240      	negs	r0, r0
 80004ae:	f000 f87b 	bl	80005a8 <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 80004b2:	4b05      	ldr	r3, [pc, #20]	; (80004c8 <HAL_InitTick+0x4c>)
 80004b4:	601c      	str	r4, [r3, #0]
  }

   /* Return function status */
  return HAL_OK;
 80004b6:	2000      	movs	r0, #0
 80004b8:	e000      	b.n	80004bc <HAL_InitTick+0x40>
    return HAL_ERROR;
 80004ba:	2001      	movs	r0, #1
}
 80004bc:	bd10      	pop	{r4, pc}
 80004be:	46c0      	nop			; (mov r8, r8)
 80004c0:	20000004 	.word	0x20000004
 80004c4:	20000000 	.word	0x20000000
 80004c8:	20000008 	.word	0x20000008

080004cc <HAL_Init>:
{
 80004cc:	b510      	push	{r4, lr}
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 80004ce:	4a06      	ldr	r2, [pc, #24]	; (80004e8 <HAL_Init+0x1c>)
 80004d0:	6813      	ldr	r3, [r2, #0]
 80004d2:	2110      	movs	r1, #16
 80004d4:	430b      	orrs	r3, r1
 80004d6:	6013      	str	r3, [r2, #0]
  HAL_InitTick(TICK_INT_PRIORITY);
 80004d8:	2003      	movs	r0, #3
 80004da:	f7ff ffcf 	bl	800047c <HAL_InitTick>
  HAL_MspInit();
 80004de:	f7ff ff45 	bl	800036c <HAL_MspInit>
}
 80004e2:	2000      	movs	r0, #0
 80004e4:	bd10      	pop	{r4, pc}
 80004e6:	46c0      	nop			; (mov r8, r8)
 80004e8:	40022000 	.word	0x40022000

080004ec <HAL_IncTick>:
  *       implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
  uwTick += uwTickFreq;
 80004ec:	4a03      	ldr	r2, [pc, #12]	; (80004fc <HAL_IncTick+0x10>)
 80004ee:	6811      	ldr	r1, [r2, #0]
 80004f0:	4b03      	ldr	r3, [pc, #12]	; (8000500 <HAL_IncTick+0x14>)
 80004f2:	781b      	ldrb	r3, [r3, #0]
 80004f4:	185b      	adds	r3, r3, r1
 80004f6:	6013      	str	r3, [r2, #0]
}
 80004f8:	4770      	bx	lr
 80004fa:	46c0      	nop			; (mov r8, r8)
 80004fc:	20000104 	.word	0x20000104
 8000500:	20000004 	.word	0x20000004

08000504 <HAL_GetTick>:
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
  return uwTick;
 8000504:	4b01      	ldr	r3, [pc, #4]	; (800050c <HAL_GetTick+0x8>)
 8000506:	6818      	ldr	r0, [r3, #0]
}
 8000508:	4770      	bx	lr
 800050a:	46c0      	nop			; (mov r8, r8)
 800050c:	20000104 	.word	0x20000104

08000510 <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 8000510:	b570      	push	{r4, r5, r6, lr}
  if ((int32_t)(IRQn) >= 0)
 8000512:	2800      	cmp	r0, #0
 8000514:	db11      	blt.n	800053a <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 8000516:	0883      	lsrs	r3, r0, #2
 8000518:	4d13      	ldr	r5, [pc, #76]	; (8000568 <__NVIC_SetPriority+0x58>)
 800051a:	33c0      	adds	r3, #192	; 0xc0
 800051c:	009b      	lsls	r3, r3, #2
 800051e:	595c      	ldr	r4, [r3, r5]
 8000520:	2203      	movs	r2, #3
 8000522:	4010      	ands	r0, r2
 8000524:	00c0      	lsls	r0, r0, #3
 8000526:	32fc      	adds	r2, #252	; 0xfc
 8000528:	0016      	movs	r6, r2
 800052a:	4086      	lsls	r6, r0
 800052c:	43b4      	bics	r4, r6
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 800052e:	0189      	lsls	r1, r1, #6
 8000530:	400a      	ands	r2, r1
 8000532:	4082      	lsls	r2, r0
    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 8000534:	4322      	orrs	r2, r4
 8000536:	515a      	str	r2, [r3, r5]
  else
  {
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  }
}
 8000538:	bd70      	pop	{r4, r5, r6, pc}
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 800053a:	230f      	movs	r3, #15
 800053c:	4003      	ands	r3, r0
 800053e:	3b08      	subs	r3, #8
 8000540:	089b      	lsrs	r3, r3, #2
 8000542:	3306      	adds	r3, #6
 8000544:	009b      	lsls	r3, r3, #2
 8000546:	4a09      	ldr	r2, [pc, #36]	; (800056c <__NVIC_SetPriority+0x5c>)
 8000548:	4694      	mov	ip, r2
 800054a:	4463      	add	r3, ip
 800054c:	685c      	ldr	r4, [r3, #4]
 800054e:	2203      	movs	r2, #3
 8000550:	4010      	ands	r0, r2
 8000552:	00c0      	lsls	r0, r0, #3
 8000554:	32fc      	adds	r2, #252	; 0xfc
 8000556:	0015      	movs	r5, r2
 8000558:	4085      	lsls	r5, r0
 800055a:	43ac      	bics	r4, r5
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 800055c:	0189      	lsls	r1, r1, #6
 800055e:	400a      	ands	r2, r1
 8000560:	4082      	lsls	r2, r0
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 8000562:	4322      	orrs	r2, r4
 8000564:	605a      	str	r2, [r3, #4]
}
 8000566:	e7e7      	b.n	8000538 <__NVIC_SetPriority+0x28>
 8000568:	e000e100 	.word	0xe000e100
 800056c:	e000ed00 	.word	0xe000ed00

08000570 <SysTick_Config>:
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 8000570:	3801      	subs	r0, #1
 8000572:	2380      	movs	r3, #128	; 0x80
 8000574:	045b      	lsls	r3, r3, #17
 8000576:	4298      	cmp	r0, r3
 8000578:	d20f      	bcs.n	800059a <SysTick_Config+0x2a>
  {
    return (1UL);                                                   /* Reload value impossible */
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 800057a:	4a09      	ldr	r2, [pc, #36]	; (80005a0 <SysTick_Config+0x30>)
 800057c:	6050      	str	r0, [r2, #4]
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 800057e:	4809      	ldr	r0, [pc, #36]	; (80005a4 <SysTick_Config+0x34>)
 8000580:	6a03      	ldr	r3, [r0, #32]
 8000582:	021b      	lsls	r3, r3, #8
 8000584:	0a1b      	lsrs	r3, r3, #8
 8000586:	21c0      	movs	r1, #192	; 0xc0
 8000588:	0609      	lsls	r1, r1, #24
 800058a:	430b      	orrs	r3, r1
 800058c:	6203      	str	r3, [r0, #32]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 800058e:	2300      	movs	r3, #0
 8000590:	6093      	str	r3, [r2, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 8000592:	3307      	adds	r3, #7
 8000594:	6013      	str	r3, [r2, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 8000596:	2000      	movs	r0, #0
}
 8000598:	4770      	bx	lr
    return (1UL);                                                   /* Reload value impossible */
 800059a:	2001      	movs	r0, #1
 800059c:	e7fc      	b.n	8000598 <SysTick_Config+0x28>
 800059e:	46c0      	nop			; (mov r8, r8)
 80005a0:	e000e010 	.word	0xe000e010
 80005a4:	e000ed00 	.word	0xe000ed00

080005a8 <HAL_NVIC_SetPriority>:
  *         with stm32f0xx devices, this parameter is a dummy value and it is ignored, because 
  *         no subpriority supported in Cortex M0 based products.   
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 80005a8:	b510      	push	{r4, lr}
  /* Check the parameters */
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  NVIC_SetPriority(IRQn,PreemptPriority);
 80005aa:	f7ff ffb1 	bl	8000510 <__NVIC_SetPriority>
}
 80005ae:	bd10      	pop	{r4, pc}

080005b0 <HAL_SYSTICK_Config>:
  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 80005b0:	b510      	push	{r4, lr}
   return SysTick_Config(TicksNumb);
 80005b2:	f7ff ffdd 	bl	8000570 <SysTick_Config>
}
 80005b6:	bd10      	pop	{r4, pc}

080005b8 <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 80005b8:	b5f0      	push	{r4, r5, r6, r7, lr}
 80005ba:	b083      	sub	sp, #12
  uint32_t position = 0x00u;
 80005bc:	2300      	movs	r3, #0
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 80005be:	e056      	b.n	800066e <HAL_GPIO_Init+0xb6>
         ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR;
 80005c0:	6886      	ldr	r6, [r0, #8]
        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
 80005c2:	005f      	lsls	r7, r3, #1
 80005c4:	2403      	movs	r4, #3
 80005c6:	40bc      	lsls	r4, r7
 80005c8:	43a6      	bics	r6, r4
        temp |= (GPIO_Init->Speed << (position * 2u));
 80005ca:	68cc      	ldr	r4, [r1, #12]
 80005cc:	40bc      	lsls	r4, r7
 80005ce:	4334      	orrs	r4, r6
        GPIOx->OSPEEDR = temp;
 80005d0:	6084      	str	r4, [r0, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 80005d2:	6844      	ldr	r4, [r0, #4]
        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
 80005d4:	4394      	bics	r4, r2
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 80005d6:	684e      	ldr	r6, [r1, #4]
 80005d8:	0936      	lsrs	r6, r6, #4
 80005da:	2201      	movs	r2, #1
 80005dc:	4032      	ands	r2, r6
 80005de:	409a      	lsls	r2, r3
 80005e0:	4322      	orrs	r2, r4
        GPIOx->OTYPER = temp;
 80005e2:	6042      	str	r2, [r0, #4]
 80005e4:	e053      	b.n	800068e <HAL_GPIO_Init+0xd6>
        /* Check the Alternate function parameters */
        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));

        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3u];
 80005e6:	08de      	lsrs	r6, r3, #3
 80005e8:	3608      	adds	r6, #8
 80005ea:	00b6      	lsls	r6, r6, #2
 80005ec:	5837      	ldr	r7, [r6, r0]
        temp &= ~(0xFu << ((position & 0x07u) * 4u));
 80005ee:	3205      	adds	r2, #5
 80005f0:	401a      	ands	r2, r3
 80005f2:	0092      	lsls	r2, r2, #2
 80005f4:	240f      	movs	r4, #15
 80005f6:	4094      	lsls	r4, r2
 80005f8:	43a7      	bics	r7, r4
        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
 80005fa:	690c      	ldr	r4, [r1, #16]
 80005fc:	4094      	lsls	r4, r2
 80005fe:	0022      	movs	r2, r4
 8000600:	433a      	orrs	r2, r7
        GPIOx->AFR[position >> 3u] = temp;
 8000602:	5032      	str	r2, [r6, r0]
 8000604:	e056      	b.n	80006b4 <HAL_GPIO_Init+0xfc>
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();

        temp = SYSCFG->EXTICR[position >> 2u];
        temp &= ~(0x0FuL << (4u * (position & 0x03u)));
        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
 8000606:	2602      	movs	r6, #2
 8000608:	e000      	b.n	800060c <HAL_GPIO_Init+0x54>
 800060a:	2600      	movs	r6, #0
 800060c:	40a6      	lsls	r6, r4
 800060e:	0034      	movs	r4, r6
 8000610:	433c      	orrs	r4, r7
        SYSCFG->EXTICR[position >> 2u] = temp;
 8000612:	3202      	adds	r2, #2
 8000614:	0092      	lsls	r2, r2, #2
 8000616:	4e42      	ldr	r6, [pc, #264]	; (8000720 <HAL_GPIO_Init+0x168>)
 8000618:	5194      	str	r4, [r2, r6]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR;
 800061a:	4a42      	ldr	r2, [pc, #264]	; (8000724 <HAL_GPIO_Init+0x16c>)
 800061c:	6897      	ldr	r7, [r2, #8]
        temp &= ~(iocurrent);
 800061e:	43ea      	mvns	r2, r5
 8000620:	003e      	movs	r6, r7
 8000622:	43ae      	bics	r6, r5
        if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
 8000624:	684c      	ldr	r4, [r1, #4]
 8000626:	02e4      	lsls	r4, r4, #11
 8000628:	d501      	bpl.n	800062e <HAL_GPIO_Init+0x76>
        {
          temp |= iocurrent;
 800062a:	003e      	movs	r6, r7
 800062c:	432e      	orrs	r6, r5
        }
        EXTI->RTSR = temp;
 800062e:	4c3d      	ldr	r4, [pc, #244]	; (8000724 <HAL_GPIO_Init+0x16c>)
 8000630:	60a6      	str	r6, [r4, #8]

        temp = EXTI->FTSR;
 8000632:	68e7      	ldr	r7, [r4, #12]
        temp &= ~(iocurrent);
 8000634:	003e      	movs	r6, r7
 8000636:	4016      	ands	r6, r2
        if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
 8000638:	684c      	ldr	r4, [r1, #4]
 800063a:	02a4      	lsls	r4, r4, #10
 800063c:	d501      	bpl.n	8000642 <HAL_GPIO_Init+0x8a>
        {
          temp |= iocurrent;
 800063e:	003e      	movs	r6, r7
 8000640:	432e      	orrs	r6, r5
        }
        EXTI->FTSR = temp;
 8000642:	4c38      	ldr	r4, [pc, #224]	; (8000724 <HAL_GPIO_Init+0x16c>)
 8000644:	60e6      	str	r6, [r4, #12]

        /* Clear EXTI line configuration */
        temp = EXTI->EMR;
 8000646:	6867      	ldr	r7, [r4, #4]
        temp &= ~(iocurrent);
 8000648:	003e      	movs	r6, r7
 800064a:	4016      	ands	r6, r2
        if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
 800064c:	684c      	ldr	r4, [r1, #4]
 800064e:	03a4      	lsls	r4, r4, #14
 8000650:	d501      	bpl.n	8000656 <HAL_GPIO_Init+0x9e>
        {
          temp |= iocurrent;
 8000652:	003e      	movs	r6, r7
 8000654:	432e      	orrs	r6, r5
        }
        EXTI->EMR = temp;
 8000656:	4c33      	ldr	r4, [pc, #204]	; (8000724 <HAL_GPIO_Init+0x16c>)
 8000658:	6066      	str	r6, [r4, #4]

        temp = EXTI->IMR;
 800065a:	6826      	ldr	r6, [r4, #0]
        temp &= ~(iocurrent);
 800065c:	4032      	ands	r2, r6
        if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
 800065e:	684c      	ldr	r4, [r1, #4]
 8000660:	03e4      	lsls	r4, r4, #15
 8000662:	d501      	bpl.n	8000668 <HAL_GPIO_Init+0xb0>
        {
          temp |= iocurrent;
 8000664:	002a      	movs	r2, r5
 8000666:	4332      	orrs	r2, r6
        }
        EXTI->IMR = temp;
 8000668:	4c2e      	ldr	r4, [pc, #184]	; (8000724 <HAL_GPIO_Init+0x16c>)
 800066a:	6022      	str	r2, [r4, #0]
      }
    }

    position++;
 800066c:	3301      	adds	r3, #1
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 800066e:	680c      	ldr	r4, [r1, #0]
 8000670:	0022      	movs	r2, r4
 8000672:	40da      	lsrs	r2, r3
 8000674:	d051      	beq.n	800071a <HAL_GPIO_Init+0x162>
    iocurrent = (GPIO_Init->Pin) & (1uL << position);
 8000676:	2201      	movs	r2, #1
 8000678:	409a      	lsls	r2, r3
 800067a:	0025      	movs	r5, r4
 800067c:	4015      	ands	r5, r2
    if (iocurrent != 0x00u)
 800067e:	4214      	tst	r4, r2
 8000680:	d0f4      	beq.n	800066c <HAL_GPIO_Init+0xb4>
      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
 8000682:	684e      	ldr	r6, [r1, #4]
 8000684:	2403      	movs	r4, #3
 8000686:	4034      	ands	r4, r6
 8000688:	3c01      	subs	r4, #1
 800068a:	2c01      	cmp	r4, #1
 800068c:	d998      	bls.n	80005c0 <HAL_GPIO_Init+0x8>
      if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 800068e:	684c      	ldr	r4, [r1, #4]
 8000690:	2203      	movs	r2, #3
 8000692:	4022      	ands	r2, r4
 8000694:	2a03      	cmp	r2, #3
 8000696:	d008      	beq.n	80006aa <HAL_GPIO_Init+0xf2>
        temp = GPIOx->PUPDR;
 8000698:	68c4      	ldr	r4, [r0, #12]
        temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
 800069a:	005e      	lsls	r6, r3, #1
 800069c:	2203      	movs	r2, #3
 800069e:	40b2      	lsls	r2, r6
 80006a0:	4394      	bics	r4, r2
        temp |= ((GPIO_Init->Pull) << (position * 2u));
 80006a2:	688a      	ldr	r2, [r1, #8]
 80006a4:	40b2      	lsls	r2, r6
 80006a6:	4322      	orrs	r2, r4
        GPIOx->PUPDR = temp;
 80006a8:	60c2      	str	r2, [r0, #12]
      if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 80006aa:	684c      	ldr	r4, [r1, #4]
 80006ac:	2203      	movs	r2, #3
 80006ae:	4022      	ands	r2, r4
 80006b0:	2a02      	cmp	r2, #2
 80006b2:	d098      	beq.n	80005e6 <HAL_GPIO_Init+0x2e>
      temp = GPIOx->MODER;
 80006b4:	6804      	ldr	r4, [r0, #0]
      temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
 80006b6:	005e      	lsls	r6, r3, #1
 80006b8:	2203      	movs	r2, #3
 80006ba:	0017      	movs	r7, r2
 80006bc:	40b7      	lsls	r7, r6
 80006be:	43bc      	bics	r4, r7
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
 80006c0:	684f      	ldr	r7, [r1, #4]
 80006c2:	403a      	ands	r2, r7
 80006c4:	40b2      	lsls	r2, r6
 80006c6:	4322      	orrs	r2, r4
      GPIOx->MODER = temp;
 80006c8:	6002      	str	r2, [r0, #0]
      if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
 80006ca:	684c      	ldr	r4, [r1, #4]
 80006cc:	22c0      	movs	r2, #192	; 0xc0
 80006ce:	0292      	lsls	r2, r2, #10
 80006d0:	4214      	tst	r4, r2
 80006d2:	d0cb      	beq.n	800066c <HAL_GPIO_Init+0xb4>
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 80006d4:	4c14      	ldr	r4, [pc, #80]	; (8000728 <HAL_GPIO_Init+0x170>)
 80006d6:	69a6      	ldr	r6, [r4, #24]
 80006d8:	2201      	movs	r2, #1
 80006da:	4316      	orrs	r6, r2
 80006dc:	61a6      	str	r6, [r4, #24]
 80006de:	69a4      	ldr	r4, [r4, #24]
 80006e0:	4022      	ands	r2, r4
 80006e2:	9201      	str	r2, [sp, #4]
 80006e4:	9a01      	ldr	r2, [sp, #4]
        temp = SYSCFG->EXTICR[position >> 2u];
 80006e6:	089a      	lsrs	r2, r3, #2
 80006e8:	1c94      	adds	r4, r2, #2
 80006ea:	00a4      	lsls	r4, r4, #2
 80006ec:	4e0c      	ldr	r6, [pc, #48]	; (8000720 <HAL_GPIO_Init+0x168>)
 80006ee:	59a7      	ldr	r7, [r4, r6]
        temp &= ~(0x0FuL << (4u * (position & 0x03u)));
 80006f0:	2403      	movs	r4, #3
 80006f2:	401c      	ands	r4, r3
 80006f4:	00a4      	lsls	r4, r4, #2
 80006f6:	260f      	movs	r6, #15
 80006f8:	40a6      	lsls	r6, r4
 80006fa:	43b7      	bics	r7, r6
        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
 80006fc:	2690      	movs	r6, #144	; 0x90
 80006fe:	05f6      	lsls	r6, r6, #23
 8000700:	42b0      	cmp	r0, r6
 8000702:	d082      	beq.n	800060a <HAL_GPIO_Init+0x52>
 8000704:	4e09      	ldr	r6, [pc, #36]	; (800072c <HAL_GPIO_Init+0x174>)
 8000706:	42b0      	cmp	r0, r6
 8000708:	d005      	beq.n	8000716 <HAL_GPIO_Init+0x15e>
 800070a:	4e09      	ldr	r6, [pc, #36]	; (8000730 <HAL_GPIO_Init+0x178>)
 800070c:	42b0      	cmp	r0, r6
 800070e:	d100      	bne.n	8000712 <HAL_GPIO_Init+0x15a>
 8000710:	e779      	b.n	8000606 <HAL_GPIO_Init+0x4e>
 8000712:	2605      	movs	r6, #5
 8000714:	e77a      	b.n	800060c <HAL_GPIO_Init+0x54>
 8000716:	2601      	movs	r6, #1
 8000718:	e778      	b.n	800060c <HAL_GPIO_Init+0x54>
  } 
}
 800071a:	b003      	add	sp, #12
 800071c:	bdf0      	pop	{r4, r5, r6, r7, pc}
 800071e:	46c0      	nop			; (mov r8, r8)
 8000720:	40010000 	.word	0x40010000
 8000724:	40010400 	.word	0x40010400
 8000728:	40021000 	.word	0x40021000
 800072c:	48000400 	.word	0x48000400
 8000730:	48000800 	.word	0x48000800

08000734 <HAL_I2C_Init>:
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
  *                the configuration information for the specified I2C.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
 8000734:	b510      	push	{r4, lr}
 8000736:	1e04      	subs	r4, r0, #0
  /* Check the I2C handle allocation */
  if (hi2c == NULL)
 8000738:	d059      	beq.n	80007ee <HAL_I2C_Init+0xba>
  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));

  if (hi2c->State == HAL_I2C_STATE_RESET)
 800073a:	2341      	movs	r3, #65	; 0x41
 800073c:	5cc3      	ldrb	r3, [r0, r3]
 800073e:	2b00      	cmp	r3, #0
 8000740:	d043      	beq.n	80007ca <HAL_I2C_Init+0x96>
    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
    HAL_I2C_MspInit(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
  }

  hi2c->State = HAL_I2C_STATE_BUSY;
 8000742:	2341      	movs	r3, #65	; 0x41
 8000744:	2224      	movs	r2, #36	; 0x24
 8000746:	54e2      	strb	r2, [r4, r3]

  /* Disable the selected I2C peripheral */
  __HAL_I2C_DISABLE(hi2c);
 8000748:	6822      	ldr	r2, [r4, #0]
 800074a:	6813      	ldr	r3, [r2, #0]
 800074c:	2101      	movs	r1, #1
 800074e:	438b      	bics	r3, r1
 8000750:	6013      	str	r3, [r2, #0]

  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
  /* Configure I2Cx: Frequency range */
  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
 8000752:	6863      	ldr	r3, [r4, #4]
 8000754:	6822      	ldr	r2, [r4, #0]
 8000756:	4927      	ldr	r1, [pc, #156]	; (80007f4 <HAL_I2C_Init+0xc0>)
 8000758:	400b      	ands	r3, r1
 800075a:	6113      	str	r3, [r2, #16]

  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
  /* Disable Own Address1 before set the Own Address1 configuration */
  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
 800075c:	6822      	ldr	r2, [r4, #0]
 800075e:	6893      	ldr	r3, [r2, #8]
 8000760:	4925      	ldr	r1, [pc, #148]	; (80007f8 <HAL_I2C_Init+0xc4>)
 8000762:	400b      	ands	r3, r1
 8000764:	6093      	str	r3, [r2, #8]

  /* Configure I2Cx: Own Address1 and ack own address1 mode */
  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
 8000766:	68e3      	ldr	r3, [r4, #12]
 8000768:	2b01      	cmp	r3, #1
 800076a:	d034      	beq.n	80007d6 <HAL_I2C_Init+0xa2>
  {
    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
  }
  else /* I2C_ADDRESSINGMODE_10BIT */
  {
    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
 800076c:	68a1      	ldr	r1, [r4, #8]
 800076e:	6822      	ldr	r2, [r4, #0]
 8000770:	2384      	movs	r3, #132	; 0x84
 8000772:	021b      	lsls	r3, r3, #8
 8000774:	430b      	orrs	r3, r1
 8000776:	6093      	str	r3, [r2, #8]
  }

  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
  /* Configure I2Cx: Addressing Master mode */
  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
 8000778:	68e3      	ldr	r3, [r4, #12]
 800077a:	2b02      	cmp	r3, #2
 800077c:	d032      	beq.n	80007e4 <HAL_I2C_Init+0xb0>
  {
    hi2c->Instance->CR2 = (I2C_CR2_ADD10);
  }
  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
 800077e:	6822      	ldr	r2, [r4, #0]
 8000780:	6851      	ldr	r1, [r2, #4]
 8000782:	4b1e      	ldr	r3, [pc, #120]	; (80007fc <HAL_I2C_Init+0xc8>)
 8000784:	430b      	orrs	r3, r1
 8000786:	6053      	str	r3, [r2, #4]

  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
  /* Disable Own Address2 before set the Own Address2 configuration */
  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
 8000788:	6822      	ldr	r2, [r4, #0]
 800078a:	68d3      	ldr	r3, [r2, #12]
 800078c:	491a      	ldr	r1, [pc, #104]	; (80007f8 <HAL_I2C_Init+0xc4>)
 800078e:	400b      	ands	r3, r1
 8000790:	60d3      	str	r3, [r2, #12]

  /* Configure I2Cx: Dual mode and Own Address2 */
  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
 8000792:	6923      	ldr	r3, [r4, #16]
 8000794:	6962      	ldr	r2, [r4, #20]
 8000796:	4313      	orrs	r3, r2
                          (hi2c->Init.OwnAddress2Masks << 8));
 8000798:	69a2      	ldr	r2, [r4, #24]
 800079a:	0212      	lsls	r2, r2, #8
  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
 800079c:	6821      	ldr	r1, [r4, #0]
 800079e:	4313      	orrs	r3, r2
 80007a0:	60cb      	str	r3, [r1, #12]

  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
  /* Configure I2Cx: Generalcall and NoStretch mode */
  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
 80007a2:	69e3      	ldr	r3, [r4, #28]
 80007a4:	6a21      	ldr	r1, [r4, #32]
 80007a6:	6822      	ldr	r2, [r4, #0]
 80007a8:	430b      	orrs	r3, r1
 80007aa:	6013      	str	r3, [r2, #0]

  /* Enable the selected I2C peripheral */
  __HAL_I2C_ENABLE(hi2c);
 80007ac:	6822      	ldr	r2, [r4, #0]
 80007ae:	6813      	ldr	r3, [r2, #0]
 80007b0:	2101      	movs	r1, #1
 80007b2:	430b      	orrs	r3, r1
 80007b4:	6013      	str	r3, [r2, #0]

  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 80007b6:	2300      	movs	r3, #0
 80007b8:	6463      	str	r3, [r4, #68]	; 0x44
  hi2c->State = HAL_I2C_STATE_READY;
 80007ba:	2241      	movs	r2, #65	; 0x41
 80007bc:	311f      	adds	r1, #31
 80007be:	54a1      	strb	r1, [r4, r2]
  hi2c->PreviousState = I2C_STATE_NONE;
 80007c0:	6323      	str	r3, [r4, #48]	; 0x30
  hi2c->Mode = HAL_I2C_MODE_NONE;
 80007c2:	3201      	adds	r2, #1
 80007c4:	54a3      	strb	r3, [r4, r2]

  return HAL_OK;
 80007c6:	2000      	movs	r0, #0
}
 80007c8:	bd10      	pop	{r4, pc}
    hi2c->Lock = HAL_UNLOCKED;
 80007ca:	3340      	adds	r3, #64	; 0x40
 80007cc:	2200      	movs	r2, #0
 80007ce:	54c2      	strb	r2, [r0, r3]
    HAL_I2C_MspInit(hi2c);
 80007d0:	f7ff fde4 	bl	800039c <HAL_I2C_MspInit>
 80007d4:	e7b5      	b.n	8000742 <HAL_I2C_Init+0xe>
    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
 80007d6:	68a1      	ldr	r1, [r4, #8]
 80007d8:	6822      	ldr	r2, [r4, #0]
 80007da:	2380      	movs	r3, #128	; 0x80
 80007dc:	021b      	lsls	r3, r3, #8
 80007de:	430b      	orrs	r3, r1
 80007e0:	6093      	str	r3, [r2, #8]
 80007e2:	e7c9      	b.n	8000778 <HAL_I2C_Init+0x44>
    hi2c->Instance->CR2 = (I2C_CR2_ADD10);
 80007e4:	6823      	ldr	r3, [r4, #0]
 80007e6:	2280      	movs	r2, #128	; 0x80
 80007e8:	0112      	lsls	r2, r2, #4
 80007ea:	605a      	str	r2, [r3, #4]
 80007ec:	e7c7      	b.n	800077e <HAL_I2C_Init+0x4a>
    return HAL_ERROR;
 80007ee:	2001      	movs	r0, #1
 80007f0:	e7ea      	b.n	80007c8 <HAL_I2C_Init+0x94>
 80007f2:	46c0      	nop			; (mov r8, r8)
 80007f4:	f0ffffff 	.word	0xf0ffffff
 80007f8:	ffff7fff 	.word	0xffff7fff
 80007fc:	02008000 	.word	0x02008000

08000800 <HAL_I2CEx_ConfigAnalogFilter>:
  *                the configuration information for the specified I2Cx peripheral.
  * @param  AnalogFilter New state of the Analog filter.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
 8000800:	b5f0      	push	{r4, r5, r6, r7, lr}
  /* Check the parameters */
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));

  if (hi2c->State == HAL_I2C_STATE_READY)
 8000802:	2341      	movs	r3, #65	; 0x41
 8000804:	5cc3      	ldrb	r3, [r0, r3]
 8000806:	2b20      	cmp	r3, #32
 8000808:	d120      	bne.n	800084c <HAL_I2CEx_ConfigAnalogFilter+0x4c>
  {
    /* Process Locked */
    __HAL_LOCK(hi2c);
 800080a:	3320      	adds	r3, #32
 800080c:	5cc3      	ldrb	r3, [r0, r3]
 800080e:	2b01      	cmp	r3, #1
 8000810:	d01e      	beq.n	8000850 <HAL_I2CEx_ConfigAnalogFilter+0x50>
 8000812:	2440      	movs	r4, #64	; 0x40
 8000814:	2201      	movs	r2, #1
 8000816:	5502      	strb	r2, [r0, r4]

    hi2c->State = HAL_I2C_STATE_BUSY;
 8000818:	2541      	movs	r5, #65	; 0x41
 800081a:	2324      	movs	r3, #36	; 0x24
 800081c:	5543      	strb	r3, [r0, r5]

    /* Disable the selected I2C peripheral */
    __HAL_I2C_DISABLE(hi2c);
 800081e:	6806      	ldr	r6, [r0, #0]
 8000820:	6833      	ldr	r3, [r6, #0]
 8000822:	4393      	bics	r3, r2
 8000824:	6033      	str	r3, [r6, #0]

    /* Reset I2Cx ANOFF bit */
    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
 8000826:	6806      	ldr	r6, [r0, #0]
 8000828:	6833      	ldr	r3, [r6, #0]
 800082a:	4f0a      	ldr	r7, [pc, #40]	; (8000854 <HAL_I2CEx_ConfigAnalogFilter+0x54>)
 800082c:	403b      	ands	r3, r7
 800082e:	6033      	str	r3, [r6, #0]

    /* Set analog filter bit*/
    hi2c->Instance->CR1 |= AnalogFilter;
 8000830:	6806      	ldr	r6, [r0, #0]
 8000832:	6833      	ldr	r3, [r6, #0]
 8000834:	430b      	orrs	r3, r1
 8000836:	6033      	str	r3, [r6, #0]

    __HAL_I2C_ENABLE(hi2c);
 8000838:	6801      	ldr	r1, [r0, #0]
 800083a:	680b      	ldr	r3, [r1, #0]
 800083c:	4313      	orrs	r3, r2
 800083e:	600b      	str	r3, [r1, #0]

    hi2c->State = HAL_I2C_STATE_READY;
 8000840:	2320      	movs	r3, #32
 8000842:	5543      	strb	r3, [r0, r5]

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 8000844:	2300      	movs	r3, #0
 8000846:	5503      	strb	r3, [r0, r4]

    return HAL_OK;
 8000848:	2000      	movs	r0, #0
  }
  else
  {
    return HAL_BUSY;
  }
}
 800084a:	bdf0      	pop	{r4, r5, r6, r7, pc}
    return HAL_BUSY;
 800084c:	2002      	movs	r0, #2
 800084e:	e7fc      	b.n	800084a <HAL_I2CEx_ConfigAnalogFilter+0x4a>
    __HAL_LOCK(hi2c);
 8000850:	2002      	movs	r0, #2
 8000852:	e7fa      	b.n	800084a <HAL_I2CEx_ConfigAnalogFilter+0x4a>
 8000854:	ffffefff 	.word	0xffffefff

08000858 <HAL_I2CEx_ConfigDigitalFilter>:
  *                the configuration information for the specified I2Cx peripheral.
  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
 8000858:	b5f0      	push	{r4, r5, r6, r7, lr}

  /* Check the parameters */
  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));

  if (hi2c->State == HAL_I2C_STATE_READY)
 800085a:	2341      	movs	r3, #65	; 0x41
 800085c:	5cc3      	ldrb	r3, [r0, r3]
 800085e:	2b20      	cmp	r3, #32
 8000860:	d11e      	bne.n	80008a0 <HAL_I2CEx_ConfigDigitalFilter+0x48>
  {
    /* Process Locked */
    __HAL_LOCK(hi2c);
 8000862:	3320      	adds	r3, #32
 8000864:	5cc3      	ldrb	r3, [r0, r3]
 8000866:	2b01      	cmp	r3, #1
 8000868:	d01c      	beq.n	80008a4 <HAL_I2CEx_ConfigDigitalFilter+0x4c>
 800086a:	2440      	movs	r4, #64	; 0x40
 800086c:	2201      	movs	r2, #1
 800086e:	5502      	strb	r2, [r0, r4]

    hi2c->State = HAL_I2C_STATE_BUSY;
 8000870:	2541      	movs	r5, #65	; 0x41
 8000872:	2324      	movs	r3, #36	; 0x24
 8000874:	5543      	strb	r3, [r0, r5]

    /* Disable the selected I2C peripheral */
    __HAL_I2C_DISABLE(hi2c);
 8000876:	6806      	ldr	r6, [r0, #0]
 8000878:	6833      	ldr	r3, [r6, #0]
 800087a:	4393      	bics	r3, r2
 800087c:	6033      	str	r3, [r6, #0]

    /* Get the old register value */
    tmpreg = hi2c->Instance->CR1;
 800087e:	6806      	ldr	r6, [r0, #0]
 8000880:	6833      	ldr	r3, [r6, #0]

    /* Reset I2Cx DNF bits [11:8] */
    tmpreg &= ~(I2C_CR1_DNF);
 8000882:	4f09      	ldr	r7, [pc, #36]	; (80008a8 <HAL_I2CEx_ConfigDigitalFilter+0x50>)
 8000884:	403b      	ands	r3, r7

    /* Set I2Cx DNF coefficient */
    tmpreg |= DigitalFilter << 8U;
 8000886:	0209      	lsls	r1, r1, #8
 8000888:	4319      	orrs	r1, r3

    /* Store the new register value */
    hi2c->Instance->CR1 = tmpreg;
 800088a:	6031      	str	r1, [r6, #0]

    __HAL_I2C_ENABLE(hi2c);
 800088c:	6801      	ldr	r1, [r0, #0]
 800088e:	680b      	ldr	r3, [r1, #0]
 8000890:	4313      	orrs	r3, r2
 8000892:	600b      	str	r3, [r1, #0]

    hi2c->State = HAL_I2C_STATE_READY;
 8000894:	2320      	movs	r3, #32
 8000896:	5543      	strb	r3, [r0, r5]

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 8000898:	2300      	movs	r3, #0
 800089a:	5503      	strb	r3, [r0, r4]

    return HAL_OK;
 800089c:	2000      	movs	r0, #0
  }
  else
  {
    return HAL_BUSY;
  }
}
 800089e:	bdf0      	pop	{r4, r5, r6, r7, pc}
    return HAL_BUSY;
 80008a0:	2002      	movs	r0, #2
 80008a2:	e7fc      	b.n	800089e <HAL_I2CEx_ConfigDigitalFilter+0x46>
    __HAL_LOCK(hi2c);
 80008a4:	2002      	movs	r0, #2
 80008a6:	e7fa      	b.n	800089e <HAL_I2CEx_ConfigDigitalFilter+0x46>
 80008a8:	fffff0ff 	.word	0xfffff0ff

080008ac <HAL_RCC_OscConfig>:
  *         supported by this macro. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 80008ac:	b570      	push	{r4, r5, r6, lr}
 80008ae:	b082      	sub	sp, #8
 80008b0:	1e04      	subs	r4, r0, #0
  uint32_t tickstart;
  uint32_t pll_config;
  uint32_t pll_config2;

  /* Check Null pointer */
  if(RCC_OscInitStruct == NULL)
 80008b2:	d100      	bne.n	80008b6 <HAL_RCC_OscConfig+0xa>
 80008b4:	e27f      	b.n	8000db6 <HAL_RCC_OscConfig+0x50a>

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  /*------------------------------- HSE Configuration ------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 80008b6:	6803      	ldr	r3, [r0, #0]
 80008b8:	07db      	lsls	r3, r3, #31
 80008ba:	d52b      	bpl.n	8000914 <HAL_RCC_OscConfig+0x68>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 
 80008bc:	4bb3      	ldr	r3, [pc, #716]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 80008be:	685a      	ldr	r2, [r3, #4]
 80008c0:	230c      	movs	r3, #12
 80008c2:	4013      	ands	r3, r2
 80008c4:	2b04      	cmp	r3, #4
 80008c6:	d01d      	beq.n	8000904 <HAL_RCC_OscConfig+0x58>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 80008c8:	4bb0      	ldr	r3, [pc, #704]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 80008ca:	685a      	ldr	r2, [r3, #4]
 80008cc:	230c      	movs	r3, #12
 80008ce:	4013      	ands	r3, r2
 80008d0:	2b08      	cmp	r3, #8
 80008d2:	d00e      	beq.n	80008f2 <HAL_RCC_OscConfig+0x46>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 80008d4:	6863      	ldr	r3, [r4, #4]
 80008d6:	2b01      	cmp	r3, #1
 80008d8:	d041      	beq.n	800095e <HAL_RCC_OscConfig+0xb2>
 80008da:	2b00      	cmp	r3, #0
 80008dc:	d156      	bne.n	800098c <HAL_RCC_OscConfig+0xe0>
 80008de:	4bab      	ldr	r3, [pc, #684]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 80008e0:	681a      	ldr	r2, [r3, #0]
 80008e2:	49ab      	ldr	r1, [pc, #684]	; (8000b90 <HAL_RCC_OscConfig+0x2e4>)
 80008e4:	400a      	ands	r2, r1
 80008e6:	601a      	str	r2, [r3, #0]
 80008e8:	681a      	ldr	r2, [r3, #0]
 80008ea:	49aa      	ldr	r1, [pc, #680]	; (8000b94 <HAL_RCC_OscConfig+0x2e8>)
 80008ec:	400a      	ands	r2, r1
 80008ee:	601a      	str	r2, [r3, #0]
 80008f0:	e03b      	b.n	800096a <HAL_RCC_OscConfig+0xbe>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 80008f2:	4ba6      	ldr	r3, [pc, #664]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 80008f4:	685b      	ldr	r3, [r3, #4]
 80008f6:	22c0      	movs	r2, #192	; 0xc0
 80008f8:	0252      	lsls	r2, r2, #9
 80008fa:	4013      	ands	r3, r2
 80008fc:	2280      	movs	r2, #128	; 0x80
 80008fe:	0252      	lsls	r2, r2, #9
 8000900:	4293      	cmp	r3, r2
 8000902:	d1e7      	bne.n	80008d4 <HAL_RCC_OscConfig+0x28>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8000904:	4ba1      	ldr	r3, [pc, #644]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000906:	681b      	ldr	r3, [r3, #0]
 8000908:	039b      	lsls	r3, r3, #14
 800090a:	d503      	bpl.n	8000914 <HAL_RCC_OscConfig+0x68>
 800090c:	6863      	ldr	r3, [r4, #4]
 800090e:	2b00      	cmp	r3, #0
 8000910:	d100      	bne.n	8000914 <HAL_RCC_OscConfig+0x68>
 8000912:	e253      	b.n	8000dbc <HAL_RCC_OscConfig+0x510>
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8000914:	6823      	ldr	r3, [r4, #0]
 8000916:	079b      	lsls	r3, r3, #30
 8000918:	d577      	bpl.n	8000a0a <HAL_RCC_OscConfig+0x15e>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
    
    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ 
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 
 800091a:	4b9c      	ldr	r3, [pc, #624]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 800091c:	685b      	ldr	r3, [r3, #4]
 800091e:	220c      	movs	r2, #12
 8000920:	421a      	tst	r2, r3
 8000922:	d062      	beq.n	80009ea <HAL_RCC_OscConfig+0x13e>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
 8000924:	4b99      	ldr	r3, [pc, #612]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000926:	685a      	ldr	r2, [r3, #4]
 8000928:	230c      	movs	r3, #12
 800092a:	4013      	ands	r3, r2
 800092c:	2b08      	cmp	r3, #8
 800092e:	d053      	beq.n	80009d8 <HAL_RCC_OscConfig+0x12c>
      }
    }
    else
    {
      /* Check the HSI State */
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 8000930:	68e3      	ldr	r3, [r4, #12]
 8000932:	2b00      	cmp	r3, #0
 8000934:	d100      	bne.n	8000938 <HAL_RCC_OscConfig+0x8c>
 8000936:	e08a      	b.n	8000a4e <HAL_RCC_OscConfig+0x1a2>
      {
       /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 8000938:	4a94      	ldr	r2, [pc, #592]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 800093a:	6813      	ldr	r3, [r2, #0]
 800093c:	2101      	movs	r1, #1
 800093e:	430b      	orrs	r3, r1
 8000940:	6013      	str	r3, [r2, #0]
        
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000942:	f7ff fddf 	bl	8000504 <HAL_GetTick>
 8000946:	0005      	movs	r5, r0
        
        /* Wait till HSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8000948:	4b90      	ldr	r3, [pc, #576]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 800094a:	681b      	ldr	r3, [r3, #0]
 800094c:	079b      	lsls	r3, r3, #30
 800094e:	d475      	bmi.n	8000a3c <HAL_RCC_OscConfig+0x190>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8000950:	f7ff fdd8 	bl	8000504 <HAL_GetTick>
 8000954:	1b40      	subs	r0, r0, r5
 8000956:	2802      	cmp	r0, #2
 8000958:	d9f6      	bls.n	8000948 <HAL_RCC_OscConfig+0x9c>
          {
            return HAL_TIMEOUT;
 800095a:	2003      	movs	r0, #3
 800095c:	e22c      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 800095e:	4a8b      	ldr	r2, [pc, #556]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000960:	6811      	ldr	r1, [r2, #0]
 8000962:	2380      	movs	r3, #128	; 0x80
 8000964:	025b      	lsls	r3, r3, #9
 8000966:	430b      	orrs	r3, r1
 8000968:	6013      	str	r3, [r2, #0]
      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 800096a:	6863      	ldr	r3, [r4, #4]
 800096c:	2b00      	cmp	r3, #0
 800096e:	d025      	beq.n	80009bc <HAL_RCC_OscConfig+0x110>
        tickstart = HAL_GetTick();
 8000970:	f7ff fdc8 	bl	8000504 <HAL_GetTick>
 8000974:	0005      	movs	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8000976:	4b85      	ldr	r3, [pc, #532]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000978:	681b      	ldr	r3, [r3, #0]
 800097a:	039b      	lsls	r3, r3, #14
 800097c:	d4ca      	bmi.n	8000914 <HAL_RCC_OscConfig+0x68>
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 800097e:	f7ff fdc1 	bl	8000504 <HAL_GetTick>
 8000982:	1b40      	subs	r0, r0, r5
 8000984:	2864      	cmp	r0, #100	; 0x64
 8000986:	d9f6      	bls.n	8000976 <HAL_RCC_OscConfig+0xca>
            return HAL_TIMEOUT;
 8000988:	2003      	movs	r0, #3
 800098a:	e215      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 800098c:	2b05      	cmp	r3, #5
 800098e:	d009      	beq.n	80009a4 <HAL_RCC_OscConfig+0xf8>
 8000990:	4b7e      	ldr	r3, [pc, #504]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000992:	681a      	ldr	r2, [r3, #0]
 8000994:	497e      	ldr	r1, [pc, #504]	; (8000b90 <HAL_RCC_OscConfig+0x2e4>)
 8000996:	400a      	ands	r2, r1
 8000998:	601a      	str	r2, [r3, #0]
 800099a:	681a      	ldr	r2, [r3, #0]
 800099c:	497d      	ldr	r1, [pc, #500]	; (8000b94 <HAL_RCC_OscConfig+0x2e8>)
 800099e:	400a      	ands	r2, r1
 80009a0:	601a      	str	r2, [r3, #0]
 80009a2:	e7e2      	b.n	800096a <HAL_RCC_OscConfig+0xbe>
 80009a4:	4b79      	ldr	r3, [pc, #484]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 80009a6:	6819      	ldr	r1, [r3, #0]
 80009a8:	2280      	movs	r2, #128	; 0x80
 80009aa:	02d2      	lsls	r2, r2, #11
 80009ac:	430a      	orrs	r2, r1
 80009ae:	601a      	str	r2, [r3, #0]
 80009b0:	6819      	ldr	r1, [r3, #0]
 80009b2:	2280      	movs	r2, #128	; 0x80
 80009b4:	0252      	lsls	r2, r2, #9
 80009b6:	430a      	orrs	r2, r1
 80009b8:	601a      	str	r2, [r3, #0]
 80009ba:	e7d6      	b.n	800096a <HAL_RCC_OscConfig+0xbe>
        tickstart = HAL_GetTick();
 80009bc:	f7ff fda2 	bl	8000504 <HAL_GetTick>
 80009c0:	0005      	movs	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 80009c2:	4b72      	ldr	r3, [pc, #456]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 80009c4:	681b      	ldr	r3, [r3, #0]
 80009c6:	039b      	lsls	r3, r3, #14
 80009c8:	d5a4      	bpl.n	8000914 <HAL_RCC_OscConfig+0x68>
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 80009ca:	f7ff fd9b 	bl	8000504 <HAL_GetTick>
 80009ce:	1b40      	subs	r0, r0, r5
 80009d0:	2864      	cmp	r0, #100	; 0x64
 80009d2:	d9f6      	bls.n	80009c2 <HAL_RCC_OscConfig+0x116>
            return HAL_TIMEOUT;
 80009d4:	2003      	movs	r0, #3
 80009d6:	e1ef      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
 80009d8:	4b6c      	ldr	r3, [pc, #432]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 80009da:	685b      	ldr	r3, [r3, #4]
 80009dc:	22c0      	movs	r2, #192	; 0xc0
 80009de:	0252      	lsls	r2, r2, #9
 80009e0:	4013      	ands	r3, r2
 80009e2:	2280      	movs	r2, #128	; 0x80
 80009e4:	0212      	lsls	r2, r2, #8
 80009e6:	4293      	cmp	r3, r2
 80009e8:	d1a2      	bne.n	8000930 <HAL_RCC_OscConfig+0x84>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 80009ea:	4b68      	ldr	r3, [pc, #416]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 80009ec:	681b      	ldr	r3, [r3, #0]
 80009ee:	079b      	lsls	r3, r3, #30
 80009f0:	d503      	bpl.n	80009fa <HAL_RCC_OscConfig+0x14e>
 80009f2:	68e3      	ldr	r3, [r4, #12]
 80009f4:	2b01      	cmp	r3, #1
 80009f6:	d000      	beq.n	80009fa <HAL_RCC_OscConfig+0x14e>
 80009f8:	e1e2      	b.n	8000dc0 <HAL_RCC_OscConfig+0x514>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 80009fa:	4964      	ldr	r1, [pc, #400]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 80009fc:	680b      	ldr	r3, [r1, #0]
 80009fe:	22f8      	movs	r2, #248	; 0xf8
 8000a00:	4393      	bics	r3, r2
 8000a02:	6922      	ldr	r2, [r4, #16]
 8000a04:	00d2      	lsls	r2, r2, #3
 8000a06:	4313      	orrs	r3, r2
 8000a08:	600b      	str	r3, [r1, #0]
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8000a0a:	6823      	ldr	r3, [r4, #0]
 8000a0c:	071b      	lsls	r3, r3, #28
 8000a0e:	d544      	bpl.n	8000a9a <HAL_RCC_OscConfig+0x1ee>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
    
    /* Check the LSI State */
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8000a10:	69e3      	ldr	r3, [r4, #28]
 8000a12:	2b00      	cmp	r3, #0
 8000a14:	d02e      	beq.n	8000a74 <HAL_RCC_OscConfig+0x1c8>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 8000a16:	4a5d      	ldr	r2, [pc, #372]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000a18:	6a53      	ldr	r3, [r2, #36]	; 0x24
 8000a1a:	2101      	movs	r1, #1
 8000a1c:	430b      	orrs	r3, r1
 8000a1e:	6253      	str	r3, [r2, #36]	; 0x24
      
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8000a20:	f7ff fd70 	bl	8000504 <HAL_GetTick>
 8000a24:	0005      	movs	r5, r0
      
      /* Wait till LSI is ready */  
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8000a26:	4b59      	ldr	r3, [pc, #356]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000a28:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8000a2a:	079b      	lsls	r3, r3, #30
 8000a2c:	d435      	bmi.n	8000a9a <HAL_RCC_OscConfig+0x1ee>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8000a2e:	f7ff fd69 	bl	8000504 <HAL_GetTick>
 8000a32:	1b40      	subs	r0, r0, r5
 8000a34:	2802      	cmp	r0, #2
 8000a36:	d9f6      	bls.n	8000a26 <HAL_RCC_OscConfig+0x17a>
        {
          return HAL_TIMEOUT;
 8000a38:	2003      	movs	r0, #3
 8000a3a:	e1bd      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8000a3c:	4953      	ldr	r1, [pc, #332]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000a3e:	680b      	ldr	r3, [r1, #0]
 8000a40:	22f8      	movs	r2, #248	; 0xf8
 8000a42:	4393      	bics	r3, r2
 8000a44:	6922      	ldr	r2, [r4, #16]
 8000a46:	00d2      	lsls	r2, r2, #3
 8000a48:	4313      	orrs	r3, r2
 8000a4a:	600b      	str	r3, [r1, #0]
 8000a4c:	e7dd      	b.n	8000a0a <HAL_RCC_OscConfig+0x15e>
        __HAL_RCC_HSI_DISABLE();
 8000a4e:	4a4f      	ldr	r2, [pc, #316]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000a50:	6813      	ldr	r3, [r2, #0]
 8000a52:	2101      	movs	r1, #1
 8000a54:	438b      	bics	r3, r1
 8000a56:	6013      	str	r3, [r2, #0]
        tickstart = HAL_GetTick();
 8000a58:	f7ff fd54 	bl	8000504 <HAL_GetTick>
 8000a5c:	0005      	movs	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 8000a5e:	4b4b      	ldr	r3, [pc, #300]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000a60:	681b      	ldr	r3, [r3, #0]
 8000a62:	079b      	lsls	r3, r3, #30
 8000a64:	d5d1      	bpl.n	8000a0a <HAL_RCC_OscConfig+0x15e>
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8000a66:	f7ff fd4d 	bl	8000504 <HAL_GetTick>
 8000a6a:	1b40      	subs	r0, r0, r5
 8000a6c:	2802      	cmp	r0, #2
 8000a6e:	d9f6      	bls.n	8000a5e <HAL_RCC_OscConfig+0x1b2>
            return HAL_TIMEOUT;
 8000a70:	2003      	movs	r0, #3
 8000a72:	e1a1      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 8000a74:	4a45      	ldr	r2, [pc, #276]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000a76:	6a53      	ldr	r3, [r2, #36]	; 0x24
 8000a78:	2101      	movs	r1, #1
 8000a7a:	438b      	bics	r3, r1
 8000a7c:	6253      	str	r3, [r2, #36]	; 0x24
      
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8000a7e:	f7ff fd41 	bl	8000504 <HAL_GetTick>
 8000a82:	0005      	movs	r5, r0
      
      /* Wait till LSI is disabled */  
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8000a84:	4b41      	ldr	r3, [pc, #260]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000a86:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8000a88:	079b      	lsls	r3, r3, #30
 8000a8a:	d506      	bpl.n	8000a9a <HAL_RCC_OscConfig+0x1ee>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8000a8c:	f7ff fd3a 	bl	8000504 <HAL_GetTick>
 8000a90:	1b40      	subs	r0, r0, r5
 8000a92:	2802      	cmp	r0, #2
 8000a94:	d9f6      	bls.n	8000a84 <HAL_RCC_OscConfig+0x1d8>
        {
          return HAL_TIMEOUT;
 8000a96:	2003      	movs	r0, #3
 8000a98:	e18e      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8000a9a:	6823      	ldr	r3, [r4, #0]
 8000a9c:	075b      	lsls	r3, r3, #29
 8000a9e:	d400      	bmi.n	8000aa2 <HAL_RCC_OscConfig+0x1f6>
 8000aa0:	e080      	b.n	8000ba4 <HAL_RCC_OscConfig+0x2f8>
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8000aa2:	4b3a      	ldr	r3, [pc, #232]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000aa4:	69db      	ldr	r3, [r3, #28]
 8000aa6:	00db      	lsls	r3, r3, #3
 8000aa8:	d41d      	bmi.n	8000ae6 <HAL_RCC_OscConfig+0x23a>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8000aaa:	4b38      	ldr	r3, [pc, #224]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000aac:	69da      	ldr	r2, [r3, #28]
 8000aae:	2180      	movs	r1, #128	; 0x80
 8000ab0:	0549      	lsls	r1, r1, #21
 8000ab2:	430a      	orrs	r2, r1
 8000ab4:	61da      	str	r2, [r3, #28]
 8000ab6:	69db      	ldr	r3, [r3, #28]
 8000ab8:	400b      	ands	r3, r1
 8000aba:	9301      	str	r3, [sp, #4]
 8000abc:	9b01      	ldr	r3, [sp, #4]
      pwrclkchanged = SET;
 8000abe:	2501      	movs	r5, #1
    }
    
    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000ac0:	4b35      	ldr	r3, [pc, #212]	; (8000b98 <HAL_RCC_OscConfig+0x2ec>)
 8000ac2:	681b      	ldr	r3, [r3, #0]
 8000ac4:	05db      	lsls	r3, r3, #23
 8000ac6:	d510      	bpl.n	8000aea <HAL_RCC_OscConfig+0x23e>
        }
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000ac8:	68a3      	ldr	r3, [r4, #8]
 8000aca:	2b01      	cmp	r3, #1
 8000acc:	d021      	beq.n	8000b12 <HAL_RCC_OscConfig+0x266>
 8000ace:	2b00      	cmp	r3, #0
 8000ad0:	d136      	bne.n	8000b40 <HAL_RCC_OscConfig+0x294>
 8000ad2:	4b2e      	ldr	r3, [pc, #184]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000ad4:	6a1a      	ldr	r2, [r3, #32]
 8000ad6:	2101      	movs	r1, #1
 8000ad8:	438a      	bics	r2, r1
 8000ada:	621a      	str	r2, [r3, #32]
 8000adc:	6a1a      	ldr	r2, [r3, #32]
 8000ade:	3103      	adds	r1, #3
 8000ae0:	438a      	bics	r2, r1
 8000ae2:	621a      	str	r2, [r3, #32]
 8000ae4:	e01a      	b.n	8000b1c <HAL_RCC_OscConfig+0x270>
    FlagStatus       pwrclkchanged = RESET;
 8000ae6:	2500      	movs	r5, #0
 8000ae8:	e7ea      	b.n	8000ac0 <HAL_RCC_OscConfig+0x214>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8000aea:	4a2b      	ldr	r2, [pc, #172]	; (8000b98 <HAL_RCC_OscConfig+0x2ec>)
 8000aec:	6811      	ldr	r1, [r2, #0]
 8000aee:	2380      	movs	r3, #128	; 0x80
 8000af0:	005b      	lsls	r3, r3, #1
 8000af2:	430b      	orrs	r3, r1
 8000af4:	6013      	str	r3, [r2, #0]
      tickstart = HAL_GetTick();
 8000af6:	f7ff fd05 	bl	8000504 <HAL_GetTick>
 8000afa:	0006      	movs	r6, r0
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000afc:	4b26      	ldr	r3, [pc, #152]	; (8000b98 <HAL_RCC_OscConfig+0x2ec>)
 8000afe:	681b      	ldr	r3, [r3, #0]
 8000b00:	05db      	lsls	r3, r3, #23
 8000b02:	d4e1      	bmi.n	8000ac8 <HAL_RCC_OscConfig+0x21c>
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8000b04:	f7ff fcfe 	bl	8000504 <HAL_GetTick>
 8000b08:	1b80      	subs	r0, r0, r6
 8000b0a:	2864      	cmp	r0, #100	; 0x64
 8000b0c:	d9f6      	bls.n	8000afc <HAL_RCC_OscConfig+0x250>
          return HAL_TIMEOUT;
 8000b0e:	2003      	movs	r0, #3
 8000b10:	e152      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000b12:	4a1e      	ldr	r2, [pc, #120]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000b14:	6a13      	ldr	r3, [r2, #32]
 8000b16:	2101      	movs	r1, #1
 8000b18:	430b      	orrs	r3, r1
 8000b1a:	6213      	str	r3, [r2, #32]
    /* Check the LSE State */
    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 8000b1c:	68a3      	ldr	r3, [r4, #8]
 8000b1e:	2b00      	cmp	r3, #0
 8000b20:	d024      	beq.n	8000b6c <HAL_RCC_OscConfig+0x2c0>
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8000b22:	f7ff fcef 	bl	8000504 <HAL_GetTick>
 8000b26:	0006      	movs	r6, r0
      
      /* Wait till LSE is ready */  
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8000b28:	4b18      	ldr	r3, [pc, #96]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000b2a:	6a1b      	ldr	r3, [r3, #32]
 8000b2c:	079b      	lsls	r3, r3, #30
 8000b2e:	d437      	bmi.n	8000ba0 <HAL_RCC_OscConfig+0x2f4>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000b30:	f7ff fce8 	bl	8000504 <HAL_GetTick>
 8000b34:	1b80      	subs	r0, r0, r6
 8000b36:	4b19      	ldr	r3, [pc, #100]	; (8000b9c <HAL_RCC_OscConfig+0x2f0>)
 8000b38:	4298      	cmp	r0, r3
 8000b3a:	d9f5      	bls.n	8000b28 <HAL_RCC_OscConfig+0x27c>
        {
          return HAL_TIMEOUT;
 8000b3c:	2003      	movs	r0, #3
 8000b3e:	e13b      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000b40:	2b05      	cmp	r3, #5
 8000b42:	d009      	beq.n	8000b58 <HAL_RCC_OscConfig+0x2ac>
 8000b44:	4b11      	ldr	r3, [pc, #68]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000b46:	6a1a      	ldr	r2, [r3, #32]
 8000b48:	2101      	movs	r1, #1
 8000b4a:	438a      	bics	r2, r1
 8000b4c:	621a      	str	r2, [r3, #32]
 8000b4e:	6a1a      	ldr	r2, [r3, #32]
 8000b50:	3103      	adds	r1, #3
 8000b52:	438a      	bics	r2, r1
 8000b54:	621a      	str	r2, [r3, #32]
 8000b56:	e7e1      	b.n	8000b1c <HAL_RCC_OscConfig+0x270>
 8000b58:	4b0c      	ldr	r3, [pc, #48]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000b5a:	6a1a      	ldr	r2, [r3, #32]
 8000b5c:	2104      	movs	r1, #4
 8000b5e:	430a      	orrs	r2, r1
 8000b60:	621a      	str	r2, [r3, #32]
 8000b62:	6a1a      	ldr	r2, [r3, #32]
 8000b64:	3903      	subs	r1, #3
 8000b66:	430a      	orrs	r2, r1
 8000b68:	621a      	str	r2, [r3, #32]
 8000b6a:	e7d7      	b.n	8000b1c <HAL_RCC_OscConfig+0x270>
      }
    }
    else
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8000b6c:	f7ff fcca 	bl	8000504 <HAL_GetTick>
 8000b70:	0006      	movs	r6, r0
      
      /* Wait till LSE is disabled */  
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8000b72:	4b06      	ldr	r3, [pc, #24]	; (8000b8c <HAL_RCC_OscConfig+0x2e0>)
 8000b74:	6a1b      	ldr	r3, [r3, #32]
 8000b76:	079b      	lsls	r3, r3, #30
 8000b78:	d512      	bpl.n	8000ba0 <HAL_RCC_OscConfig+0x2f4>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000b7a:	f7ff fcc3 	bl	8000504 <HAL_GetTick>
 8000b7e:	1b80      	subs	r0, r0, r6
 8000b80:	4b06      	ldr	r3, [pc, #24]	; (8000b9c <HAL_RCC_OscConfig+0x2f0>)
 8000b82:	4298      	cmp	r0, r3
 8000b84:	d9f5      	bls.n	8000b72 <HAL_RCC_OscConfig+0x2c6>
        {
          return HAL_TIMEOUT;
 8000b86:	2003      	movs	r0, #3
 8000b88:	e116      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
 8000b8a:	46c0      	nop			; (mov r8, r8)
 8000b8c:	40021000 	.word	0x40021000
 8000b90:	fffeffff 	.word	0xfffeffff
 8000b94:	fffbffff 	.word	0xfffbffff
 8000b98:	40007000 	.word	0x40007000
 8000b9c:	00001388 	.word	0x00001388
        }
      }
    }

    /* Require to disable power clock if necessary */
    if(pwrclkchanged == SET)
 8000ba0:	2d01      	cmp	r5, #1
 8000ba2:	d039      	beq.n	8000c18 <HAL_RCC_OscConfig+0x36c>
      __HAL_RCC_PWR_CLK_DISABLE();
    }
  }

  /*----------------------------- HSI14 Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
 8000ba4:	6823      	ldr	r3, [r4, #0]
 8000ba6:	06db      	lsls	r3, r3, #27
 8000ba8:	d510      	bpl.n	8000bcc <HAL_RCC_OscConfig+0x320>
    /* Check the parameters */
    assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));

    /* Check the HSI14 State */
    if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
 8000baa:	6963      	ldr	r3, [r4, #20]
 8000bac:	2b01      	cmp	r3, #1
 8000bae:	d039      	beq.n	8000c24 <HAL_RCC_OscConfig+0x378>
      } 

      /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
      __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
    }
    else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
 8000bb0:	3305      	adds	r3, #5
 8000bb2:	d157      	bne.n	8000c64 <HAL_RCC_OscConfig+0x3b8>
    {
      /* Enable ADC control of the Internal High Speed oscillator HSI14 */
      __HAL_RCC_HSI14ADC_ENABLE();
 8000bb4:	4a89      	ldr	r2, [pc, #548]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000bb6:	6b53      	ldr	r3, [r2, #52]	; 0x34
 8000bb8:	2104      	movs	r1, #4
 8000bba:	438b      	bics	r3, r1
 8000bbc:	6353      	str	r3, [r2, #52]	; 0x34

      /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
      __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
 8000bbe:	6b53      	ldr	r3, [r2, #52]	; 0x34
 8000bc0:	31f4      	adds	r1, #244	; 0xf4
 8000bc2:	438b      	bics	r3, r1
 8000bc4:	69a1      	ldr	r1, [r4, #24]
 8000bc6:	00c9      	lsls	r1, r1, #3
 8000bc8:	430b      	orrs	r3, r1
 8000bca:	6353      	str	r3, [r2, #52]	; 0x34
    }
  }

#if defined(RCC_HSI48_SUPPORT)
  /*----------------------------- HSI48 Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
 8000bcc:	6823      	ldr	r3, [r4, #0]
 8000bce:	069b      	lsls	r3, r3, #26
 8000bd0:	d56e      	bpl.n	8000cb0 <HAL_RCC_OscConfig+0x404>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));

    /* When the HSI48 is used as system clock it is not allowed to be disabled */
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) ||
 8000bd2:	4b82      	ldr	r3, [pc, #520]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000bd4:	685a      	ldr	r2, [r3, #4]
 8000bd6:	230c      	movs	r3, #12
 8000bd8:	4013      	ands	r3, r2
 8000bda:	2b0c      	cmp	r3, #12
 8000bdc:	d060      	beq.n	8000ca0 <HAL_RCC_OscConfig+0x3f4>
       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))
 8000bde:	4b7f      	ldr	r3, [pc, #508]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000be0:	685a      	ldr	r2, [r3, #4]
 8000be2:	230c      	movs	r3, #12
 8000be4:	4013      	ands	r3, r2
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) ||
 8000be6:	2b08      	cmp	r3, #8
 8000be8:	d053      	beq.n	8000c92 <HAL_RCC_OscConfig+0x3e6>
      }
    }
    else
    {
      /* Check the HSI48 State */
      if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
 8000bea:	6a23      	ldr	r3, [r4, #32]
 8000bec:	2b00      	cmp	r3, #0
 8000bee:	d07e      	beq.n	8000cee <HAL_RCC_OscConfig+0x442>
      {
        /* Enable the Internal High Speed oscillator (HSI48). */
        __HAL_RCC_HSI48_ENABLE();
 8000bf0:	4a7a      	ldr	r2, [pc, #488]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000bf2:	6b51      	ldr	r1, [r2, #52]	; 0x34
 8000bf4:	2380      	movs	r3, #128	; 0x80
 8000bf6:	025b      	lsls	r3, r3, #9
 8000bf8:	430b      	orrs	r3, r1
 8000bfa:	6353      	str	r3, [r2, #52]	; 0x34

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000bfc:	f7ff fc82 	bl	8000504 <HAL_GetTick>
 8000c00:	0005      	movs	r5, r0
      
        /* Wait till HSI48 is ready */  
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
 8000c02:	4b76      	ldr	r3, [pc, #472]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000c04:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8000c06:	039b      	lsls	r3, r3, #14
 8000c08:	d452      	bmi.n	8000cb0 <HAL_RCC_OscConfig+0x404>
        {
          if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
 8000c0a:	f7ff fc7b 	bl	8000504 <HAL_GetTick>
 8000c0e:	1b40      	subs	r0, r0, r5
 8000c10:	2802      	cmp	r0, #2
 8000c12:	d9f6      	bls.n	8000c02 <HAL_RCC_OscConfig+0x356>
          {
            return HAL_TIMEOUT;
 8000c14:	2003      	movs	r0, #3
 8000c16:	e0cf      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
      __HAL_RCC_PWR_CLK_DISABLE();
 8000c18:	4a70      	ldr	r2, [pc, #448]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000c1a:	69d3      	ldr	r3, [r2, #28]
 8000c1c:	4970      	ldr	r1, [pc, #448]	; (8000de0 <HAL_RCC_OscConfig+0x534>)
 8000c1e:	400b      	ands	r3, r1
 8000c20:	61d3      	str	r3, [r2, #28]
 8000c22:	e7bf      	b.n	8000ba4 <HAL_RCC_OscConfig+0x2f8>
      __HAL_RCC_HSI14ADC_DISABLE();
 8000c24:	4b6d      	ldr	r3, [pc, #436]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000c26:	6b5a      	ldr	r2, [r3, #52]	; 0x34
 8000c28:	2104      	movs	r1, #4
 8000c2a:	430a      	orrs	r2, r1
 8000c2c:	635a      	str	r2, [r3, #52]	; 0x34
      __HAL_RCC_HSI14_ENABLE();
 8000c2e:	6b5a      	ldr	r2, [r3, #52]	; 0x34
 8000c30:	3903      	subs	r1, #3
 8000c32:	430a      	orrs	r2, r1
 8000c34:	635a      	str	r2, [r3, #52]	; 0x34
      tickstart = HAL_GetTick();
 8000c36:	f7ff fc65 	bl	8000504 <HAL_GetTick>
 8000c3a:	0005      	movs	r5, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
 8000c3c:	4b67      	ldr	r3, [pc, #412]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000c3e:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8000c40:	079b      	lsls	r3, r3, #30
 8000c42:	d406      	bmi.n	8000c52 <HAL_RCC_OscConfig+0x3a6>
        if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
 8000c44:	f7ff fc5e 	bl	8000504 <HAL_GetTick>
 8000c48:	1b40      	subs	r0, r0, r5
 8000c4a:	2802      	cmp	r0, #2
 8000c4c:	d9f6      	bls.n	8000c3c <HAL_RCC_OscConfig+0x390>
          return HAL_TIMEOUT;
 8000c4e:	2003      	movs	r0, #3
 8000c50:	e0b2      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
      __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
 8000c52:	4962      	ldr	r1, [pc, #392]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000c54:	6b4b      	ldr	r3, [r1, #52]	; 0x34
 8000c56:	22f8      	movs	r2, #248	; 0xf8
 8000c58:	4393      	bics	r3, r2
 8000c5a:	69a2      	ldr	r2, [r4, #24]
 8000c5c:	00d2      	lsls	r2, r2, #3
 8000c5e:	4313      	orrs	r3, r2
 8000c60:	634b      	str	r3, [r1, #52]	; 0x34
 8000c62:	e7b3      	b.n	8000bcc <HAL_RCC_OscConfig+0x320>
      __HAL_RCC_HSI14ADC_DISABLE();
 8000c64:	4b5d      	ldr	r3, [pc, #372]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000c66:	6b5a      	ldr	r2, [r3, #52]	; 0x34
 8000c68:	2104      	movs	r1, #4
 8000c6a:	430a      	orrs	r2, r1
 8000c6c:	635a      	str	r2, [r3, #52]	; 0x34
      __HAL_RCC_HSI14_DISABLE();
 8000c6e:	6b5a      	ldr	r2, [r3, #52]	; 0x34
 8000c70:	3903      	subs	r1, #3
 8000c72:	438a      	bics	r2, r1
 8000c74:	635a      	str	r2, [r3, #52]	; 0x34
      tickstart = HAL_GetTick();
 8000c76:	f7ff fc45 	bl	8000504 <HAL_GetTick>
 8000c7a:	0005      	movs	r5, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
 8000c7c:	4b57      	ldr	r3, [pc, #348]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000c7e:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8000c80:	079b      	lsls	r3, r3, #30
 8000c82:	d5a3      	bpl.n	8000bcc <HAL_RCC_OscConfig+0x320>
        if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
 8000c84:	f7ff fc3e 	bl	8000504 <HAL_GetTick>
 8000c88:	1b40      	subs	r0, r0, r5
 8000c8a:	2802      	cmp	r0, #2
 8000c8c:	d9f6      	bls.n	8000c7c <HAL_RCC_OscConfig+0x3d0>
          return HAL_TIMEOUT;
 8000c8e:	2003      	movs	r0, #3
 8000c90:	e092      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
       ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))
 8000c92:	4b52      	ldr	r3, [pc, #328]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000c94:	685b      	ldr	r3, [r3, #4]
 8000c96:	22c0      	movs	r2, #192	; 0xc0
 8000c98:	0252      	lsls	r2, r2, #9
 8000c9a:	4013      	ands	r3, r2
 8000c9c:	4293      	cmp	r3, r2
 8000c9e:	d1a4      	bne.n	8000bea <HAL_RCC_OscConfig+0x33e>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON))
 8000ca0:	4b4e      	ldr	r3, [pc, #312]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000ca2:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8000ca4:	039b      	lsls	r3, r3, #14
 8000ca6:	d503      	bpl.n	8000cb0 <HAL_RCC_OscConfig+0x404>
 8000ca8:	6a23      	ldr	r3, [r4, #32]
 8000caa:	2b01      	cmp	r3, #1
 8000cac:	d000      	beq.n	8000cb0 <HAL_RCC_OscConfig+0x404>
 8000cae:	e089      	b.n	8000dc4 <HAL_RCC_OscConfig+0x518>
#endif /* RCC_HSI48_SUPPORT */
       
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8000cb0:	6a63      	ldr	r3, [r4, #36]	; 0x24
 8000cb2:	2b00      	cmp	r3, #0
 8000cb4:	d100      	bne.n	8000cb8 <HAL_RCC_OscConfig+0x40c>
 8000cb6:	e087      	b.n	8000dc8 <HAL_RCC_OscConfig+0x51c>
  {
    /* Check if the PLL is used as system clock or not */
    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8000cb8:	4a48      	ldr	r2, [pc, #288]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000cba:	6851      	ldr	r1, [r2, #4]
 8000cbc:	220c      	movs	r2, #12
 8000cbe:	400a      	ands	r2, r1
 8000cc0:	2a08      	cmp	r2, #8
 8000cc2:	d060      	beq.n	8000d86 <HAL_RCC_OscConfig+0x4da>
    { 
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8000cc4:	2b02      	cmp	r3, #2
 8000cc6:	d025      	beq.n	8000d14 <HAL_RCC_OscConfig+0x468>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8000cc8:	4a44      	ldr	r2, [pc, #272]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000cca:	6813      	ldr	r3, [r2, #0]
 8000ccc:	4945      	ldr	r1, [pc, #276]	; (8000de4 <HAL_RCC_OscConfig+0x538>)
 8000cce:	400b      	ands	r3, r1
 8000cd0:	6013      	str	r3, [r2, #0]
 
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000cd2:	f7ff fc17 	bl	8000504 <HAL_GetTick>
 8000cd6:	0004      	movs	r4, r0
        
        /* Wait till PLL is disabled */  
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8000cd8:	4b40      	ldr	r3, [pc, #256]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000cda:	681b      	ldr	r3, [r3, #0]
 8000cdc:	019b      	lsls	r3, r3, #6
 8000cde:	d550      	bpl.n	8000d82 <HAL_RCC_OscConfig+0x4d6>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000ce0:	f7ff fc10 	bl	8000504 <HAL_GetTick>
 8000ce4:	1b00      	subs	r0, r0, r4
 8000ce6:	2802      	cmp	r0, #2
 8000ce8:	d9f6      	bls.n	8000cd8 <HAL_RCC_OscConfig+0x42c>
          {
            return HAL_TIMEOUT;
 8000cea:	2003      	movs	r0, #3
 8000cec:	e064      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
        __HAL_RCC_HSI48_DISABLE();
 8000cee:	4a3b      	ldr	r2, [pc, #236]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000cf0:	6b53      	ldr	r3, [r2, #52]	; 0x34
 8000cf2:	493d      	ldr	r1, [pc, #244]	; (8000de8 <HAL_RCC_OscConfig+0x53c>)
 8000cf4:	400b      	ands	r3, r1
 8000cf6:	6353      	str	r3, [r2, #52]	; 0x34
        tickstart = HAL_GetTick();
 8000cf8:	f7ff fc04 	bl	8000504 <HAL_GetTick>
 8000cfc:	0005      	movs	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
 8000cfe:	4b37      	ldr	r3, [pc, #220]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000d00:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8000d02:	039b      	lsls	r3, r3, #14
 8000d04:	d5d4      	bpl.n	8000cb0 <HAL_RCC_OscConfig+0x404>
          if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
 8000d06:	f7ff fbfd 	bl	8000504 <HAL_GetTick>
 8000d0a:	1b40      	subs	r0, r0, r5
 8000d0c:	2802      	cmp	r0, #2
 8000d0e:	d9f6      	bls.n	8000cfe <HAL_RCC_OscConfig+0x452>
            return HAL_TIMEOUT;
 8000d10:	2003      	movs	r0, #3
 8000d12:	e051      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
        __HAL_RCC_PLL_DISABLE();
 8000d14:	4a31      	ldr	r2, [pc, #196]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000d16:	6813      	ldr	r3, [r2, #0]
 8000d18:	4932      	ldr	r1, [pc, #200]	; (8000de4 <HAL_RCC_OscConfig+0x538>)
 8000d1a:	400b      	ands	r3, r1
 8000d1c:	6013      	str	r3, [r2, #0]
        tickstart = HAL_GetTick();
 8000d1e:	f7ff fbf1 	bl	8000504 <HAL_GetTick>
 8000d22:	0005      	movs	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8000d24:	4b2d      	ldr	r3, [pc, #180]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000d26:	681b      	ldr	r3, [r3, #0]
 8000d28:	019b      	lsls	r3, r3, #6
 8000d2a:	d506      	bpl.n	8000d3a <HAL_RCC_OscConfig+0x48e>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000d2c:	f7ff fbea 	bl	8000504 <HAL_GetTick>
 8000d30:	1b40      	subs	r0, r0, r5
 8000d32:	2802      	cmp	r0, #2
 8000d34:	d9f6      	bls.n	8000d24 <HAL_RCC_OscConfig+0x478>
            return HAL_TIMEOUT;
 8000d36:	2003      	movs	r0, #3
 8000d38:	e03e      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8000d3a:	4b28      	ldr	r3, [pc, #160]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000d3c:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8000d3e:	210f      	movs	r1, #15
 8000d40:	438a      	bics	r2, r1
 8000d42:	6b21      	ldr	r1, [r4, #48]	; 0x30
 8000d44:	430a      	orrs	r2, r1
 8000d46:	62da      	str	r2, [r3, #44]	; 0x2c
 8000d48:	685a      	ldr	r2, [r3, #4]
 8000d4a:	4928      	ldr	r1, [pc, #160]	; (8000dec <HAL_RCC_OscConfig+0x540>)
 8000d4c:	400a      	ands	r2, r1
 8000d4e:	6ae1      	ldr	r1, [r4, #44]	; 0x2c
 8000d50:	6aa0      	ldr	r0, [r4, #40]	; 0x28
 8000d52:	4301      	orrs	r1, r0
 8000d54:	430a      	orrs	r2, r1
 8000d56:	605a      	str	r2, [r3, #4]
        __HAL_RCC_PLL_ENABLE();
 8000d58:	6819      	ldr	r1, [r3, #0]
 8000d5a:	2280      	movs	r2, #128	; 0x80
 8000d5c:	0452      	lsls	r2, r2, #17
 8000d5e:	430a      	orrs	r2, r1
 8000d60:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8000d62:	f7ff fbcf 	bl	8000504 <HAL_GetTick>
 8000d66:	0004      	movs	r4, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 8000d68:	4b1c      	ldr	r3, [pc, #112]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000d6a:	681b      	ldr	r3, [r3, #0]
 8000d6c:	019b      	lsls	r3, r3, #6
 8000d6e:	d406      	bmi.n	8000d7e <HAL_RCC_OscConfig+0x4d2>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000d70:	f7ff fbc8 	bl	8000504 <HAL_GetTick>
 8000d74:	1b00      	subs	r0, r0, r4
 8000d76:	2802      	cmp	r0, #2
 8000d78:	d9f6      	bls.n	8000d68 <HAL_RCC_OscConfig+0x4bc>
            return HAL_TIMEOUT;
 8000d7a:	2003      	movs	r0, #3
 8000d7c:	e01c      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
        }
      }
    }
  }

  return HAL_OK;
 8000d7e:	2000      	movs	r0, #0
 8000d80:	e01a      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
 8000d82:	2000      	movs	r0, #0
 8000d84:	e018      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 8000d86:	2b01      	cmp	r3, #1
 8000d88:	d020      	beq.n	8000dcc <HAL_RCC_OscConfig+0x520>
        pll_config  = RCC->CFGR;
 8000d8a:	4b14      	ldr	r3, [pc, #80]	; (8000ddc <HAL_RCC_OscConfig+0x530>)
 8000d8c:	685a      	ldr	r2, [r3, #4]
        pll_config2 = RCC->CFGR2;
 8000d8e:	6ad8      	ldr	r0, [r3, #44]	; 0x2c
        if((READ_BIT(pll_config,  RCC_CFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
 8000d90:	23c0      	movs	r3, #192	; 0xc0
 8000d92:	025b      	lsls	r3, r3, #9
 8000d94:	4013      	ands	r3, r2
 8000d96:	6aa1      	ldr	r1, [r4, #40]	; 0x28
 8000d98:	428b      	cmp	r3, r1
 8000d9a:	d119      	bne.n	8000dd0 <HAL_RCC_OscConfig+0x524>
           (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)    ||
 8000d9c:	230f      	movs	r3, #15
 8000d9e:	4003      	ands	r3, r0
 8000da0:	6b21      	ldr	r1, [r4, #48]	; 0x30
        if((READ_BIT(pll_config,  RCC_CFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
 8000da2:	428b      	cmp	r3, r1
 8000da4:	d116      	bne.n	8000dd4 <HAL_RCC_OscConfig+0x528>
           (READ_BIT(pll_config,  RCC_CFGR_PLLMUL)  != RCC_OscInitStruct->PLL.PLLMUL))
 8000da6:	23f0      	movs	r3, #240	; 0xf0
 8000da8:	039b      	lsls	r3, r3, #14
 8000daa:	401a      	ands	r2, r3
 8000dac:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
           (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)    ||
 8000dae:	429a      	cmp	r2, r3
 8000db0:	d112      	bne.n	8000dd8 <HAL_RCC_OscConfig+0x52c>
  return HAL_OK;
 8000db2:	2000      	movs	r0, #0
 8000db4:	e000      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
    return HAL_ERROR;
 8000db6:	2001      	movs	r0, #1
}
 8000db8:	b002      	add	sp, #8
 8000dba:	bd70      	pop	{r4, r5, r6, pc}
        return HAL_ERROR;
 8000dbc:	2001      	movs	r0, #1
 8000dbe:	e7fb      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
        return HAL_ERROR;
 8000dc0:	2001      	movs	r0, #1
 8000dc2:	e7f9      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
        return HAL_ERROR;
 8000dc4:	2001      	movs	r0, #1
 8000dc6:	e7f7      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
  return HAL_OK;
 8000dc8:	2000      	movs	r0, #0
 8000dca:	e7f5      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
        return HAL_ERROR;
 8000dcc:	2001      	movs	r0, #1
 8000dce:	e7f3      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
          return HAL_ERROR;
 8000dd0:	2001      	movs	r0, #1
 8000dd2:	e7f1      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
 8000dd4:	2001      	movs	r0, #1
 8000dd6:	e7ef      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
 8000dd8:	2001      	movs	r0, #1
 8000dda:	e7ed      	b.n	8000db8 <HAL_RCC_OscConfig+0x50c>
 8000ddc:	40021000 	.word	0x40021000
 8000de0:	efffffff 	.word	0xefffffff
 8000de4:	feffffff 	.word	0xfeffffff
 8000de8:	fffeffff 	.word	0xfffeffff
 8000dec:	ffc27fff 	.word	0xffc27fff

08000df0 <HAL_RCC_GetSysClockFreq>:
  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
  *         
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8000df0:	b510      	push	{r4, lr}
                                                   9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};

  uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
  uint32_t sysclockfreq = 0U;
  
  tmpreg = RCC->CFGR;
 8000df2:	4b18      	ldr	r3, [pc, #96]	; (8000e54 <HAL_RCC_GetSysClockFreq+0x64>)
 8000df4:	685a      	ldr	r2, [r3, #4]
  
  /* Get SYSCLK source -------------------------------------------------------*/
  switch (tmpreg & RCC_CFGR_SWS)
 8000df6:	230c      	movs	r3, #12
 8000df8:	4013      	ands	r3, r2
 8000dfa:	2b08      	cmp	r3, #8
 8000dfc:	d003      	beq.n	8000e06 <HAL_RCC_GetSysClockFreq+0x16>
 8000dfe:	2b0c      	cmp	r3, #12
 8000e00:	d125      	bne.n	8000e4e <HAL_RCC_GetSysClockFreq+0x5e>
      break;
    }
#if defined(RCC_CFGR_SWS_HSI48)
    case RCC_SYSCLKSOURCE_STATUS_HSI48:    /* HSI48 used as system clock source */
    {
      sysclockfreq = HSI48_VALUE;
 8000e02:	4815      	ldr	r0, [pc, #84]	; (8000e58 <HAL_RCC_GetSysClockFreq+0x68>)
      sysclockfreq = HSI_VALUE;
      break;
    }
  }
  return sysclockfreq;
}
 8000e04:	bd10      	pop	{r4, pc}
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
 8000e06:	0c91      	lsrs	r1, r2, #18
 8000e08:	230f      	movs	r3, #15
 8000e0a:	4019      	ands	r1, r3
 8000e0c:	4813      	ldr	r0, [pc, #76]	; (8000e5c <HAL_RCC_GetSysClockFreq+0x6c>)
 8000e0e:	5c44      	ldrb	r4, [r0, r1]
      prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
 8000e10:	4910      	ldr	r1, [pc, #64]	; (8000e54 <HAL_RCC_GetSysClockFreq+0x64>)
 8000e12:	6ac9      	ldr	r1, [r1, #44]	; 0x2c
 8000e14:	400b      	ands	r3, r1
 8000e16:	4912      	ldr	r1, [pc, #72]	; (8000e60 <HAL_RCC_GetSysClockFreq+0x70>)
 8000e18:	5cc9      	ldrb	r1, [r1, r3]
      if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
 8000e1a:	23c0      	movs	r3, #192	; 0xc0
 8000e1c:	025b      	lsls	r3, r3, #9
 8000e1e:	401a      	ands	r2, r3
 8000e20:	2380      	movs	r3, #128	; 0x80
 8000e22:	025b      	lsls	r3, r3, #9
 8000e24:	429a      	cmp	r2, r3
 8000e26:	d008      	beq.n	8000e3a <HAL_RCC_GetSysClockFreq+0x4a>
      else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48)
 8000e28:	23c0      	movs	r3, #192	; 0xc0
 8000e2a:	025b      	lsls	r3, r3, #9
 8000e2c:	429a      	cmp	r2, r3
 8000e2e:	d009      	beq.n	8000e44 <HAL_RCC_GetSysClockFreq+0x54>
        pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
 8000e30:	480c      	ldr	r0, [pc, #48]	; (8000e64 <HAL_RCC_GetSysClockFreq+0x74>)
 8000e32:	f7ff f945 	bl	80000c0 <__udivsi3>
 8000e36:	4360      	muls	r0, r4
 8000e38:	e7e4      	b.n	8000e04 <HAL_RCC_GetSysClockFreq+0x14>
        pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
 8000e3a:	480a      	ldr	r0, [pc, #40]	; (8000e64 <HAL_RCC_GetSysClockFreq+0x74>)
 8000e3c:	f7ff f940 	bl	80000c0 <__udivsi3>
 8000e40:	4360      	muls	r0, r4
 8000e42:	e7df      	b.n	8000e04 <HAL_RCC_GetSysClockFreq+0x14>
        pllclk = (uint32_t)((uint64_t) HSI48_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
 8000e44:	4804      	ldr	r0, [pc, #16]	; (8000e58 <HAL_RCC_GetSysClockFreq+0x68>)
 8000e46:	f7ff f93b 	bl	80000c0 <__udivsi3>
 8000e4a:	4360      	muls	r0, r4
 8000e4c:	e7da      	b.n	8000e04 <HAL_RCC_GetSysClockFreq+0x14>
  switch (tmpreg & RCC_CFGR_SWS)
 8000e4e:	4805      	ldr	r0, [pc, #20]	; (8000e64 <HAL_RCC_GetSysClockFreq+0x74>)
  return sysclockfreq;
 8000e50:	e7d8      	b.n	8000e04 <HAL_RCC_GetSysClockFreq+0x14>
 8000e52:	46c0      	nop			; (mov r8, r8)
 8000e54:	40021000 	.word	0x40021000
 8000e58:	02dc6c00 	.word	0x02dc6c00
 8000e5c:	080016bc 	.word	0x080016bc
 8000e60:	080016ac 	.word	0x080016ac
 8000e64:	007a1200 	.word	0x007a1200

08000e68 <HAL_RCC_ClockConfig>:
{
 8000e68:	b570      	push	{r4, r5, r6, lr}
 8000e6a:	0004      	movs	r4, r0
 8000e6c:	000d      	movs	r5, r1
  if(RCC_ClkInitStruct == NULL)
 8000e6e:	2800      	cmp	r0, #0
 8000e70:	d100      	bne.n	8000e74 <HAL_RCC_ClockConfig+0xc>
 8000e72:	e086      	b.n	8000f82 <HAL_RCC_ClockConfig+0x11a>
  if(FLatency > __HAL_FLASH_GET_LATENCY())
 8000e74:	4b47      	ldr	r3, [pc, #284]	; (8000f94 <HAL_RCC_ClockConfig+0x12c>)
 8000e76:	681a      	ldr	r2, [r3, #0]
 8000e78:	2301      	movs	r3, #1
 8000e7a:	4013      	ands	r3, r2
 8000e7c:	428b      	cmp	r3, r1
 8000e7e:	d20a      	bcs.n	8000e96 <HAL_RCC_ClockConfig+0x2e>
    __HAL_FLASH_SET_LATENCY(FLatency);
 8000e80:	4944      	ldr	r1, [pc, #272]	; (8000f94 <HAL_RCC_ClockConfig+0x12c>)
 8000e82:	680b      	ldr	r3, [r1, #0]
 8000e84:	2201      	movs	r2, #1
 8000e86:	4393      	bics	r3, r2
 8000e88:	432b      	orrs	r3, r5
 8000e8a:	600b      	str	r3, [r1, #0]
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8000e8c:	680b      	ldr	r3, [r1, #0]
 8000e8e:	401a      	ands	r2, r3
 8000e90:	42aa      	cmp	r2, r5
 8000e92:	d000      	beq.n	8000e96 <HAL_RCC_ClockConfig+0x2e>
 8000e94:	e077      	b.n	8000f86 <HAL_RCC_ClockConfig+0x11e>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8000e96:	6823      	ldr	r3, [r4, #0]
 8000e98:	079a      	lsls	r2, r3, #30
 8000e9a:	d50e      	bpl.n	8000eba <HAL_RCC_ClockConfig+0x52>
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8000e9c:	075b      	lsls	r3, r3, #29
 8000e9e:	d505      	bpl.n	8000eac <HAL_RCC_ClockConfig+0x44>
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
 8000ea0:	4a3d      	ldr	r2, [pc, #244]	; (8000f98 <HAL_RCC_ClockConfig+0x130>)
 8000ea2:	6851      	ldr	r1, [r2, #4]
 8000ea4:	23e0      	movs	r3, #224	; 0xe0
 8000ea6:	00db      	lsls	r3, r3, #3
 8000ea8:	430b      	orrs	r3, r1
 8000eaa:	6053      	str	r3, [r2, #4]
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8000eac:	4a3a      	ldr	r2, [pc, #232]	; (8000f98 <HAL_RCC_ClockConfig+0x130>)
 8000eae:	6853      	ldr	r3, [r2, #4]
 8000eb0:	21f0      	movs	r1, #240	; 0xf0
 8000eb2:	438b      	bics	r3, r1
 8000eb4:	68a1      	ldr	r1, [r4, #8]
 8000eb6:	430b      	orrs	r3, r1
 8000eb8:	6053      	str	r3, [r2, #4]
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8000eba:	6823      	ldr	r3, [r4, #0]
 8000ebc:	07db      	lsls	r3, r3, #31
 8000ebe:	d535      	bpl.n	8000f2c <HAL_RCC_ClockConfig+0xc4>
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8000ec0:	6863      	ldr	r3, [r4, #4]
 8000ec2:	2b01      	cmp	r3, #1
 8000ec4:	d009      	beq.n	8000eda <HAL_RCC_ClockConfig+0x72>
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 8000ec6:	2b02      	cmp	r3, #2
 8000ec8:	d024      	beq.n	8000f14 <HAL_RCC_ClockConfig+0xac>
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
 8000eca:	2b03      	cmp	r3, #3
 8000ecc:	d028      	beq.n	8000f20 <HAL_RCC_ClockConfig+0xb8>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8000ece:	4a32      	ldr	r2, [pc, #200]	; (8000f98 <HAL_RCC_ClockConfig+0x130>)
 8000ed0:	6812      	ldr	r2, [r2, #0]
 8000ed2:	0792      	lsls	r2, r2, #30
 8000ed4:	d405      	bmi.n	8000ee2 <HAL_RCC_ClockConfig+0x7a>
        return HAL_ERROR;
 8000ed6:	2001      	movs	r0, #1
 8000ed8:	e052      	b.n	8000f80 <HAL_RCC_ClockConfig+0x118>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8000eda:	4a2f      	ldr	r2, [pc, #188]	; (8000f98 <HAL_RCC_ClockConfig+0x130>)
 8000edc:	6812      	ldr	r2, [r2, #0]
 8000ede:	0392      	lsls	r2, r2, #14
 8000ee0:	d553      	bpl.n	8000f8a <HAL_RCC_ClockConfig+0x122>
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 8000ee2:	492d      	ldr	r1, [pc, #180]	; (8000f98 <HAL_RCC_ClockConfig+0x130>)
 8000ee4:	684a      	ldr	r2, [r1, #4]
 8000ee6:	2003      	movs	r0, #3
 8000ee8:	4382      	bics	r2, r0
 8000eea:	4313      	orrs	r3, r2
 8000eec:	604b      	str	r3, [r1, #4]
    tickstart = HAL_GetTick();
 8000eee:	f7ff fb09 	bl	8000504 <HAL_GetTick>
 8000ef2:	0006      	movs	r6, r0
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8000ef4:	4b28      	ldr	r3, [pc, #160]	; (8000f98 <HAL_RCC_ClockConfig+0x130>)
 8000ef6:	685b      	ldr	r3, [r3, #4]
 8000ef8:	220c      	movs	r2, #12
 8000efa:	401a      	ands	r2, r3
 8000efc:	6863      	ldr	r3, [r4, #4]
 8000efe:	009b      	lsls	r3, r3, #2
 8000f00:	429a      	cmp	r2, r3
 8000f02:	d013      	beq.n	8000f2c <HAL_RCC_ClockConfig+0xc4>
      if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8000f04:	f7ff fafe 	bl	8000504 <HAL_GetTick>
 8000f08:	1b80      	subs	r0, r0, r6
 8000f0a:	4b24      	ldr	r3, [pc, #144]	; (8000f9c <HAL_RCC_ClockConfig+0x134>)
 8000f0c:	4298      	cmp	r0, r3
 8000f0e:	d9f1      	bls.n	8000ef4 <HAL_RCC_ClockConfig+0x8c>
        return HAL_TIMEOUT;
 8000f10:	2003      	movs	r0, #3
 8000f12:	e035      	b.n	8000f80 <HAL_RCC_ClockConfig+0x118>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8000f14:	4a20      	ldr	r2, [pc, #128]	; (8000f98 <HAL_RCC_ClockConfig+0x130>)
 8000f16:	6812      	ldr	r2, [r2, #0]
 8000f18:	0192      	lsls	r2, r2, #6
 8000f1a:	d4e2      	bmi.n	8000ee2 <HAL_RCC_ClockConfig+0x7a>
        return HAL_ERROR;
 8000f1c:	2001      	movs	r0, #1
 8000f1e:	e02f      	b.n	8000f80 <HAL_RCC_ClockConfig+0x118>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
 8000f20:	4a1d      	ldr	r2, [pc, #116]	; (8000f98 <HAL_RCC_ClockConfig+0x130>)
 8000f22:	6b52      	ldr	r2, [r2, #52]	; 0x34
 8000f24:	0392      	lsls	r2, r2, #14
 8000f26:	d4dc      	bmi.n	8000ee2 <HAL_RCC_ClockConfig+0x7a>
        return HAL_ERROR;
 8000f28:	2001      	movs	r0, #1
 8000f2a:	e029      	b.n	8000f80 <HAL_RCC_ClockConfig+0x118>
  if(FLatency < __HAL_FLASH_GET_LATENCY())
 8000f2c:	4b19      	ldr	r3, [pc, #100]	; (8000f94 <HAL_RCC_ClockConfig+0x12c>)
 8000f2e:	681a      	ldr	r2, [r3, #0]
 8000f30:	2301      	movs	r3, #1
 8000f32:	4013      	ands	r3, r2
 8000f34:	42ab      	cmp	r3, r5
 8000f36:	d909      	bls.n	8000f4c <HAL_RCC_ClockConfig+0xe4>
    __HAL_FLASH_SET_LATENCY(FLatency);
 8000f38:	4916      	ldr	r1, [pc, #88]	; (8000f94 <HAL_RCC_ClockConfig+0x12c>)
 8000f3a:	680b      	ldr	r3, [r1, #0]
 8000f3c:	2201      	movs	r2, #1
 8000f3e:	4393      	bics	r3, r2
 8000f40:	432b      	orrs	r3, r5
 8000f42:	600b      	str	r3, [r1, #0]
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8000f44:	680b      	ldr	r3, [r1, #0]
 8000f46:	401a      	ands	r2, r3
 8000f48:	42aa      	cmp	r2, r5
 8000f4a:	d120      	bne.n	8000f8e <HAL_RCC_ClockConfig+0x126>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8000f4c:	6823      	ldr	r3, [r4, #0]
 8000f4e:	075b      	lsls	r3, r3, #29
 8000f50:	d506      	bpl.n	8000f60 <HAL_RCC_ClockConfig+0xf8>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
 8000f52:	4a11      	ldr	r2, [pc, #68]	; (8000f98 <HAL_RCC_ClockConfig+0x130>)
 8000f54:	6853      	ldr	r3, [r2, #4]
 8000f56:	4912      	ldr	r1, [pc, #72]	; (8000fa0 <HAL_RCC_ClockConfig+0x138>)
 8000f58:	400b      	ands	r3, r1
 8000f5a:	68e1      	ldr	r1, [r4, #12]
 8000f5c:	430b      	orrs	r3, r1
 8000f5e:	6053      	str	r3, [r2, #4]
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
 8000f60:	f7ff ff46 	bl	8000df0 <HAL_RCC_GetSysClockFreq>
 8000f64:	4b0c      	ldr	r3, [pc, #48]	; (8000f98 <HAL_RCC_ClockConfig+0x130>)
 8000f66:	685a      	ldr	r2, [r3, #4]
 8000f68:	0912      	lsrs	r2, r2, #4
 8000f6a:	230f      	movs	r3, #15
 8000f6c:	4013      	ands	r3, r2
 8000f6e:	4a0d      	ldr	r2, [pc, #52]	; (8000fa4 <HAL_RCC_ClockConfig+0x13c>)
 8000f70:	5cd3      	ldrb	r3, [r2, r3]
 8000f72:	40d8      	lsrs	r0, r3
 8000f74:	4b0c      	ldr	r3, [pc, #48]	; (8000fa8 <HAL_RCC_ClockConfig+0x140>)
 8000f76:	6018      	str	r0, [r3, #0]
  HAL_InitTick (TICK_INT_PRIORITY);
 8000f78:	2003      	movs	r0, #3
 8000f7a:	f7ff fa7f 	bl	800047c <HAL_InitTick>
  return HAL_OK;
 8000f7e:	2000      	movs	r0, #0
}
 8000f80:	bd70      	pop	{r4, r5, r6, pc}
    return HAL_ERROR;
 8000f82:	2001      	movs	r0, #1
 8000f84:	e7fc      	b.n	8000f80 <HAL_RCC_ClockConfig+0x118>
      return HAL_ERROR;
 8000f86:	2001      	movs	r0, #1
 8000f88:	e7fa      	b.n	8000f80 <HAL_RCC_ClockConfig+0x118>
        return HAL_ERROR;
 8000f8a:	2001      	movs	r0, #1
 8000f8c:	e7f8      	b.n	8000f80 <HAL_RCC_ClockConfig+0x118>
      return HAL_ERROR;
 8000f8e:	2001      	movs	r0, #1
 8000f90:	e7f6      	b.n	8000f80 <HAL_RCC_ClockConfig+0x118>
 8000f92:	46c0      	nop			; (mov r8, r8)
 8000f94:	40022000 	.word	0x40022000
 8000f98:	40021000 	.word	0x40021000
 8000f9c:	00001388 	.word	0x00001388
 8000fa0:	fffff8ff 	.word	0xfffff8ff
 8000fa4:	0800169c 	.word	0x0800169c
 8000fa8:	20000000 	.word	0x20000000

08000fac <HAL_RCC_GetHCLKFreq>:
  *         and updated within this function
  * @retval HCLK frequency
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
  return SystemCoreClock;
 8000fac:	4b01      	ldr	r3, [pc, #4]	; (8000fb4 <HAL_RCC_GetHCLKFreq+0x8>)
 8000fae:	6818      	ldr	r0, [r3, #0]
}
 8000fb0:	4770      	bx	lr
 8000fb2:	46c0      	nop			; (mov r8, r8)
 8000fb4:	20000000 	.word	0x20000000

08000fb8 <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 8000fb8:	b510      	push	{r4, lr}
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]);
 8000fba:	f7ff fff7 	bl	8000fac <HAL_RCC_GetHCLKFreq>
 8000fbe:	4b04      	ldr	r3, [pc, #16]	; (8000fd0 <HAL_RCC_GetPCLK1Freq+0x18>)
 8000fc0:	685a      	ldr	r2, [r3, #4]
 8000fc2:	0a12      	lsrs	r2, r2, #8
 8000fc4:	2307      	movs	r3, #7
 8000fc6:	4013      	ands	r3, r2
 8000fc8:	4a02      	ldr	r2, [pc, #8]	; (8000fd4 <HAL_RCC_GetPCLK1Freq+0x1c>)
 8000fca:	5cd3      	ldrb	r3, [r2, r3]
 8000fcc:	40d8      	lsrs	r0, r3
}    
 8000fce:	bd10      	pop	{r4, pc}
 8000fd0:	40021000 	.word	0x40021000
 8000fd4:	08001694 	.word	0x08001694

08000fd8 <HAL_RCCEx_PeriphCLKConfig>:
  *         the backup registers) and RCC_BDCR register are set to their reset values.
  *
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
{
 8000fd8:	b570      	push	{r4, r5, r6, lr}
 8000fda:	b082      	sub	sp, #8
 8000fdc:	0004      	movs	r4, r0

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
  
  /*---------------------------- RTC configuration -------------------------------*/
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
 8000fde:	6803      	ldr	r3, [r0, #0]
 8000fe0:	03db      	lsls	r3, r3, #15
 8000fe2:	d539      	bpl.n	8001058 <HAL_RCCEx_PeriphCLKConfig+0x80>
    FlagStatus       pwrclkchanged = RESET;

    /* As soon as function is called to change RTC clock source, activation of the 
       power domain is done. */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8000fe4:	4b48      	ldr	r3, [pc, #288]	; (8001108 <HAL_RCCEx_PeriphCLKConfig+0x130>)
 8000fe6:	69db      	ldr	r3, [r3, #28]
 8000fe8:	00db      	lsls	r3, r3, #3
 8000fea:	d45f      	bmi.n	80010ac <HAL_RCCEx_PeriphCLKConfig+0xd4>
    {
    __HAL_RCC_PWR_CLK_ENABLE();
 8000fec:	4b46      	ldr	r3, [pc, #280]	; (8001108 <HAL_RCCEx_PeriphCLKConfig+0x130>)
 8000fee:	69da      	ldr	r2, [r3, #28]
 8000ff0:	2180      	movs	r1, #128	; 0x80
 8000ff2:	0549      	lsls	r1, r1, #21
 8000ff4:	430a      	orrs	r2, r1
 8000ff6:	61da      	str	r2, [r3, #28]
 8000ff8:	69db      	ldr	r3, [r3, #28]
 8000ffa:	400b      	ands	r3, r1
 8000ffc:	9301      	str	r3, [sp, #4]
 8000ffe:	9b01      	ldr	r3, [sp, #4]
      pwrclkchanged = SET;
 8001000:	2501      	movs	r5, #1
    }
    
    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8001002:	4b42      	ldr	r3, [pc, #264]	; (800110c <HAL_RCCEx_PeriphCLKConfig+0x134>)
 8001004:	681b      	ldr	r3, [r3, #0]
 8001006:	05db      	lsls	r3, r3, #23
 8001008:	d552      	bpl.n	80010b0 <HAL_RCCEx_PeriphCLKConfig+0xd8>
        }
      }
    }
    
    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ 
    temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
 800100a:	4b3f      	ldr	r3, [pc, #252]	; (8001108 <HAL_RCCEx_PeriphCLKConfig+0x130>)
 800100c:	6a1a      	ldr	r2, [r3, #32]
 800100e:	23c0      	movs	r3, #192	; 0xc0
 8001010:	009b      	lsls	r3, r3, #2
 8001012:	0011      	movs	r1, r2
 8001014:	4019      	ands	r1, r3
    if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
 8001016:	421a      	tst	r2, r3
 8001018:	d015      	beq.n	8001046 <HAL_RCCEx_PeriphCLKConfig+0x6e>
 800101a:	6863      	ldr	r3, [r4, #4]
 800101c:	22c0      	movs	r2, #192	; 0xc0
 800101e:	0092      	lsls	r2, r2, #2
 8001020:	4013      	ands	r3, r2
 8001022:	428b      	cmp	r3, r1
 8001024:	d00f      	beq.n	8001046 <HAL_RCCEx_PeriphCLKConfig+0x6e>
    {
      /* Store the content of BDCR register before the reset of Backup Domain */
      temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
 8001026:	4b38      	ldr	r3, [pc, #224]	; (8001108 <HAL_RCCEx_PeriphCLKConfig+0x130>)
 8001028:	6a1a      	ldr	r2, [r3, #32]
 800102a:	4939      	ldr	r1, [pc, #228]	; (8001110 <HAL_RCCEx_PeriphCLKConfig+0x138>)
 800102c:	4011      	ands	r1, r2
      /* RTC Clock selection can be changed only if the Backup Domain is reset */
      __HAL_RCC_BACKUPRESET_FORCE();
 800102e:	6a1e      	ldr	r6, [r3, #32]
 8001030:	2080      	movs	r0, #128	; 0x80
 8001032:	0240      	lsls	r0, r0, #9
 8001034:	4330      	orrs	r0, r6
 8001036:	6218      	str	r0, [r3, #32]
      __HAL_RCC_BACKUPRESET_RELEASE();
 8001038:	6a18      	ldr	r0, [r3, #32]
 800103a:	4e36      	ldr	r6, [pc, #216]	; (8001114 <HAL_RCCEx_PeriphCLKConfig+0x13c>)
 800103c:	4030      	ands	r0, r6
 800103e:	6218      	str	r0, [r3, #32]
      /* Restore the Content of BDCR register */
      RCC->BDCR = temp_reg;
 8001040:	6219      	str	r1, [r3, #32]
      
      /* Wait for LSERDY if LSE was enabled */
      if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
 8001042:	07d2      	lsls	r2, r2, #31
 8001044:	d448      	bmi.n	80010d8 <HAL_RCCEx_PeriphCLKConfig+0x100>
            return HAL_TIMEOUT;
          }
        }
      }
    }
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 8001046:	4a30      	ldr	r2, [pc, #192]	; (8001108 <HAL_RCCEx_PeriphCLKConfig+0x130>)
 8001048:	6a13      	ldr	r3, [r2, #32]
 800104a:	4931      	ldr	r1, [pc, #196]	; (8001110 <HAL_RCCEx_PeriphCLKConfig+0x138>)
 800104c:	400b      	ands	r3, r1
 800104e:	6861      	ldr	r1, [r4, #4]
 8001050:	430b      	orrs	r3, r1
 8001052:	6213      	str	r3, [r2, #32]

    /* Require to disable power clock if necessary */
    if(pwrclkchanged == SET)
 8001054:	2d01      	cmp	r5, #1
 8001056:	d04e      	beq.n	80010f6 <HAL_RCCEx_PeriphCLKConfig+0x11e>
      __HAL_RCC_PWR_CLK_DISABLE();
    }
  }

  /*------------------------------- USART1 Configuration ------------------------*/ 
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
 8001058:	6823      	ldr	r3, [r4, #0]
 800105a:	07db      	lsls	r3, r3, #31
 800105c:	d506      	bpl.n	800106c <HAL_RCCEx_PeriphCLKConfig+0x94>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
    
    /* Configure the USART1 clock source */
    __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
 800105e:	4a2a      	ldr	r2, [pc, #168]	; (8001108 <HAL_RCCEx_PeriphCLKConfig+0x130>)
 8001060:	6b13      	ldr	r3, [r2, #48]	; 0x30
 8001062:	2103      	movs	r1, #3
 8001064:	438b      	bics	r3, r1
 8001066:	68a1      	ldr	r1, [r4, #8]
 8001068:	430b      	orrs	r3, r1
 800106a:	6313      	str	r3, [r2, #48]	; 0x30
    __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
  }
#endif /* STM32F091xC || STM32F098xx */  

  /*------------------------------ I2C1 Configuration ------------------------*/ 
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
 800106c:	6823      	ldr	r3, [r4, #0]
 800106e:	069b      	lsls	r3, r3, #26
 8001070:	d506      	bpl.n	8001080 <HAL_RCCEx_PeriphCLKConfig+0xa8>
  {
    /* Check the parameters */
    assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
    
    /* Configure the I2C1 clock source */
    __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
 8001072:	4a25      	ldr	r2, [pc, #148]	; (8001108 <HAL_RCCEx_PeriphCLKConfig+0x130>)
 8001074:	6b13      	ldr	r3, [r2, #48]	; 0x30
 8001076:	2110      	movs	r1, #16
 8001078:	438b      	bics	r3, r1
 800107a:	68e1      	ldr	r1, [r4, #12]
 800107c:	430b      	orrs	r3, r1
 800107e:	6313      	str	r3, [r2, #48]	; 0x30
  }

#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
  /*------------------------------ USB Configuration ------------------------*/ 
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
 8001080:	6823      	ldr	r3, [r4, #0]
 8001082:	039b      	lsls	r3, r3, #14
 8001084:	d506      	bpl.n	8001094 <HAL_RCCEx_PeriphCLKConfig+0xbc>
  {
    /* Check the parameters */
    assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
    
    /* Configure the USB clock source */
    __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
 8001086:	4a20      	ldr	r2, [pc, #128]	; (8001108 <HAL_RCCEx_PeriphCLKConfig+0x130>)
 8001088:	6b13      	ldr	r3, [r2, #48]	; 0x30
 800108a:	2180      	movs	r1, #128	; 0x80
 800108c:	438b      	bics	r3, r1
 800108e:	6961      	ldr	r1, [r4, #20]
 8001090:	430b      	orrs	r3, r1
 8001092:	6313      	str	r3, [r2, #48]	; 0x30
#if defined(STM32F042x6) || defined(STM32F048xx)\
 || defined(STM32F051x8) || defined(STM32F058xx)\
 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
 || defined(STM32F091xC) || defined(STM32F098xx)
  /*------------------------------ CEC clock Configuration -------------------*/ 
  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
 8001094:	6823      	ldr	r3, [r4, #0]
 8001096:	055b      	lsls	r3, r3, #21
 8001098:	d532      	bpl.n	8001100 <HAL_RCCEx_PeriphCLKConfig+0x128>
  {
    /* Check the parameters */
    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
    
    /* Configure the CEC clock source */
    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
 800109a:	4a1b      	ldr	r2, [pc, #108]	; (8001108 <HAL_RCCEx_PeriphCLKConfig+0x130>)
 800109c:	6b13      	ldr	r3, [r2, #48]	; 0x30
 800109e:	2140      	movs	r1, #64	; 0x40
 80010a0:	438b      	bics	r3, r1
 80010a2:	6921      	ldr	r1, [r4, #16]
 80010a4:	430b      	orrs	r3, r1
 80010a6:	6313      	str	r3, [r2, #48]	; 0x30
#endif /* STM32F042x6 || STM32F048xx ||                */
       /* STM32F051x8 || STM32F058xx ||                */
       /* STM32F071xB || STM32F072xB || STM32F078xx || */
       /* STM32F091xC || STM32F098xx */
  
  return HAL_OK;
 80010a8:	2000      	movs	r0, #0
 80010aa:	e02a      	b.n	8001102 <HAL_RCCEx_PeriphCLKConfig+0x12a>
    FlagStatus       pwrclkchanged = RESET;
 80010ac:	2500      	movs	r5, #0
 80010ae:	e7a8      	b.n	8001002 <HAL_RCCEx_PeriphCLKConfig+0x2a>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 80010b0:	4a16      	ldr	r2, [pc, #88]	; (800110c <HAL_RCCEx_PeriphCLKConfig+0x134>)
 80010b2:	6811      	ldr	r1, [r2, #0]
 80010b4:	2380      	movs	r3, #128	; 0x80
 80010b6:	005b      	lsls	r3, r3, #1
 80010b8:	430b      	orrs	r3, r1
 80010ba:	6013      	str	r3, [r2, #0]
      tickstart = HAL_GetTick();
 80010bc:	f7ff fa22 	bl	8000504 <HAL_GetTick>
 80010c0:	0006      	movs	r6, r0
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80010c2:	4b12      	ldr	r3, [pc, #72]	; (800110c <HAL_RCCEx_PeriphCLKConfig+0x134>)
 80010c4:	681b      	ldr	r3, [r3, #0]
 80010c6:	05db      	lsls	r3, r3, #23
 80010c8:	d49f      	bmi.n	800100a <HAL_RCCEx_PeriphCLKConfig+0x32>
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 80010ca:	f7ff fa1b 	bl	8000504 <HAL_GetTick>
 80010ce:	1b80      	subs	r0, r0, r6
 80010d0:	2864      	cmp	r0, #100	; 0x64
 80010d2:	d9f6      	bls.n	80010c2 <HAL_RCCEx_PeriphCLKConfig+0xea>
          return HAL_TIMEOUT;
 80010d4:	2003      	movs	r0, #3
 80010d6:	e014      	b.n	8001102 <HAL_RCCEx_PeriphCLKConfig+0x12a>
        tickstart = HAL_GetTick();
 80010d8:	f7ff fa14 	bl	8000504 <HAL_GetTick>
 80010dc:	0006      	movs	r6, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 80010de:	4b0a      	ldr	r3, [pc, #40]	; (8001108 <HAL_RCCEx_PeriphCLKConfig+0x130>)
 80010e0:	6a1b      	ldr	r3, [r3, #32]
 80010e2:	079b      	lsls	r3, r3, #30
 80010e4:	d4af      	bmi.n	8001046 <HAL_RCCEx_PeriphCLKConfig+0x6e>
          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 80010e6:	f7ff fa0d 	bl	8000504 <HAL_GetTick>
 80010ea:	1b80      	subs	r0, r0, r6
 80010ec:	4b0a      	ldr	r3, [pc, #40]	; (8001118 <HAL_RCCEx_PeriphCLKConfig+0x140>)
 80010ee:	4298      	cmp	r0, r3
 80010f0:	d9f5      	bls.n	80010de <HAL_RCCEx_PeriphCLKConfig+0x106>
            return HAL_TIMEOUT;
 80010f2:	2003      	movs	r0, #3
 80010f4:	e005      	b.n	8001102 <HAL_RCCEx_PeriphCLKConfig+0x12a>
      __HAL_RCC_PWR_CLK_DISABLE();
 80010f6:	69d3      	ldr	r3, [r2, #28]
 80010f8:	4908      	ldr	r1, [pc, #32]	; (800111c <HAL_RCCEx_PeriphCLKConfig+0x144>)
 80010fa:	400b      	ands	r3, r1
 80010fc:	61d3      	str	r3, [r2, #28]
 80010fe:	e7ab      	b.n	8001058 <HAL_RCCEx_PeriphCLKConfig+0x80>
  return HAL_OK;
 8001100:	2000      	movs	r0, #0
}
 8001102:	b002      	add	sp, #8
 8001104:	bd70      	pop	{r4, r5, r6, pc}
 8001106:	46c0      	nop			; (mov r8, r8)
 8001108:	40021000 	.word	0x40021000
 800110c:	40007000 	.word	0x40007000
 8001110:	fffffcff 	.word	0xfffffcff
 8001114:	fffeffff 	.word	0xfffeffff
 8001118:	00001388 	.word	0x00001388
 800111c:	efffffff 	.word	0xefffffff

08001120 <UART_EndRxTransfer>:
  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
  * @param  huart UART handle.
  * @retval None
  */
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
 8001120:	b510      	push	{r4, lr}
 */
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
  uint32_t result;

  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
 8001122:	f3ef 8c10 	mrs	ip, PRIMASK
  \details Assigns the given value to the Priority Mask Register.
  \param [in]    priMask  Priority Mask
 */
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
 8001126:	2201      	movs	r2, #1
 8001128:	f382 8810 	msr	PRIMASK, r2
  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 800112c:	6801      	ldr	r1, [r0, #0]
 800112e:	680b      	ldr	r3, [r1, #0]
 8001130:	4c12      	ldr	r4, [pc, #72]	; (800117c <UART_EndRxTransfer+0x5c>)
 8001132:	4023      	ands	r3, r4
 8001134:	600b      	str	r3, [r1, #0]
 8001136:	f38c 8810 	msr	PRIMASK, ip
  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
 800113a:	f3ef 8c10 	mrs	ip, PRIMASK
  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
 800113e:	f382 8810 	msr	PRIMASK, r2
  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8001142:	6801      	ldr	r1, [r0, #0]
 8001144:	688b      	ldr	r3, [r1, #8]
 8001146:	4393      	bics	r3, r2
 8001148:	608b      	str	r3, [r1, #8]
 800114a:	f38c 8810 	msr	PRIMASK, ip

  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
 800114e:	6e03      	ldr	r3, [r0, #96]	; 0x60
 8001150:	2b01      	cmp	r3, #1
 8001152:	d006      	beq.n	8001162 <UART_EndRxTransfer+0x42>
  {
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
  }

  /* At end of Rx process, restore huart->RxState to Ready */
  huart->RxState = HAL_UART_STATE_READY;
 8001154:	2380      	movs	r3, #128	; 0x80
 8001156:	2220      	movs	r2, #32
 8001158:	50c2      	str	r2, [r0, r3]
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800115a:	2300      	movs	r3, #0
 800115c:	6603      	str	r3, [r0, #96]	; 0x60

  /* Reset RxIsr function pointer */
  huart->RxISR = NULL;
 800115e:	6683      	str	r3, [r0, #104]	; 0x68
}
 8001160:	bd10      	pop	{r4, pc}
  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
 8001162:	f3ef 8110 	mrs	r1, PRIMASK
  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
 8001166:	f383 8810 	msr	PRIMASK, r3
    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 800116a:	6802      	ldr	r2, [r0, #0]
 800116c:	6813      	ldr	r3, [r2, #0]
 800116e:	3432      	adds	r4, #50	; 0x32
 8001170:	34ff      	adds	r4, #255	; 0xff
 8001172:	43a3      	bics	r3, r4
 8001174:	6013      	str	r3, [r2, #0]
 8001176:	f381 8810 	msr	PRIMASK, r1
}
 800117a:	e7eb      	b.n	8001154 <UART_EndRxTransfer+0x34>
 800117c:	fffffedf 	.word	0xfffffedf

08001180 <UART_SetConfig>:
{
 8001180:	b510      	push	{r4, lr}
 8001182:	0004      	movs	r4, r0
  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
 8001184:	6883      	ldr	r3, [r0, #8]
 8001186:	6902      	ldr	r2, [r0, #16]
 8001188:	4313      	orrs	r3, r2
 800118a:	6942      	ldr	r2, [r0, #20]
 800118c:	4313      	orrs	r3, r2
 800118e:	69c2      	ldr	r2, [r0, #28]
 8001190:	4313      	orrs	r3, r2
  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
 8001192:	6801      	ldr	r1, [r0, #0]
 8001194:	680a      	ldr	r2, [r1, #0]
 8001196:	484d      	ldr	r0, [pc, #308]	; (80012cc <UART_SetConfig+0x14c>)
 8001198:	4002      	ands	r2, r0
 800119a:	4313      	orrs	r3, r2
 800119c:	600b      	str	r3, [r1, #0]
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 800119e:	6822      	ldr	r2, [r4, #0]
 80011a0:	6853      	ldr	r3, [r2, #4]
 80011a2:	494b      	ldr	r1, [pc, #300]	; (80012d0 <UART_SetConfig+0x150>)
 80011a4:	400b      	ands	r3, r1
 80011a6:	68e1      	ldr	r1, [r4, #12]
 80011a8:	430b      	orrs	r3, r1
 80011aa:	6053      	str	r3, [r2, #4]
  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
 80011ac:	69a3      	ldr	r3, [r4, #24]
  tmpreg |= huart->Init.OneBitSampling;
 80011ae:	6a22      	ldr	r2, [r4, #32]
 80011b0:	431a      	orrs	r2, r3
  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
 80011b2:	6821      	ldr	r1, [r4, #0]
 80011b4:	688b      	ldr	r3, [r1, #8]
 80011b6:	4847      	ldr	r0, [pc, #284]	; (80012d4 <UART_SetConfig+0x154>)
 80011b8:	4003      	ands	r3, r0
 80011ba:	4313      	orrs	r3, r2
 80011bc:	608b      	str	r3, [r1, #8]
  UART_GETCLOCKSOURCE(huart, clocksource);
 80011be:	6823      	ldr	r3, [r4, #0]
 80011c0:	4a45      	ldr	r2, [pc, #276]	; (80012d8 <UART_SetConfig+0x158>)
 80011c2:	4293      	cmp	r3, r2
 80011c4:	d021      	beq.n	800120a <UART_SetConfig+0x8a>
 80011c6:	4a45      	ldr	r2, [pc, #276]	; (80012dc <UART_SetConfig+0x15c>)
 80011c8:	4293      	cmp	r3, r2
 80011ca:	d02f      	beq.n	800122c <UART_SetConfig+0xac>
 80011cc:	2310      	movs	r3, #16
  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 80011ce:	69e0      	ldr	r0, [r4, #28]
 80011d0:	2280      	movs	r2, #128	; 0x80
 80011d2:	0212      	lsls	r2, r2, #8
 80011d4:	4290      	cmp	r0, r2
 80011d6:	d033      	beq.n	8001240 <UART_SetConfig+0xc0>
    switch (clocksource)
 80011d8:	2b04      	cmp	r3, #4
 80011da:	d100      	bne.n	80011de <UART_SetConfig+0x5e>
 80011dc:	e06f      	b.n	80012be <UART_SetConfig+0x13e>
 80011de:	d85e      	bhi.n	800129e <UART_SetConfig+0x11e>
 80011e0:	2b00      	cmp	r3, #0
 80011e2:	d066      	beq.n	80012b2 <UART_SetConfig+0x132>
 80011e4:	2b02      	cmp	r3, #2
 80011e6:	d158      	bne.n	800129a <UART_SetConfig+0x11a>
 80011e8:	483d      	ldr	r0, [pc, #244]	; (80012e0 <UART_SetConfig+0x160>)
      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
 80011ea:	6861      	ldr	r1, [r4, #4]
 80011ec:	084b      	lsrs	r3, r1, #1
 80011ee:	1818      	adds	r0, r3, r0
 80011f0:	f7fe ff66 	bl	80000c0 <__udivsi3>
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 80011f4:	0002      	movs	r2, r0
 80011f6:	3a10      	subs	r2, #16
 80011f8:	4b3a      	ldr	r3, [pc, #232]	; (80012e4 <UART_SetConfig+0x164>)
 80011fa:	429a      	cmp	r2, r3
 80011fc:	d864      	bhi.n	80012c8 <UART_SetConfig+0x148>
        huart->Instance->BRR = (uint16_t)usartdiv;
 80011fe:	6823      	ldr	r3, [r4, #0]
 8001200:	0400      	lsls	r0, r0, #16
 8001202:	0c00      	lsrs	r0, r0, #16
 8001204:	60d8      	str	r0, [r3, #12]
 8001206:	2000      	movs	r0, #0
 8001208:	e04f      	b.n	80012aa <UART_SetConfig+0x12a>
  UART_GETCLOCKSOURCE(huart, clocksource);
 800120a:	4b37      	ldr	r3, [pc, #220]	; (80012e8 <UART_SetConfig+0x168>)
 800120c:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 800120e:	2303      	movs	r3, #3
 8001210:	4013      	ands	r3, r2
 8001212:	2b02      	cmp	r3, #2
 8001214:	d00c      	beq.n	8001230 <UART_SetConfig+0xb0>
 8001216:	d805      	bhi.n	8001224 <UART_SetConfig+0xa4>
 8001218:	2b00      	cmp	r3, #0
 800121a:	d00b      	beq.n	8001234 <UART_SetConfig+0xb4>
 800121c:	2b01      	cmp	r3, #1
 800121e:	d10b      	bne.n	8001238 <UART_SetConfig+0xb8>
 8001220:	3303      	adds	r3, #3
 8001222:	e7d4      	b.n	80011ce <UART_SetConfig+0x4e>
 8001224:	2b03      	cmp	r3, #3
 8001226:	d109      	bne.n	800123c <UART_SetConfig+0xbc>
 8001228:	3b01      	subs	r3, #1
 800122a:	e7d0      	b.n	80011ce <UART_SetConfig+0x4e>
 800122c:	2300      	movs	r3, #0
 800122e:	e7ce      	b.n	80011ce <UART_SetConfig+0x4e>
 8001230:	2308      	movs	r3, #8
 8001232:	e7cc      	b.n	80011ce <UART_SetConfig+0x4e>
 8001234:	2300      	movs	r3, #0
 8001236:	e7ca      	b.n	80011ce <UART_SetConfig+0x4e>
 8001238:	2310      	movs	r3, #16
 800123a:	e7c8      	b.n	80011ce <UART_SetConfig+0x4e>
 800123c:	2310      	movs	r3, #16
 800123e:	e7c6      	b.n	80011ce <UART_SetConfig+0x4e>
    switch (clocksource)
 8001240:	2b04      	cmp	r3, #4
 8001242:	d027      	beq.n	8001294 <UART_SetConfig+0x114>
 8001244:	d81c      	bhi.n	8001280 <UART_SetConfig+0x100>
 8001246:	2b00      	cmp	r3, #0
 8001248:	d01e      	beq.n	8001288 <UART_SetConfig+0x108>
 800124a:	2b02      	cmp	r3, #2
 800124c:	d116      	bne.n	800127c <UART_SetConfig+0xfc>
        pclk = (uint32_t) HSI_VALUE;
 800124e:	4824      	ldr	r0, [pc, #144]	; (80012e0 <UART_SetConfig+0x160>)
      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
 8001250:	0040      	lsls	r0, r0, #1
 8001252:	6861      	ldr	r1, [r4, #4]
 8001254:	084b      	lsrs	r3, r1, #1
 8001256:	18c0      	adds	r0, r0, r3
 8001258:	f7fe ff32 	bl	80000c0 <__udivsi3>
      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
 800125c:	0002      	movs	r2, r0
 800125e:	3a10      	subs	r2, #16
 8001260:	4b20      	ldr	r3, [pc, #128]	; (80012e4 <UART_SetConfig+0x164>)
 8001262:	429a      	cmp	r2, r3
 8001264:	d82e      	bhi.n	80012c4 <UART_SetConfig+0x144>
        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
 8001266:	b282      	uxth	r2, r0
 8001268:	230f      	movs	r3, #15
 800126a:	439a      	bics	r2, r3
        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
 800126c:	0840      	lsrs	r0, r0, #1
 800126e:	3b08      	subs	r3, #8
 8001270:	4003      	ands	r3, r0
 8001272:	4313      	orrs	r3, r2
        huart->Instance->BRR = brrtemp;
 8001274:	6822      	ldr	r2, [r4, #0]
 8001276:	60d3      	str	r3, [r2, #12]
 8001278:	2000      	movs	r0, #0
 800127a:	e016      	b.n	80012aa <UART_SetConfig+0x12a>
    switch (clocksource)
 800127c:	2001      	movs	r0, #1
 800127e:	e014      	b.n	80012aa <UART_SetConfig+0x12a>
 8001280:	2b08      	cmp	r3, #8
 8001282:	d0e5      	beq.n	8001250 <UART_SetConfig+0xd0>
 8001284:	2001      	movs	r0, #1
 8001286:	e010      	b.n	80012aa <UART_SetConfig+0x12a>
        pclk = HAL_RCC_GetPCLK1Freq();
 8001288:	f7ff fe96 	bl	8000fb8 <HAL_RCC_GetPCLK1Freq>
    if (pclk != 0U)
 800128c:	2800      	cmp	r0, #0
 800128e:	d1df      	bne.n	8001250 <UART_SetConfig+0xd0>
 8001290:	2000      	movs	r0, #0
 8001292:	e00a      	b.n	80012aa <UART_SetConfig+0x12a>
        pclk = HAL_RCC_GetSysClockFreq();
 8001294:	f7ff fdac 	bl	8000df0 <HAL_RCC_GetSysClockFreq>
        break;
 8001298:	e7f8      	b.n	800128c <UART_SetConfig+0x10c>
    switch (clocksource)
 800129a:	2001      	movs	r0, #1
 800129c:	e005      	b.n	80012aa <UART_SetConfig+0x12a>
 800129e:	2b08      	cmp	r3, #8
 80012a0:	d102      	bne.n	80012a8 <UART_SetConfig+0x128>
        pclk = (uint32_t) LSE_VALUE;
 80012a2:	2080      	movs	r0, #128	; 0x80
 80012a4:	0200      	lsls	r0, r0, #8
 80012a6:	e7a0      	b.n	80011ea <UART_SetConfig+0x6a>
    switch (clocksource)
 80012a8:	2001      	movs	r0, #1
  huart->RxISR = NULL;
 80012aa:	2300      	movs	r3, #0
 80012ac:	66a3      	str	r3, [r4, #104]	; 0x68
  huart->TxISR = NULL;
 80012ae:	66e3      	str	r3, [r4, #108]	; 0x6c
}
 80012b0:	bd10      	pop	{r4, pc}
        pclk = HAL_RCC_GetPCLK1Freq();
 80012b2:	f7ff fe81 	bl	8000fb8 <HAL_RCC_GetPCLK1Freq>
    if (pclk != 0U)
 80012b6:	2800      	cmp	r0, #0
 80012b8:	d197      	bne.n	80011ea <UART_SetConfig+0x6a>
 80012ba:	2000      	movs	r0, #0
 80012bc:	e7f5      	b.n	80012aa <UART_SetConfig+0x12a>
        pclk = HAL_RCC_GetSysClockFreq();
 80012be:	f7ff fd97 	bl	8000df0 <HAL_RCC_GetSysClockFreq>
        break;
 80012c2:	e7f8      	b.n	80012b6 <UART_SetConfig+0x136>
        ret = HAL_ERROR;
 80012c4:	2001      	movs	r0, #1
 80012c6:	e7f0      	b.n	80012aa <UART_SetConfig+0x12a>
        ret = HAL_ERROR;
 80012c8:	2001      	movs	r0, #1
 80012ca:	e7ee      	b.n	80012aa <UART_SetConfig+0x12a>
 80012cc:	efff69f3 	.word	0xefff69f3
 80012d0:	ffffcfff 	.word	0xffffcfff
 80012d4:	fffff4ff 	.word	0xfffff4ff
 80012d8:	40013800 	.word	0x40013800
 80012dc:	40004400 	.word	0x40004400
 80012e0:	007a1200 	.word	0x007a1200
 80012e4:	0000ffef 	.word	0x0000ffef
 80012e8:	40021000 	.word	0x40021000

080012ec <UART_AdvFeatureConfig>:
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
 80012ec:	6a43      	ldr	r3, [r0, #36]	; 0x24
 80012ee:	07db      	lsls	r3, r3, #31
 80012f0:	d506      	bpl.n	8001300 <UART_AdvFeatureConfig+0x14>
    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
 80012f2:	6802      	ldr	r2, [r0, #0]
 80012f4:	6853      	ldr	r3, [r2, #4]
 80012f6:	492c      	ldr	r1, [pc, #176]	; (80013a8 <UART_AdvFeatureConfig+0xbc>)
 80012f8:	400b      	ands	r3, r1
 80012fa:	6a81      	ldr	r1, [r0, #40]	; 0x28
 80012fc:	430b      	orrs	r3, r1
 80012fe:	6053      	str	r3, [r2, #4]
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
 8001300:	6a43      	ldr	r3, [r0, #36]	; 0x24
 8001302:	079b      	lsls	r3, r3, #30
 8001304:	d506      	bpl.n	8001314 <UART_AdvFeatureConfig+0x28>
    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
 8001306:	6802      	ldr	r2, [r0, #0]
 8001308:	6853      	ldr	r3, [r2, #4]
 800130a:	4928      	ldr	r1, [pc, #160]	; (80013ac <UART_AdvFeatureConfig+0xc0>)
 800130c:	400b      	ands	r3, r1
 800130e:	6ac1      	ldr	r1, [r0, #44]	; 0x2c
 8001310:	430b      	orrs	r3, r1
 8001312:	6053      	str	r3, [r2, #4]
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
 8001314:	6a43      	ldr	r3, [r0, #36]	; 0x24
 8001316:	075b      	lsls	r3, r3, #29
 8001318:	d506      	bpl.n	8001328 <UART_AdvFeatureConfig+0x3c>
    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
 800131a:	6802      	ldr	r2, [r0, #0]
 800131c:	6853      	ldr	r3, [r2, #4]
 800131e:	4924      	ldr	r1, [pc, #144]	; (80013b0 <UART_AdvFeatureConfig+0xc4>)
 8001320:	400b      	ands	r3, r1
 8001322:	6b01      	ldr	r1, [r0, #48]	; 0x30
 8001324:	430b      	orrs	r3, r1
 8001326:	6053      	str	r3, [r2, #4]
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
 8001328:	6a43      	ldr	r3, [r0, #36]	; 0x24
 800132a:	071b      	lsls	r3, r3, #28
 800132c:	d506      	bpl.n	800133c <UART_AdvFeatureConfig+0x50>
    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
 800132e:	6802      	ldr	r2, [r0, #0]
 8001330:	6853      	ldr	r3, [r2, #4]
 8001332:	4920      	ldr	r1, [pc, #128]	; (80013b4 <UART_AdvFeatureConfig+0xc8>)
 8001334:	400b      	ands	r3, r1
 8001336:	6b41      	ldr	r1, [r0, #52]	; 0x34
 8001338:	430b      	orrs	r3, r1
 800133a:	6053      	str	r3, [r2, #4]
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
 800133c:	6a43      	ldr	r3, [r0, #36]	; 0x24
 800133e:	06db      	lsls	r3, r3, #27
 8001340:	d506      	bpl.n	8001350 <UART_AdvFeatureConfig+0x64>
    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
 8001342:	6802      	ldr	r2, [r0, #0]
 8001344:	6893      	ldr	r3, [r2, #8]
 8001346:	491c      	ldr	r1, [pc, #112]	; (80013b8 <UART_AdvFeatureConfig+0xcc>)
 8001348:	400b      	ands	r3, r1
 800134a:	6b81      	ldr	r1, [r0, #56]	; 0x38
 800134c:	430b      	orrs	r3, r1
 800134e:	6093      	str	r3, [r2, #8]
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
 8001350:	6a43      	ldr	r3, [r0, #36]	; 0x24
 8001352:	069b      	lsls	r3, r3, #26
 8001354:	d506      	bpl.n	8001364 <UART_AdvFeatureConfig+0x78>
    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
 8001356:	6802      	ldr	r2, [r0, #0]
 8001358:	6893      	ldr	r3, [r2, #8]
 800135a:	4918      	ldr	r1, [pc, #96]	; (80013bc <UART_AdvFeatureConfig+0xd0>)
 800135c:	400b      	ands	r3, r1
 800135e:	6bc1      	ldr	r1, [r0, #60]	; 0x3c
 8001360:	430b      	orrs	r3, r1
 8001362:	6093      	str	r3, [r2, #8]
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
 8001364:	6a43      	ldr	r3, [r0, #36]	; 0x24
 8001366:	065b      	lsls	r3, r3, #25
 8001368:	d50b      	bpl.n	8001382 <UART_AdvFeatureConfig+0x96>
    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
 800136a:	6802      	ldr	r2, [r0, #0]
 800136c:	6853      	ldr	r3, [r2, #4]
 800136e:	4914      	ldr	r1, [pc, #80]	; (80013c0 <UART_AdvFeatureConfig+0xd4>)
 8001370:	400b      	ands	r3, r1
 8001372:	6c01      	ldr	r1, [r0, #64]	; 0x40
 8001374:	430b      	orrs	r3, r1
 8001376:	6053      	str	r3, [r2, #4]
    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
 8001378:	6c02      	ldr	r2, [r0, #64]	; 0x40
 800137a:	2380      	movs	r3, #128	; 0x80
 800137c:	035b      	lsls	r3, r3, #13
 800137e:	429a      	cmp	r2, r3
 8001380:	d00a      	beq.n	8001398 <UART_AdvFeatureConfig+0xac>
  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
 8001382:	6a43      	ldr	r3, [r0, #36]	; 0x24
 8001384:	061b      	lsls	r3, r3, #24
 8001386:	d506      	bpl.n	8001396 <UART_AdvFeatureConfig+0xaa>
    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
 8001388:	6802      	ldr	r2, [r0, #0]
 800138a:	6853      	ldr	r3, [r2, #4]
 800138c:	490d      	ldr	r1, [pc, #52]	; (80013c4 <UART_AdvFeatureConfig+0xd8>)
 800138e:	400b      	ands	r3, r1
 8001390:	6c81      	ldr	r1, [r0, #72]	; 0x48
 8001392:	430b      	orrs	r3, r1
 8001394:	6053      	str	r3, [r2, #4]
}
 8001396:	4770      	bx	lr
      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
 8001398:	6802      	ldr	r2, [r0, #0]
 800139a:	6853      	ldr	r3, [r2, #4]
 800139c:	490a      	ldr	r1, [pc, #40]	; (80013c8 <UART_AdvFeatureConfig+0xdc>)
 800139e:	400b      	ands	r3, r1
 80013a0:	6c41      	ldr	r1, [r0, #68]	; 0x44
 80013a2:	430b      	orrs	r3, r1
 80013a4:	6053      	str	r3, [r2, #4]
 80013a6:	e7ec      	b.n	8001382 <UART_AdvFeatureConfig+0x96>
 80013a8:	fffdffff 	.word	0xfffdffff
 80013ac:	fffeffff 	.word	0xfffeffff
 80013b0:	fffbffff 	.word	0xfffbffff
 80013b4:	ffff7fff 	.word	0xffff7fff
 80013b8:	ffffefff 	.word	0xffffefff
 80013bc:	ffffdfff 	.word	0xffffdfff
 80013c0:	ffefffff 	.word	0xffefffff
 80013c4:	fff7ffff 	.word	0xfff7ffff
 80013c8:	ff9fffff 	.word	0xff9fffff

080013cc <UART_WaitOnFlagUntilTimeout>:
{
 80013cc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80013ce:	46ce      	mov	lr, r9
 80013d0:	4647      	mov	r7, r8
 80013d2:	b580      	push	{r7, lr}
 80013d4:	0006      	movs	r6, r0
 80013d6:	000d      	movs	r5, r1
 80013d8:	0017      	movs	r7, r2
 80013da:	4699      	mov	r9, r3
 80013dc:	9b08      	ldr	r3, [sp, #32]
 80013de:	4698      	mov	r8, r3
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 80013e0:	6833      	ldr	r3, [r6, #0]
 80013e2:	69dc      	ldr	r4, [r3, #28]
 80013e4:	402c      	ands	r4, r5
 80013e6:	1b64      	subs	r4, r4, r5
 80013e8:	4263      	negs	r3, r4
 80013ea:	415c      	adcs	r4, r3
 80013ec:	42bc      	cmp	r4, r7
 80013ee:	d12f      	bne.n	8001450 <UART_WaitOnFlagUntilTimeout+0x84>
    if (Timeout != HAL_MAX_DELAY)
 80013f0:	4643      	mov	r3, r8
 80013f2:	3301      	adds	r3, #1
 80013f4:	d0f4      	beq.n	80013e0 <UART_WaitOnFlagUntilTimeout+0x14>
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 80013f6:	f7ff f885 	bl	8000504 <HAL_GetTick>
 80013fa:	464b      	mov	r3, r9
 80013fc:	1ac0      	subs	r0, r0, r3
 80013fe:	4540      	cmp	r0, r8
 8001400:	d82b      	bhi.n	800145a <UART_WaitOnFlagUntilTimeout+0x8e>
 8001402:	4643      	mov	r3, r8
 8001404:	2b00      	cmp	r3, #0
 8001406:	d02a      	beq.n	800145e <UART_WaitOnFlagUntilTimeout+0x92>
      if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
 8001408:	6833      	ldr	r3, [r6, #0]
 800140a:	681a      	ldr	r2, [r3, #0]
 800140c:	0752      	lsls	r2, r2, #29
 800140e:	d5e7      	bpl.n	80013e0 <UART_WaitOnFlagUntilTimeout+0x14>
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
 8001410:	69da      	ldr	r2, [r3, #28]
 8001412:	0712      	lsls	r2, r2, #28
 8001414:	d410      	bmi.n	8001438 <UART_WaitOnFlagUntilTimeout+0x6c>
        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
 8001416:	69da      	ldr	r2, [r3, #28]
 8001418:	0512      	lsls	r2, r2, #20
 800141a:	d5e1      	bpl.n	80013e0 <UART_WaitOnFlagUntilTimeout+0x14>
          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 800141c:	2280      	movs	r2, #128	; 0x80
 800141e:	0112      	lsls	r2, r2, #4
 8001420:	621a      	str	r2, [r3, #32]
          UART_EndRxTransfer(huart);
 8001422:	0030      	movs	r0, r6
 8001424:	f7ff fe7c 	bl	8001120 <UART_EndRxTransfer>
          huart->ErrorCode = HAL_UART_ERROR_RTO;
 8001428:	2384      	movs	r3, #132	; 0x84
 800142a:	2220      	movs	r2, #32
 800142c:	50f2      	str	r2, [r6, r3]
          __HAL_UNLOCK(huart);
 800142e:	3b0c      	subs	r3, #12
 8001430:	2200      	movs	r2, #0
 8001432:	54f2      	strb	r2, [r6, r3]
          return HAL_TIMEOUT;
 8001434:	2003      	movs	r0, #3
 8001436:	e00c      	b.n	8001452 <UART_WaitOnFlagUntilTimeout+0x86>
           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
 8001438:	2408      	movs	r4, #8
 800143a:	621c      	str	r4, [r3, #32]
           UART_EndRxTransfer(huart);
 800143c:	0030      	movs	r0, r6
 800143e:	f7ff fe6f 	bl	8001120 <UART_EndRxTransfer>
           huart->ErrorCode = HAL_UART_ERROR_ORE;
 8001442:	2384      	movs	r3, #132	; 0x84
 8001444:	50f4      	str	r4, [r6, r3]
           __HAL_UNLOCK(huart);
 8001446:	3b0c      	subs	r3, #12
 8001448:	2200      	movs	r2, #0
 800144a:	54f2      	strb	r2, [r6, r3]
           return HAL_ERROR;
 800144c:	2001      	movs	r0, #1
 800144e:	e000      	b.n	8001452 <UART_WaitOnFlagUntilTimeout+0x86>
  return HAL_OK;
 8001450:	2000      	movs	r0, #0
}
 8001452:	bcc0      	pop	{r6, r7}
 8001454:	46b9      	mov	r9, r7
 8001456:	46b0      	mov	r8, r6
 8001458:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
        return HAL_TIMEOUT;
 800145a:	2003      	movs	r0, #3
 800145c:	e7f9      	b.n	8001452 <UART_WaitOnFlagUntilTimeout+0x86>
 800145e:	2003      	movs	r0, #3
 8001460:	e7f7      	b.n	8001452 <UART_WaitOnFlagUntilTimeout+0x86>
	...

08001464 <UART_CheckIdleState>:
{
 8001464:	b530      	push	{r4, r5, lr}
 8001466:	b083      	sub	sp, #12
 8001468:	0004      	movs	r4, r0
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 800146a:	2384      	movs	r3, #132	; 0x84
 800146c:	2200      	movs	r2, #0
 800146e:	50c2      	str	r2, [r0, r3]
  tickstart = HAL_GetTick();
 8001470:	f7ff f848 	bl	8000504 <HAL_GetTick>
 8001474:	0005      	movs	r5, r0
  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
 8001476:	6823      	ldr	r3, [r4, #0]
 8001478:	681b      	ldr	r3, [r3, #0]
 800147a:	071b      	lsls	r3, r3, #28
 800147c:	d40f      	bmi.n	800149e <UART_CheckIdleState+0x3a>
  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
 800147e:	6823      	ldr	r3, [r4, #0]
 8001480:	681b      	ldr	r3, [r3, #0]
 8001482:	075b      	lsls	r3, r3, #29
 8001484:	d429      	bmi.n	80014da <UART_CheckIdleState+0x76>
  huart->gState = HAL_UART_STATE_READY;
 8001486:	2320      	movs	r3, #32
 8001488:	67e3      	str	r3, [r4, #124]	; 0x7c
  huart->RxState = HAL_UART_STATE_READY;
 800148a:	2280      	movs	r2, #128	; 0x80
 800148c:	50a3      	str	r3, [r4, r2]
  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 800148e:	2300      	movs	r3, #0
 8001490:	6623      	str	r3, [r4, #96]	; 0x60
  huart->RxEventType = HAL_UART_RXEVENT_TC;
 8001492:	6663      	str	r3, [r4, #100]	; 0x64
  __HAL_UNLOCK(huart);
 8001494:	3a08      	subs	r2, #8
 8001496:	54a3      	strb	r3, [r4, r2]
  return HAL_OK;
 8001498:	2000      	movs	r0, #0
}
 800149a:	b003      	add	sp, #12
 800149c:	bd30      	pop	{r4, r5, pc}
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 800149e:	2180      	movs	r1, #128	; 0x80
 80014a0:	4b22      	ldr	r3, [pc, #136]	; (800152c <UART_CheckIdleState+0xc8>)
 80014a2:	9300      	str	r3, [sp, #0]
 80014a4:	0003      	movs	r3, r0
 80014a6:	2200      	movs	r2, #0
 80014a8:	0389      	lsls	r1, r1, #14
 80014aa:	0020      	movs	r0, r4
 80014ac:	f7ff ff8e 	bl	80013cc <UART_WaitOnFlagUntilTimeout>
 80014b0:	2800      	cmp	r0, #0
 80014b2:	d0e4      	beq.n	800147e <UART_CheckIdleState+0x1a>
  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
 80014b4:	f3ef 8110 	mrs	r1, PRIMASK
  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
 80014b8:	2301      	movs	r3, #1
 80014ba:	f383 8810 	msr	PRIMASK, r3
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
 80014be:	6822      	ldr	r2, [r4, #0]
 80014c0:	6813      	ldr	r3, [r2, #0]
 80014c2:	2080      	movs	r0, #128	; 0x80
 80014c4:	4383      	bics	r3, r0
 80014c6:	6013      	str	r3, [r2, #0]
 80014c8:	f381 8810 	msr	PRIMASK, r1
      huart->gState = HAL_UART_STATE_READY;
 80014cc:	2320      	movs	r3, #32
 80014ce:	67e3      	str	r3, [r4, #124]	; 0x7c
      __HAL_UNLOCK(huart);
 80014d0:	3358      	adds	r3, #88	; 0x58
 80014d2:	2200      	movs	r2, #0
 80014d4:	54e2      	strb	r2, [r4, r3]
      return HAL_TIMEOUT;
 80014d6:	387d      	subs	r0, #125	; 0x7d
 80014d8:	e7df      	b.n	800149a <UART_CheckIdleState+0x36>
    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
 80014da:	2180      	movs	r1, #128	; 0x80
 80014dc:	4b13      	ldr	r3, [pc, #76]	; (800152c <UART_CheckIdleState+0xc8>)
 80014de:	9300      	str	r3, [sp, #0]
 80014e0:	002b      	movs	r3, r5
 80014e2:	2200      	movs	r2, #0
 80014e4:	03c9      	lsls	r1, r1, #15
 80014e6:	0020      	movs	r0, r4
 80014e8:	f7ff ff70 	bl	80013cc <UART_WaitOnFlagUntilTimeout>
 80014ec:	2800      	cmp	r0, #0
 80014ee:	d0ca      	beq.n	8001486 <UART_CheckIdleState+0x22>
  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
 80014f0:	f3ef 8010 	mrs	r0, PRIMASK
  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
 80014f4:	2201      	movs	r2, #1
 80014f6:	f382 8810 	msr	PRIMASK, r2
      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
 80014fa:	6821      	ldr	r1, [r4, #0]
 80014fc:	680b      	ldr	r3, [r1, #0]
 80014fe:	4d0c      	ldr	r5, [pc, #48]	; (8001530 <UART_CheckIdleState+0xcc>)
 8001500:	402b      	ands	r3, r5
 8001502:	600b      	str	r3, [r1, #0]
 8001504:	f380 8810 	msr	PRIMASK, r0
  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
 8001508:	f3ef 8010 	mrs	r0, PRIMASK
  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
 800150c:	f382 8810 	msr	PRIMASK, r2
      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8001510:	6821      	ldr	r1, [r4, #0]
 8001512:	688b      	ldr	r3, [r1, #8]
 8001514:	4393      	bics	r3, r2
 8001516:	608b      	str	r3, [r1, #8]
 8001518:	f380 8810 	msr	PRIMASK, r0
      huart->RxState = HAL_UART_STATE_READY;
 800151c:	2380      	movs	r3, #128	; 0x80
 800151e:	321f      	adds	r2, #31
 8001520:	50e2      	str	r2, [r4, r3]
      __HAL_UNLOCK(huart);
 8001522:	3b08      	subs	r3, #8
 8001524:	2200      	movs	r2, #0
 8001526:	54e2      	strb	r2, [r4, r3]
      return HAL_TIMEOUT;
 8001528:	2003      	movs	r0, #3
 800152a:	e7b6      	b.n	800149a <UART_CheckIdleState+0x36>
 800152c:	01ffffff 	.word	0x01ffffff
 8001530:	fffffedf 	.word	0xfffffedf

08001534 <HAL_UART_Init>:
{
 8001534:	b510      	push	{r4, lr}
 8001536:	1e04      	subs	r4, r0, #0
  if (huart == NULL)
 8001538:	d02e      	beq.n	8001598 <HAL_UART_Init+0x64>
  if (huart->gState == HAL_UART_STATE_RESET)
 800153a:	6fc3      	ldr	r3, [r0, #124]	; 0x7c
 800153c:	2b00      	cmp	r3, #0
 800153e:	d021      	beq.n	8001584 <HAL_UART_Init+0x50>
  huart->gState = HAL_UART_STATE_BUSY;
 8001540:	2324      	movs	r3, #36	; 0x24
 8001542:	67e3      	str	r3, [r4, #124]	; 0x7c
  __HAL_UART_DISABLE(huart);
 8001544:	6822      	ldr	r2, [r4, #0]
 8001546:	6813      	ldr	r3, [r2, #0]
 8001548:	2101      	movs	r1, #1
 800154a:	438b      	bics	r3, r1
 800154c:	6013      	str	r3, [r2, #0]
  if (UART_SetConfig(huart) == HAL_ERROR)
 800154e:	0020      	movs	r0, r4
 8001550:	f7ff fe16 	bl	8001180 <UART_SetConfig>
 8001554:	2801      	cmp	r0, #1
 8001556:	d014      	beq.n	8001582 <HAL_UART_Init+0x4e>
  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
 8001558:	6a63      	ldr	r3, [r4, #36]	; 0x24
 800155a:	2b00      	cmp	r3, #0
 800155c:	d118      	bne.n	8001590 <HAL_UART_Init+0x5c>
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 800155e:	6822      	ldr	r2, [r4, #0]
 8001560:	6853      	ldr	r3, [r2, #4]
 8001562:	490e      	ldr	r1, [pc, #56]	; (800159c <HAL_UART_Init+0x68>)
 8001564:	400b      	ands	r3, r1
 8001566:	6053      	str	r3, [r2, #4]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 8001568:	6822      	ldr	r2, [r4, #0]
 800156a:	6893      	ldr	r3, [r2, #8]
 800156c:	212a      	movs	r1, #42	; 0x2a
 800156e:	438b      	bics	r3, r1
 8001570:	6093      	str	r3, [r2, #8]
  __HAL_UART_ENABLE(huart);
 8001572:	6822      	ldr	r2, [r4, #0]
 8001574:	6813      	ldr	r3, [r2, #0]
 8001576:	3929      	subs	r1, #41	; 0x29
 8001578:	430b      	orrs	r3, r1
 800157a:	6013      	str	r3, [r2, #0]
  return (UART_CheckIdleState(huart));
 800157c:	0020      	movs	r0, r4
 800157e:	f7ff ff71 	bl	8001464 <UART_CheckIdleState>
}
 8001582:	bd10      	pop	{r4, pc}
    huart->Lock = HAL_UNLOCKED;
 8001584:	3378      	adds	r3, #120	; 0x78
 8001586:	2200      	movs	r2, #0
 8001588:	54c2      	strb	r2, [r0, r3]
    HAL_UART_MspInit(huart);
 800158a:	f7fe ff3b 	bl	8000404 <HAL_UART_MspInit>
 800158e:	e7d7      	b.n	8001540 <HAL_UART_Init+0xc>
    UART_AdvFeatureConfig(huart);
 8001590:	0020      	movs	r0, r4
 8001592:	f7ff feab 	bl	80012ec <UART_AdvFeatureConfig>
 8001596:	e7e2      	b.n	800155e <HAL_UART_Init+0x2a>
    return HAL_ERROR;
 8001598:	2001      	movs	r0, #1
 800159a:	e7f2      	b.n	8001582 <HAL_UART_Init+0x4e>
 800159c:	ffffb7ff 	.word	0xffffb7ff

080015a0 <Reset_Handler>:

  .section .text.Reset_Handler
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:
  ldr   r0, =_estack
 80015a0:	4813      	ldr	r0, [pc, #76]	; (80015f0 <LoopForever+0x2>)
  mov   sp, r0          /* set stack pointer */
 80015a2:	4685      	mov	sp, r0
  
/* Call the clock system initialization function.*/
  bl  SystemInit
 80015a4:	f7fe ff68 	bl	8000478 <SystemInit>

/*Check if boot space corresponds to test memory*/
 
    LDR R0,=0x00000004
 80015a8:	4812      	ldr	r0, [pc, #72]	; (80015f4 <LoopForever+0x6>)
    LDR R1, [R0]
 80015aa:	6801      	ldr	r1, [r0, #0]
    LSRS R1, R1, #24
 80015ac:	0e09      	lsrs	r1, r1, #24
    LDR R2,=0x1F
 80015ae:	4a12      	ldr	r2, [pc, #72]	; (80015f8 <LoopForever+0xa>)
    CMP R1, R2
 80015b0:	4291      	cmp	r1, r2
    BNE ApplicationStart
 80015b2:	d105      	bne.n	80015c0 <ApplicationStart>

 /*SYSCFG clock enable*/

    LDR R0,=0x40021018
 80015b4:	4811      	ldr	r0, [pc, #68]	; (80015fc <LoopForever+0xe>)
    LDR R1,=0x00000001
 80015b6:	4912      	ldr	r1, [pc, #72]	; (8001600 <LoopForever+0x12>)
    STR R1, [R0]
 80015b8:	6001      	str	r1, [r0, #0]

/*Set CFGR1 register with flash memory remap at address 0*/
    LDR R0,=0x40010000
 80015ba:	4812      	ldr	r0, [pc, #72]	; (8001604 <LoopForever+0x16>)
    LDR R1,=0x00000000
 80015bc:	4912      	ldr	r1, [pc, #72]	; (8001608 <LoopForever+0x1a>)
    STR R1, [R0]
 80015be:	6001      	str	r1, [r0, #0]

080015c0 <ApplicationStart>:

ApplicationStart:
/* Copy the data segment initializers from flash to SRAM */
  ldr r0, =_sdata
 80015c0:	4812      	ldr	r0, [pc, #72]	; (800160c <LoopForever+0x1e>)
  ldr r1, =_edata
 80015c2:	4913      	ldr	r1, [pc, #76]	; (8001610 <LoopForever+0x22>)
  ldr r2, =_sidata
 80015c4:	4a13      	ldr	r2, [pc, #76]	; (8001614 <LoopForever+0x26>)
  movs r3, #0
 80015c6:	2300      	movs	r3, #0
  b LoopCopyDataInit
 80015c8:	e002      	b.n	80015d0 <LoopCopyDataInit>

080015ca <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 80015ca:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 80015cc:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 80015ce:	3304      	adds	r3, #4

080015d0 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 80015d0:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 80015d2:	428c      	cmp	r4, r1
  bcc CopyDataInit
 80015d4:	d3f9      	bcc.n	80015ca <CopyDataInit>
  
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 80015d6:	4a10      	ldr	r2, [pc, #64]	; (8001618 <LoopForever+0x2a>)
  ldr r4, =_ebss
 80015d8:	4c10      	ldr	r4, [pc, #64]	; (800161c <LoopForever+0x2e>)
  movs r3, #0
 80015da:	2300      	movs	r3, #0
  b LoopFillZerobss
 80015dc:	e001      	b.n	80015e2 <LoopFillZerobss>

080015de <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 80015de:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 80015e0:	3204      	adds	r2, #4

080015e2 <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 80015e2:	42a2      	cmp	r2, r4
  bcc FillZerobss
 80015e4:	d3fb      	bcc.n	80015de <FillZerobss>

/* Call static constructors */
  bl __libc_init_array
 80015e6:	f000 f825 	bl	8001634 <__libc_init_array>
/* Call the application's entry point.*/
  bl main
 80015ea:	f7fe feb3 	bl	8000354 <main>

080015ee <LoopForever>:

LoopForever:
    b LoopForever
 80015ee:	e7fe      	b.n	80015ee <LoopForever>
  ldr   r0, =_estack
 80015f0:	20001800 	.word	0x20001800
    LDR R0,=0x00000004
 80015f4:	00000004 	.word	0x00000004
    LDR R2,=0x1F
 80015f8:	0000001f 	.word	0x0000001f
    LDR R0,=0x40021018
 80015fc:	40021018 	.word	0x40021018
    LDR R1,=0x00000001
 8001600:	00000001 	.word	0x00000001
    LDR R0,=0x40010000
 8001604:	40010000 	.word	0x40010000
    LDR R1,=0x00000000
 8001608:	00000000 	.word	0x00000000
  ldr r0, =_sdata
 800160c:	20000000 	.word	0x20000000
  ldr r1, =_edata
 8001610:	2000000c 	.word	0x2000000c
  ldr r2, =_sidata
 8001614:	080016d4 	.word	0x080016d4
  ldr r2, =_sbss
 8001618:	2000000c 	.word	0x2000000c
  ldr r4, =_ebss
 800161c:	20000108 	.word	0x20000108

08001620 <ADC1_IRQHandler>:
 * @retval : None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 8001620:	e7fe      	b.n	8001620 <ADC1_IRQHandler>

08001622 <memset>:
 8001622:	0003      	movs	r3, r0
 8001624:	1882      	adds	r2, r0, r2
 8001626:	4293      	cmp	r3, r2
 8001628:	d100      	bne.n	800162c <memset+0xa>
 800162a:	4770      	bx	lr
 800162c:	7019      	strb	r1, [r3, #0]
 800162e:	3301      	adds	r3, #1
 8001630:	e7f9      	b.n	8001626 <memset+0x4>
	...

08001634 <__libc_init_array>:
 8001634:	b570      	push	{r4, r5, r6, lr}
 8001636:	2600      	movs	r6, #0
 8001638:	4c0c      	ldr	r4, [pc, #48]	; (800166c <__libc_init_array+0x38>)
 800163a:	4d0d      	ldr	r5, [pc, #52]	; (8001670 <__libc_init_array+0x3c>)
 800163c:	1b64      	subs	r4, r4, r5
 800163e:	10a4      	asrs	r4, r4, #2
 8001640:	42a6      	cmp	r6, r4
 8001642:	d109      	bne.n	8001658 <__libc_init_array+0x24>
 8001644:	2600      	movs	r6, #0
 8001646:	f000 f819 	bl	800167c <_init>
 800164a:	4c0a      	ldr	r4, [pc, #40]	; (8001674 <__libc_init_array+0x40>)
 800164c:	4d0a      	ldr	r5, [pc, #40]	; (8001678 <__libc_init_array+0x44>)
 800164e:	1b64      	subs	r4, r4, r5
 8001650:	10a4      	asrs	r4, r4, #2
 8001652:	42a6      	cmp	r6, r4
 8001654:	d105      	bne.n	8001662 <__libc_init_array+0x2e>
 8001656:	bd70      	pop	{r4, r5, r6, pc}
 8001658:	00b3      	lsls	r3, r6, #2
 800165a:	58eb      	ldr	r3, [r5, r3]
 800165c:	4798      	blx	r3
 800165e:	3601      	adds	r6, #1
 8001660:	e7ee      	b.n	8001640 <__libc_init_array+0xc>
 8001662:	00b3      	lsls	r3, r6, #2
 8001664:	58eb      	ldr	r3, [r5, r3]
 8001666:	4798      	blx	r3
 8001668:	3601      	adds	r6, #1
 800166a:	e7f2      	b.n	8001652 <__libc_init_array+0x1e>
 800166c:	080016cc 	.word	0x080016cc
 8001670:	080016cc 	.word	0x080016cc
 8001674:	080016d0 	.word	0x080016d0
 8001678:	080016cc 	.word	0x080016cc

0800167c <_init>:
 800167c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800167e:	46c0      	nop			; (mov r8, r8)
 8001680:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8001682:	bc08      	pop	{r3}
 8001684:	469e      	mov	lr, r3
 8001686:	4770      	bx	lr

08001688 <_fini>:
 8001688:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800168a:	46c0      	nop			; (mov r8, r8)
 800168c:	bcf8      	pop	{r3, r4, r5, r6, r7}
 800168e:	bc08      	pop	{r3}
 8001690:	469e      	mov	lr, r3
 8001692:	4770      	bx	lr