EDA Tool CLI Abstraction Layer.

Post-processing of EDA Tool outputs.

VUnit is a unit testing framework for VHDL/SystemVerilog

VHDL 2008/93/87 simulator

Building and deploying container images for open source electronic design automation (EDA)

An IP-XACT DOM for IEEE 1685-2014 in Python.

An abstract language model of SystemVerilog (incl. Verilog) written in Python.

Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.

Unified Coverage Interoperability Standard (UCIS)

An abstract model of EDA tool projects.

A curated list of awesome resources for HDL design and verification

Repo to help explain the different options users have for packaging.

Electronic design automation (EDA) package recipes for MinGW-w64 (MSYS2)

Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards

Shared resources for smoke testing electronic design automation (EDA) tooling

Reusable steps and workflows for GitHub Actions

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.

cocotb: Python-based chip (RTL) verification

Open Source Verification Bundle for VHDL and System Verilog

Dynamic Binary Hardware Injection

qemu-user-static (qus) and containers, non-invasive minimal working setups

Virtual development board for HDL design

An abstract language model of VHDL written in Python.

This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

Verilog to Routing -- Open Source CAD Flow for FPGA Research

FOSS Flow For FPGA