Variable cannot be driven by a primitive or continuous assignment with non-default strength

[L3odr0id]

Compilation of the following SystemVerilog module throws an error:

module a(output logic c);
  not b(c, d);
endmodule: a

Command:

iverilog -g2012 test.sv

Error output:

test.sv:2: error: variable c; cannot be driven by a primitive or continuous assignment with non-default strength.
1 error(s) during elaboration.

Expected behavior:
This module should be compiled. IEEE-1800 6.5 Nets and variables says

Variables can be written by one or more procedural statements, including procedural continuous
assignments. The last write determines the value. Alternatively, variables can be written by one continuous
assignment or one port.

So variable c could be written by one port (primitive gate output)

This issue occurs in Icarus Verilog version 13.0 (devel) (s20250103-44-gf82c6c7b3)

Found by a verilog model using deptycheck

[caryr]

The BNF is very clear the output can only connect to a net_lvalue, but the following is in 1800-2023 section 10.3.2:

Variables can only be driven by one continuous assignment or by one primitive output or module output.

So this does seem valid and was even mentioned in 1800-2005.