Assertion failed: (ivl_stmt_lvals(net) == 1), function force_link_rval, file vvp_process.c, line 1008.

[shirriff]

I got an assertion failure when I ran iverilog t.v on the attached file.

t.v.txt

Expected behavior: an error message instead of a failure.

Full error:

Assertion failed: (ivl_stmt_lvals(net) == 1), function force_link_rval, file vvp_process.c, line 1008.
sh: line 1: 56097 Done                    /opt/local/lib/ivl/ivlpp -L -F"/var/folders/y0/std_yssd13z9snh48rx3m8l40000gq/T//ivrlg23831d039" -f"/var/folders/y0/std_yssd13z9snh48rx3m8l40000gq/T//ivrlg3831d039" -p"/var/folders/y0/std_yssd13z9snh48rx3m8l40000gq/T//ivrli3831d039"
     56098 Abort trap: 6           | /opt/local/lib/ivl/ivl -C"/var/folders/y0/std_yssd13z9snh48rx3m8l40000gq/T//ivrlh3831d039" -C"/opt/local/lib/ivl/vvp.conf" -- -

I'm using Icarus Verilog version 13.0 (devel) (s20250103) on a MacBook, installed through macports.

I'm not expecting a fix for this, just letting you know in case it is helpful, so feel free to close the issue.

[caryr]

This is a bug in Icarus related to the handling of procedural assign statements with a concatenation as the L-value. Keep in mind the procedural assign/release has been deprecated in recent versions of the SystemVerilog standard and should not be used. If you use a normal procedural assignment this code works except for a bug in the TB.

To get something that will compile replace the:
assign {a, b} = i;
statement with
{a, b} = i;

The TB bug is that you need some delay after assigning the inputs to allow the DUT to generate an output before the $display() so add a #1 like follows:
#1 $display(a, b, out);

[shirriff]

Thank you for your help! As you may have guessed, I'm not a Verilog expert :-)