Multidimensional indicies are not properly supported.

[avgsurfman]

Trying to create byte-enabled memory, like this: (link)

...
//    [shw][sby][dat]    [   word_count   ]
logic [1:0][1:0][7:0] mem[2**MEM_WIDTH-1:0]; // same as [31:0] 

always_ff@(posedge clk_i) begin : mem_write
    // Unfortunately implicit bit truncation will crash your simulation,
    // hence the 7 magic constant instead of 31:2.
    err = 1'b0;
    if(we) begin 
        case(be)
        // sw
        4'b1111: mem[a[7:2]] <= wd; // this is fine
        // sh zone
        4'b1100: mem[a[7:2]][a[1]] <= wd[31:16]; //this works too
        4'b0011: mem[a[7:2]][a[0]] <= wd[15:0]; 
        // sb zone
        4'b1000: mem[a[7:2]][a[1]][a[1]] <= wd[31:24]; //throws an iverilog error but works in other simulators
       ...

Compiles just fine with verilator with no warnings.

Version: Icarus Verilog version 13.0 (devel) ()

[martinwhitaker]

When reporting bugs, please provide a complete test case, cut down to the bare minimum that demonstrates the problem. In this case, this would suffice:

module test();

reg clk;

reg [7:0] a;

reg [31:0] wd;

logic [1:0][1:0][7:0] mem[63:0];

always_ff @(posedge clk) begin
  mem[a[7:2]][a[1]][a[1]] <= wd[31:24];
end

endmodule

(I suspect you meant the minor index to be a[0], not a[1])

This issue is already reported in #521.

[avgsurfman]

#521 I see that this is related but this bug is 4 years old.
Do I close the ticket now? It's clearly still an issue.

[caryr]

Yes, clearly if a bug has not been closed then it has not been fixed.

All the developers currently work on Icarus during our free time and for most of us that has been a rare luxury for quite some time, so getting issues fixed has been slower than we would like.