Signal declaration after use not supported

[MichaelBell]

In iverilog 12, signals can be declared after use. In devel, this is no longer supported.

I'm not sure if declare after use is technically valid, but it would be nice to at least have an option to support it as I have a body of existing code that relies on this style.

I believe the change that introduced this was 649fbb9.

[Wren6991]

For what it's worth, this is invalid Verilog. When you use the wire before declaring, that's an implicit declaration. Later you have an explicit declaration. E.g. 4.2.2 in 1364-2005:

It is illegal to redeclare a name already declared by a net, parameter, or
variable declaration

Commercial simulators like Xcelium will hard error on this, so it's worth cleaning up in your RTL. I'm glad there is now one open-source simulator that complains about it (Yosys/CXXRTL and Verilator both accept it). I guess it would make sense for Icarus to demote it to a warning as the intent is pretty clear, but that's effectively a non-standard extension to Verilog.

[martinwhitaker]

It was never explicitly stated in the IEEE 1364 standard whether variables had to be declared before use, but that standard evolved from the Verilog-XL LRM, and Verilog-XL required it. The first mention I could find in an IEEE standard comes in 1800-2005 section 6.1 which states "SystemVerilog follows Verilog by requiring data to be declared before they are used, apart from implicit nets.". In 1800-2012 and later it is stated more formally in section 6.6 that "Data shall be declared before they are used, apart from implicit nets (see 6.10).".

With nested scopes, it is possible to write code that behaves differently if we allow declaration after use - see the example in #1102. So I would prefer to enforce this.