@@ -757,6 +757,58 @@ static int32_t stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uin
757757 return (ret );
758758}
759759
760+ /**
761+ * Write option bytes L5
762+ * @param sl
763+ * @param addr of the memory mapped option bytes
764+ * @param base option bytes
765+ * @param len of option bytes
766+ * @return 0 on success, -ve on failure.
767+ */
768+ static int32_t stlink_write_option_bytes_l5 (stlink_t * sl , stm32_addr_t addr ,
769+ uint8_t * base , uint32_t len ) {
770+ /* Write options bytes */
771+ uint32_t val ;
772+ int32_t ret = 0 ;
773+ (void )len ;
774+ uint32_t data ;
775+
776+ clear_flash_error (sl );
777+
778+ while (len != 0 ) {
779+ write_uint32 ((unsigned char * )& data ,
780+ * (uint32_t * )(base )); // write options bytes
781+
782+ WLOG ("Writing option bytes %#10x to %#10x\n" , data , addr );
783+ stlink_write_debug32 (sl , addr , data );
784+ wait_flash_busy (sl );
785+
786+ if ((ret = check_flash_error (sl ))) {
787+ break ;
788+ }
789+
790+ len -= 4 ;
791+ addr += 4 ;
792+ base += 4 ;
793+ }
794+
795+ // Set Options Start bit
796+ stlink_read_debug32 (sl , STM32_FLASH_L5_NSCR , & val );
797+ val |= (1 << STM32_FLASH_L5_NSCR_NSOPTSTRT );
798+ stlink_write_debug32 (sl , STM32_FLASH_L5_NSCR , val );
799+
800+ wait_flash_busy (sl );
801+
802+ ret = check_flash_error (sl );
803+
804+ // Reload options
805+ stlink_read_debug32 (sl , STM32_FLASH_L5_NSCR , & val );
806+ val |= (1 << STM32_FLASH_L5_NSCR_OBL_LAUNCH );
807+ stlink_write_debug32 (sl , STM32_FLASH_L5_NSCR , val );
808+
809+ return (ret );
810+ }
811+
760812/**
761813 * Read option control register WB
762814 * @param sl
@@ -880,6 +932,9 @@ int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base
880932 case STM32_FLASH_TYPE_WB_WL :
881933 ret = stlink_write_option_bytes_wb (sl , addr , base , len );
882934 break ;
935+ case STM32_FLASH_TYPE_L5_U5_H5 :
936+ ret = stlink_write_option_bytes_l5 (sl , addr , base , len );
937+ break ;
883938 default :
884939 ELOG ("Option bytes writing is currently not implemented for connected chip\n" );
885940 break ;
0 commit comments