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fix(h5): review SPI input clock
Also prevent to use HSE as it is not operational as oscillator. See Errata sheet. Fixes #2598 Signed-off-by: Frederic Pillon <[email protected]>
1 parent a2e6705 commit 4daecca

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3 files changed

+37
-24
lines changed

3 files changed

+37
-24
lines changed

Diff for: variants/STM32H5xx/H503CB(T-U)/generic_clock.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ WEAK void SystemClock_Config(void)
4747
RCC_OscInitStruct.PLL.PLLM = 1;
4848
RCC_OscInitStruct.PLL.PLLN = 125;
4949
RCC_OscInitStruct.PLL.PLLP = 2;
50-
RCC_OscInitStruct.PLL.PLLQ = 2;
50+
RCC_OscInitStruct.PLL.PLLQ = 10;
5151
RCC_OscInitStruct.PLL.PLLR = 2;
5252
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
5353
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;

Diff for: variants/STM32H5xx/H503RBT/generic_clock.c

+6-2
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ WEAK void SystemClock_Config(void)
4343
RCC_OscInitStruct.PLL.PLLM = 1;
4444
RCC_OscInitStruct.PLL.PLLN = 125;
4545
RCC_OscInitStruct.PLL.PLLP = 2;
46-
RCC_OscInitStruct.PLL.PLLQ = 2;
46+
RCC_OscInitStruct.PLL.PLLQ = 10;
4747
RCC_OscInitStruct.PLL.PLLR = 2;
4848
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
4949
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
@@ -64,6 +64,10 @@ WEAK void SystemClock_Config(void)
6464
Error_Handler();
6565
}
6666

67+
/** Configure the programming delay
68+
*/
69+
__HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
70+
6771
/* Initializes the peripherals clock */
6872
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1
6973
| RCC_PERIPHCLK_USB;
@@ -72,7 +76,7 @@ WEAK void SystemClock_Config(void)
7276
PeriphClkInitStruct.PLL2.PLL2N = 125;
7377
PeriphClkInitStruct.PLL2.PLL2P = 2;
7478
PeriphClkInitStruct.PLL2.PLL2Q = 15;
75-
PeriphClkInitStruct.PLL2.PLL2R = 4;
79+
PeriphClkInitStruct.PLL2.PLL2R = 10;
7680
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2;
7781
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE;
7882
PeriphClkInitStruct.PLL2.PLL2FRACN = 0;

Diff for: variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp

+30-21
Original file line numberDiff line numberDiff line change
@@ -114,20 +114,25 @@ WEAK void SystemClock_Config(void)
114114

115115
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
116116

117+
/** Configure LSE Drive Capability
118+
* Warning : Only applied when the LSE is disabled.
119+
*/
120+
HAL_PWR_EnableBkUpAccess();
121+
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
122+
117123
/* Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */
118-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE
119-
| RCC_OSCILLATORTYPE_LSE;
120-
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
124+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_CSI;
121125
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
122-
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
126+
RCC_OscInitStruct.CSIState = RCC_CSI_ON;
127+
RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
123128
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
124-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
125-
RCC_OscInitStruct.PLL.PLLM = 12;
126-
RCC_OscInitStruct.PLL.PLLN = 250;
129+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI;
130+
RCC_OscInitStruct.PLL.PLLM = 1;
131+
RCC_OscInitStruct.PLL.PLLN = 125;
127132
RCC_OscInitStruct.PLL.PLLP = 2;
128-
RCC_OscInitStruct.PLL.PLLQ = 2;
133+
RCC_OscInitStruct.PLL.PLLQ = 10;
129134
RCC_OscInitStruct.PLL.PLLR = 2;
130-
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1;
135+
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
131136
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
132137
RCC_OscInitStruct.PLL.PLLFRACN = 0;
133138
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
@@ -148,23 +153,27 @@ WEAK void SystemClock_Config(void)
148153
Error_Handler();
149154
}
150155

156+
/** Configure the programming delay
157+
*/
158+
__HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
159+
151160
/* Initializes the peripherals clock */
152-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1
153-
| RCC_PERIPHCLK_USB;
154-
PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE;
155-
PeriphClkInitStruct.PLL2.PLL2M = 2;
156-
PeriphClkInitStruct.PLL2.PLL2N = 31;
157-
PeriphClkInitStruct.PLL2.PLL2P = 2;
158-
PeriphClkInitStruct.PLL2.PLL2Q = 12;
161+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADCDAC
162+
| RCC_PERIPHCLK_LPUART1;
163+
PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI;
164+
PeriphClkInitStruct.PLL2.PLL2M = 1;
165+
PeriphClkInitStruct.PLL2.PLL2N = 36;
166+
PeriphClkInitStruct.PLL2.PLL2P = 3;
167+
PeriphClkInitStruct.PLL2.PLL2Q = 4;
159168
PeriphClkInitStruct.PLL2.PLL2R = 3;
160-
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_3;
169+
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2;
161170
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE;
162-
PeriphClkInitStruct.PLL2.PLL2FRACN = 2048;
163-
PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR;
171+
PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
172+
PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVP | RCC_PLL2_DIVQ
173+
| RCC_PLL2_DIVR;
164174
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q;
165175
PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
166-
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
167-
176+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL2Q;
168177
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
169178
Error_Handler();
170179
}

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