From d8a556f346ff27d31d2971a686ec6abb2e1f2193 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 10 Jan 2025 11:18:19 +0100 Subject: [PATCH 1/2] system(U5) update STM32U5xx HAL Drivers to v1.6.1 Included in STM32CubeU5 FW v1.7.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 84 +- .../STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h | 38 +- .../Inc/stm32u5xx_hal_comp.h | 10 +- .../Inc/stm32u5xx_hal_cordic.h | 21 +- .../Inc/stm32u5xx_hal_cortex.h | 70 +- .../Inc/stm32u5xx_hal_cryp.h | 28 +- .../Inc/stm32u5xx_hal_dac.h | 11 +- .../Inc/stm32u5xx_hal_dcmi.h | 2 +- .../Inc/stm32u5xx_hal_def.h | 4 +- .../Inc/stm32u5xx_hal_dma.h | 1 - .../Inc/stm32u5xx_hal_dsi.h | 6 +- .../Inc/stm32u5xx_hal_fdcan.h | 4 +- .../Inc/stm32u5xx_hal_fmac.h | 12 +- .../Inc/stm32u5xx_hal_gfxmmu.h | 14 +- .../Inc/stm32u5xx_hal_hash.h | 60 +- .../Inc/stm32u5xx_hal_hash_ex.h | 64 +- .../Inc/stm32u5xx_hal_lptim.h | 2 + .../Inc/stm32u5xx_hal_mmc.h | 4 +- .../Inc/stm32u5xx_hal_mmc_ex.h | 6 +- .../Inc/stm32u5xx_hal_pcd.h | 8 + .../Inc/stm32u5xx_hal_pcd_ex.h | 1 - .../Inc/stm32u5xx_hal_rng.h | 1 + .../Inc/stm32u5xx_hal_rng_ex.h | 38 +- .../Inc/stm32u5xx_hal_rtc.h | 7 + .../Inc/stm32u5xx_hal_sd.h | 4 +- .../Inc/stm32u5xx_hal_sd_ex.h | 4 +- .../Inc/stm32u5xx_hal_sdio.h | 24 +- .../Inc/stm32u5xx_hal_spi.h | 7 + .../Inc/stm32u5xx_hal_tim.h | 40 +- .../Inc/stm32u5xx_hal_uart.h | 6 +- .../Inc/stm32u5xx_hal_uart_ex.h | 2 - .../Inc/stm32u5xx_hal_usart.h | 5 +- .../Inc/stm32u5xx_hal_usart_ex.h | 2 +- .../Inc/stm32u5xx_hal_xspi.h | 136 ++- .../Inc/stm32u5xx_ll_adc.h | 107 +-- .../Inc/stm32u5xx_ll_cordic.h | 28 +- .../Inc/stm32u5xx_ll_cortex.h | 64 +- .../Inc/stm32u5xx_ll_fmac.h | 6 - .../Inc/stm32u5xx_ll_lptim.h | 21 +- .../Inc/stm32u5xx_ll_opamp.h | 14 +- .../Inc/stm32u5xx_ll_rng.h | 41 +- .../Inc/stm32u5xx_ll_sdmmc.h | 10 +- .../Inc/stm32u5xx_ll_system.h | 793 +++++++++++++++--- .../Inc/stm32u5xx_ll_tim.h | 18 +- .../Inc/stm32u5xx_ll_ucpd.h | 61 +- .../Inc/stm32u5xx_ll_usb.h | 2 +- .../STM32U5xx_HAL_Driver/Release_Notes.html | 203 ++++- .../STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c | 50 +- .../Src/stm32u5xx_hal_cordic.c | 2 +- .../Src/stm32u5xx_hal_cortex.c | 22 +- .../Src/stm32u5xx_hal_crc_ex.c | 2 - .../Src/stm32u5xx_hal_cryp.c | 144 +++- .../Src/stm32u5xx_hal_cryp_ex.c | 70 +- .../Src/stm32u5xx_hal_dac.c | 8 + .../Src/stm32u5xx_hal_dcmi.c | 10 +- .../Src/stm32u5xx_hal_dma_ex.c | 18 +- .../Src/stm32u5xx_hal_dsi.c | 8 +- .../Src/stm32u5xx_hal_fdcan.c | 4 +- .../Src/stm32u5xx_hal_fmac.c | 24 +- .../Src/stm32u5xx_hal_gfxmmu.c | 17 +- .../Src/stm32u5xx_hal_gtzc.c | 2 +- .../Src/stm32u5xx_hal_hash.c | 78 +- .../Src/stm32u5xx_hal_hash_ex.c | 64 +- .../Src/stm32u5xx_hal_hcd.c | 44 +- .../Src/stm32u5xx_hal_i2c.c | 67 +- .../Src/stm32u5xx_hal_iwdg.c | 3 +- .../Src/stm32u5xx_hal_lptim.c | 4 +- .../Src/stm32u5xx_hal_mmc.c | 7 +- .../Src/stm32u5xx_hal_mmc_ex.c | 6 +- .../Src/stm32u5xx_hal_ospi.c | 11 +- .../Src/stm32u5xx_hal_pcd.c | 44 +- .../Src/stm32u5xx_hal_pcd_ex.c | 2 - .../Src/stm32u5xx_hal_pka.c | 30 +- .../Src/stm32u5xx_hal_pwr.c | 10 +- .../Src/stm32u5xx_hal_pwr_ex.c | 16 +- .../Src/stm32u5xx_hal_rcc.c | 19 + .../Src/stm32u5xx_hal_rng.c | 16 +- .../Src/stm32u5xx_hal_rng_ex.c | 15 +- .../Src/stm32u5xx_hal_rtc.c | 54 +- .../Src/stm32u5xx_hal_sd.c | 4 +- .../Src/stm32u5xx_hal_sd_ex.c | 6 +- .../Src/stm32u5xx_hal_sdio.c | 73 +- .../Src/stm32u5xx_hal_smartcard.c | 56 ++ .../Src/stm32u5xx_hal_spi.c | 415 +++++++-- .../Src/stm32u5xx_hal_spi_ex.c | 1 - .../Src/stm32u5xx_hal_tim.c | 14 +- .../Src/stm32u5xx_hal_tim_ex.c | 52 +- .../Src/stm32u5xx_hal_uart.c | 34 +- .../Src/stm32u5xx_hal_uart_ex.c | 18 +- .../Src/stm32u5xx_hal_usart.c | 17 +- .../Src/stm32u5xx_hal_usart_ex.c | 2 +- .../Src/stm32u5xx_hal_xspi.c | 53 +- .../Src/stm32u5xx_ll_dma.c | 10 +- .../Src/stm32u5xx_ll_fmac.c | 2 - .../Src/stm32u5xx_ll_opamp.c | 2 +- .../Src/stm32u5xx_ll_rng.c | 2 +- .../Src/stm32u5xx_ll_sdmmc.c | 6 +- .../Src/stm32u5xx_ll_tim.c | 30 +- .../Src/stm32u5xx_ll_ucpd.c | 2 +- .../Src/stm32u5xx_ll_usb.c | 122 +-- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 101 files changed, 2730 insertions(+), 1158 deletions(-) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index d10f6f6f89..cf3942e283 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -806,6 +817,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -860,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -997,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1249,10 +1279,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1264,10 +1294,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1817,7 +1847,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1999,12 +2029,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -2731,6 +2761,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3659,7 +3695,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3910,7 +3946,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4204,6 +4241,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h index 08fef12a8b..a779890d07 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h @@ -143,10 +143,22 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ +/** + * @} + */ +#if defined(SYSCFG_CFGR1_ENDCAP) +/** @defgroup SYSCFG_DECOUPLING_CAPACITANCE SYSCFG DECOUPLING CAPACITANCE + * @{ + */ +#define SYSCFG_HSPI_CAPACITANCE_OFF 0x00000000U /*!< Decoupling with no capacitance value on HSPI supply */ +#define SYSCFG_HSPI_CAPACITANCE_1_DIV_3 SYSCFG_CFGR1_ENDCAP_0 /*!< Decoupling with 1/3 of capacitance value on HSPI supply */ +#define SYSCFG_HSPI_CAPACITANCE_2_DIV_3 SYSCFG_CFGR1_ENDCAP_1 /*!< Decoupling with 2/3 of capacitance value on HSPI supply */ +#define SYSCFG_HSPI_CAPACITANCE_FULL SYSCFG_CFGR1_ENDCAP /*!< Decoupling with full capacitance value on HSPI supply */ /** * @} */ +#endif /* SYSCFG_CFGR1_ENDCAP */ /** @defgroup SYSCFG_Lock_items SYSCFG Lock items * @brief SYSCFG items to set lock on @@ -620,8 +632,14 @@ extern HAL_TickFreqTypeDef uwTickFreq; (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#if defined(SYSCFG_CFGR1_ENDCAP) +#define IS_SYSCFG_DECOUPLING_CAPACITANCE(__CAPA__) (((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_OFF) || \ + ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_1_DIV_3) || \ + ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_2_DIV_3) || \ + ((__CAPA__) == SYSCFG_HSPI_CAPACITANCE_FULL)) +#endif /* SYSCFG_CFGR1_ENDCAP */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ ((__ATTRIBUTES__) == SYSCFG_NSEC)) @@ -642,11 +660,9 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) - - #endif /* __ARM_FEATURE_CMSE */ -#ifdef SYSCFG_OTGHSPHYCR_EN +#if defined SYSCFG_OTGHSPHYCR_EN #define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \ ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \ ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \ @@ -750,8 +766,6 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); */ /* SYSCFG Control functions ****************************************************/ -void HAL_SYSCFG_SRAM2Erase(void); - void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); @@ -765,10 +779,14 @@ void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); #endif /* SYSCFG_OTGHSPHYCR_EN */ -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); -void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void); -void HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection(void); +void HAL_SYSCFG_EnableIOAnalogBooster(void); +void HAL_SYSCFG_DisableIOAnalogBooster(void); +void HAL_SYSCFG_EnableIOAnalogVoltageSelection(void); +void HAL_SYSCFG_DisableIOAnalogVoltageSelection(void); +#if defined(SYSCFG_CFGR1_ENDCAP) +void HAL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance); +uint32_t HAL_SYSCFG_GetHSPIDecouplingCapacitance(void); +#endif /* SYSCFG_CFGR1_ENDCAP */ void HAL_SYSCFG_EnableSRAMCached(void); void HAL_SYSCFG_DisableSRAMCached(void); void HAL_SYSCFG_EnableVddCompensationCell(void); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h index 7220ae1737..423a1c1f19 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_comp.h @@ -753,11 +753,11 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /* Exported functions --------------------------------------------------------*/ -/** @addtogroup COMP_Exported_Functions COMP Exported Functions +/** @addtogroup COMP_Exported_Functions * @{ */ -/** @addtogroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions +/** @addtogroup COMP_Exported_Functions_Group1 * @{ */ @@ -778,7 +778,7 @@ HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COM */ /* IO operation functions *****************************************************/ -/** @addtogroup COMP_Exported_Functions_Group2 Start-Stop operation functions +/** @addtogroup COMP_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); @@ -789,7 +789,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); */ /* Peripheral Control functions ************************************************/ -/** @addtogroup COMP_Exported_Functions_Group3 Peripheral Control functions +/** @addtogroup COMP_Exported_Functions_Group3 * @{ */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); @@ -801,7 +801,7 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); */ /* Peripheral State functions **************************************************/ -/** @addtogroup COMP_Exported_Functions_Group4 Peripheral State functions +/** @addtogroup COMP_Exported_Functions_Group4 * @{ */ HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cordic.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cordic.h index f489238642..315b3b4390 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cordic.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cordic.h @@ -149,7 +149,6 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants * @{ @@ -166,6 +165,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + /** * @} */ @@ -183,6 +183,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */ #define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */ #define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */ + /** * @} */ @@ -212,6 +213,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ |CORDIC_CSR_PRECISION_0)) + /** * @} */ @@ -229,6 +231,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0)) #define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1)) #define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) + /** * @} */ @@ -237,6 +240,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */ + /** * @} */ @@ -245,6 +249,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */ + /** * @} */ @@ -253,6 +258,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */ + /** * @} */ @@ -288,6 +294,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */ #define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */ + /** * @} */ @@ -297,6 +304,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */ #define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */ + /** * @} */ @@ -305,6 +313,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */ + /** * @} */ @@ -316,6 +325,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */ #define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */ #define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */ + /** * @} */ @@ -336,9 +346,9 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET) @@ -416,7 +426,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ -/* Private macros --------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /** @defgroup CORDIC_Private_Macros CORDIC Private Macros * @{ */ @@ -584,6 +594,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic); /* Peripheral State functions *************************************************/ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic); uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic); + /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h index 0e0e4fd4bd..7670159f27 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h @@ -123,10 +123,10 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE 0U -#define MPU_HARDFAULT_NMI 2U -#define MPU_PRIVILEGED_DEFAULT 4U -#define MPU_HFNMI_PRIVDEF 6U +#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -134,8 +134,8 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ -#define MPU_REGION_ENABLE 1U -#define MPU_REGION_DISABLE 0U +#define MPU_REGION_ENABLE 1U /*!< Enable region */ +#define MPU_REGION_DISABLE 0U /*!< Disable region */ /** * @} */ @@ -143,8 +143,8 @@ typedef struct /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ -#define MPU_INSTRUCTION_ACCESS_ENABLE 0U -#define MPU_INSTRUCTION_ACCESS_DISABLE 1U +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */ +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */ /** * @} */ @@ -152,9 +152,9 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ -#define MPU_ACCESS_NOT_SHAREABLE 0U -#define MPU_ACCESS_OUTER_SHAREABLE 2U -#define MPU_ACCESS_INNER_SHAREABLE 3U +#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */ +#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */ +#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */ /** * @} */ @@ -162,10 +162,10 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_PRIV_RW 0U -#define MPU_REGION_ALL_RW 1U -#define MPU_REGION_PRIV_RO 2U -#define MPU_REGION_ALL_RO 3U +#define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */ +#define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */ +#define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */ +#define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */ /** * @} */ @@ -203,22 +203,30 @@ typedef struct /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes * @{ */ -#define MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ - -#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ -#define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - -#define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ -#define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - -#define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ -#define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ -#define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ -#define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/* Device memory attributes */ +#define MPU_DEVICE_NGNRNE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define MPU_DEVICE_NGNRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define MPU_DEVICE_NGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* To set with INNER_OUTER() macro for both inner/outer cache attributes */ + +/* Non-cacheable memory attribute */ +#define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */ +#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */ +/* - transient mode attribute */ +#define MPU_TRANSIENT 0x0U /*!< Normal memory, transient */ +#define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */ +/* - allocation attribute */ +#define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */ +#define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */ +#define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */ +#define MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */ /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h index a7c0a5589c..015418e3a3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cryp.h @@ -484,25 +484,25 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @arg @ref CRYP_FLAG_KEIF Key error flag * @arg @ref CRYP_FLAG_RWEIF Read/write Error flag - * @retval The state of __FLAG__ (TRUE or FALSE). + * @retval The state of __FLAG__ (FlagStatus). */ #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (\ - ((__FLAG__) == CRYP_FLAG_KEYVALID )?(((__HANDLE__)->Instance->SR \ - & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \ - ((__FLAG__) == CRYP_FLAG_BUSY )?(((__HANDLE__)->Instance->SR \ - & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \ - ((__FLAG__) == CRYP_FLAG_WRERR )?(((__HANDLE__)->Instance->SR \ + ((__FLAG__) == CRYP_FLAG_KEYVALID )?((((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_BUSY )?((((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_WRERR )?((((__HANDLE__)->Instance->SR \ & (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) == \ - (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) : \ - ((__FLAG__) == CRYP_FLAG_RDERR )?(((__HANDLE__)->Instance->SR \ + (CRYP_FLAG_WRERR & 0x7FFFFFFFU))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_RDERR )?((((__HANDLE__)->Instance->SR \ & (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) == \ - (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) : \ - ((__FLAG__) == CRYP_FLAG_KEIF )?(((__HANDLE__)->Instance->ISR \ - & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF)) : \ - ((__FLAG__) == CRYP_FLAG_RWEIF )?(((__HANDLE__)->Instance->ISR \ - & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF)) : \ - (((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF))) + (CRYP_FLAG_RDERR & 0x7FFFFFFFU))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_KEIF )?((((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF))?SET:RESET) : \ + ((__FLAG__) == CRYP_FLAG_RWEIF )?((((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF))?SET:RESET) : \ + ((((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF)))?SET:RESET) /** @brief Clear the CRYP pending status flag. * @param __HANDLE__ specifies the CRYP handle. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h index cb23c4d9c3..bdd6bb9f74 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dac.h @@ -291,10 +291,13 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) -#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) -#define DAC_CHIPCONNECT_BOTH (1UL << 2) - +#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/ +#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. */ +#define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. + Note: this connection is not available in mode normal + with buffer disabled. */ /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcmi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcmi.h index 017e9108d3..24020a2f6c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcmi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dcmi.h @@ -574,7 +574,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0 uint32_t YSize); HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi); HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi); -HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask); +HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, const DCMI_SyncUnmaskTypeDef *SyncUnmask); /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h index 043f0df60a..5fac6913cf 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h @@ -174,7 +174,7 @@ typedef enum /** * @brief __RAM_FUNC definition */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) /* ARM Compiler ------------ @@ -207,7 +207,7 @@ typedef enum /** * @brief __NOINLINE definition */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) /* ARM & GNUCompiler ---------------- */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h index 72153b44e9..a15d4fe8cf 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h @@ -561,7 +561,6 @@ typedef struct __DMA_HandleTypeDef */ - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dsi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dsi.h index 29a8e549ec..cbb6e35ffd 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dsi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dsi.h @@ -1246,7 +1246,7 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t NbParams, uint32_t Param1, - uint8_t *ParametersTable); + const uint8_t *ParametersTable); HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, uint32_t ChannelNbr, uint8_t *Array, @@ -1274,8 +1274,8 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane * @brief Peripheral State and Errors functions * @{ */ -uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); -HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); +uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi); +HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi); /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fdcan.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fdcan.h index 9a8741bbbf..0ddede43a2 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fdcan.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fdcan.h @@ -517,8 +517,8 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ -#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ -#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Put element in full FIFO */ #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fmac.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fmac.h index da7ed7596c..3641a3e164 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fmac.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_fmac.h @@ -243,10 +243,7 @@ typedef struct * @} */ - /* Exported constants --------------------------------------------------------*/ - - /** @defgroup FMAC_Exported_Constants FMAC Exported Constants * @{ */ @@ -357,7 +354,6 @@ typedef struct * @} */ - /* Exported variables --------------------------------------------------------*/ /** @defgroup FMAC_Exported_variables FMAC Exported variables * @{ @@ -499,7 +495,7 @@ typedef struct * @} */ -/* Private Macros-----------------------------------------------------------*/ +/* Private Macros-------------------------------------------------------------*/ /** @addtogroup FMAC_Private_Macros FMAC Private Macros * @{ */ @@ -578,9 +574,9 @@ typedef struct * @param __FUNCTION__ ID of the filter function. * @retval SET (__Q__ is a valid value) or RESET (__Q__ is invalid) */ -#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ - (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ - (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) ) +#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ + (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ + (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX)))) /** * @brief Verify the FMAC filter parameter R. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gfxmmu.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gfxmmu.h index b06c3dceae..0e7de3faf2 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gfxmmu.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gfxmmu.h @@ -379,28 +379,28 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf * @{ */ /* Operation functions ********************************************************/ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address); -HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber); -HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_LutLineTypeDef *lutLine); #if defined(GFXMMU_CR_CE) HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam); HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu, - GFXMMU_CachePrefetchTypeDef *CachePrefetch); + const GFXMMU_CachePrefetchTypeDef *CachePrefetch); #endif /* GFXMMU_CR_CE */ -HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers); +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_BuffersTypeDef *Buffers); #if defined(GFXMMU_CR_ACE) HAL_StatusTypeDef HAL_GFXMMU_ModifyAddressCache(GFXMMU_HandleTypeDef *hgfxmmu, - GFXMMU_AddressCacheTypeDef *AddressCache); + const GFXMMU_AddressCacheTypeDef *AddressCache); #endif /* GFXMMU_CR_ACE */ void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu); @@ -414,7 +414,7 @@ void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu); * @{ */ /* State function *************************************************************/ -HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu); +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu); uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash.h index 2f02a3f675..72dc629173 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash.h @@ -117,13 +117,13 @@ typedef struct { HASH_InitTypeDef Init; /*!< HASH required parameters */ - uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ + uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ - uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ + uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ uint32_t HashBuffSize; /*!< Size of buffer to be processed */ @@ -476,15 +476,15 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS /* HASH processing using polling *********************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); @@ -497,15 +497,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p */ /* HASH processing using IT **************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** @@ -517,9 +517,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); */ /* HASH processing using DMA *************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -531,9 +531,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu */ /* HASH-MAC processing using polling *****************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -544,9 +544,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @{ */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -558,8 +558,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ /* HASH-HMAC processing using DMA ********************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -594,19 +594,19 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); */ /* Private functions */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm); /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash_ex.h index 3e26a61c46..adda0f89e4 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_hash_ex.h @@ -50,15 +50,15 @@ extern "C" { * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -69,15 +69,15 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -87,9 +87,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin /** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -99,9 +99,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -111,9 +111,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -124,8 +124,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -135,20 +135,20 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h index 0a6423dde0..06358af1a6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_lptim.h @@ -220,6 +220,7 @@ typedef struct __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ __IO HAL_LPTIM_ChannelStateTypeDef ChannelState[2]; /*!< LPTIM channel operation state */ + #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */ void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */ @@ -616,6 +617,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Write the passed parameter in the Autoreload register. * @param __HANDLE__ LPTIM handle * @param __VALUE__ Autoreload value + * This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF. * @retval None * @note The ARR register can only be modified when the LPTIM instance is enabled. */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h index 892676b7a0..385cfc33b1 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc.h @@ -717,9 +717,9 @@ HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_Parti * @{ */ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc_ex.h index 9aca5ee185..3289331d10 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mmc_ex.h @@ -69,9 +69,11 @@ extern "C" { /** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions * @{ */ -HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, SDMMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, + const MMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, SDMMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, + const MMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks); HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_BuildNode(MMC_DMALinkNodeTypeDef *pNode, diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h index 62741b5ec5..a7958a58fc 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h @@ -508,6 +508,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); #define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND #define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_OUT_STATUS USB_DRD_CLEAR_CHEP_KIND /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h index ab2bb878e0..60e75c07f6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h @@ -45,7 +45,6 @@ extern "C" { /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ - #if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h index c6610c709f..d0847d18d3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng.h @@ -178,6 +178,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h index a01303c1ba..807d02f26b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -55,11 +55,11 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ uint32_t AutoReset; /*!< automatic reset When a noise source error occurs - value of @ref RNG_Ex_Auto_Reset */ + value of @ref RNGEx_Auto_Reset */ uint32_t HealthTest; /*!< RNG health test control must be a value between 0x0FFCABFF and 0x00005200 */ uint32_t NoiseSource; /*!< RNG noise source control(Oscillator Enable signals) @@ -71,11 +71,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -114,7 +114,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -123,7 +123,7 @@ typedef struct /** * @} */ -/** @defgroup RNG_Ex_Auto_Reset Auto Reset configuration +/** @defgroup RNGEx_Auto_Reset Auto Reset configuration * @{ */ #define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/ @@ -138,7 +138,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -147,7 +147,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -156,7 +156,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -165,7 +165,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -204,7 +204,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -213,11 +213,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Exported_Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); @@ -228,7 +228,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc.h index 69cb662c83..b81e33e4db 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rtc.h @@ -742,6 +742,13 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to */ #define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS)) +/** + * @brief Get RTC Binary mode. + * @param __HANDLE__ specifies the RTC handle. + * @retval The selected RTC Binary mode (RTC_BINARY_NONE, RTC_BINARY_ONLY, or RTC_BINARY_MIX). + */ +#define __HAL_RTC_GET_BINARY_MODE(__HANDLE__) (READ_REG(RTC->ICSR & RTC_ICSR_BIN)) + /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd.h index 952df68764..bae7bc2772 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd.h @@ -687,10 +687,10 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t * @{ */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd_ex.h index 18e89ad8e0..cc2de072fa 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sd_ex.h @@ -69,9 +69,9 @@ extern "C" { /** @defgroup SDEx_Exported_Functions_Group1 Linked List functions * @{ */ -HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SD_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, const SD_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SD_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, const SD_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks); HAL_StatusTypeDef HAL_SDEx_DMALinkedList_BuildNode(SD_DMALinkNodeTypeDef *pNode, SD_DMALinkNodeConfTypeDef *pNodeConf); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sdio.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sdio.h index 0368251abe..f51f6806b0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sdio.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_sdio.h @@ -6,7 +6,7 @@ ********************************************************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -154,12 +154,13 @@ typedef struct __SDIO_HandleTypeDef void (* ErrorCallback)(struct __SDIO_HandleTypeDef *hsdio); void (* MspInitCallback)(struct __SDIO_HandleTypeDef *hsdio); void (* MspDeInitCallback)(struct __SDIO_HandleTypeDef *hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ #if (USE_SDIO_TRANSCEIVER != 0U) void (* DriveTransceiver_1_8V_Callback)(struct __SDIO_HandleTypeDef *hsdio, FlagStatus status); #endif /* USE_SDIO_TRANSCEIVER */ -#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + HAL_StatusTypeDef(* SDIO_IdentifyCard)(struct __SDIO_HandleTypeDef *hsdio); } SDIO_HandleTypeDef; @@ -186,14 +187,16 @@ typedef enum * @{ */ typedef void (*pSDIO_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio); -#if (USE_SDIO_TRANSCEIVER != 0U) -typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status); -#endif /* USE_SDIO_TRANSCEIVER */ /** * @} */ #endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ +#if (USE_SDIO_TRANSCEIVER != 0U) +typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + +typedef HAL_StatusTypeDef(*pSDIO_IdentifyCardCallbackTypeDef)(SDIO_HandleTypeDef *hsdio); typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, uint32_t func); /** * @} @@ -213,9 +216,7 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u #define HAL_SDIO_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ #define HAL_SDIO_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ #define HAL_SDIO_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ -#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) #define HAL_SDIO_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ -#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ /** * @} */ @@ -289,7 +290,7 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u * @} */ -/** @defgroup SDIO_Exported_Constansts_Group8 SDIO Data block size enumeration +/** @defgroup SDIO_Exported_Constansts_Group8 SDIO Bus Width enumeration * @{ */ #define HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED 0U /*!< SDIO bus width 8 bit is not supported */ @@ -470,16 +471,19 @@ HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ pSDIO_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ #if (USE_SDIO_TRANSCEIVER != 0U) HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio, pSDIO_TransceiverCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio); #endif /* USE_SDIO_TRANSCEIVER */ -#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction, - HAL_SDIO_IOFunction_CallbackTypeDef Callback); + HAL_SDIO_IOFunction_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_IdentifyCardCallbackTypeDef pCallback); /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h index bbc186528d..24fa33d53a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h @@ -1083,6 +1083,9 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ ((LENGTH) == SPI_CRC_LENGTH_4BIT)) + +#define IS_SPI_LIMITED_TRANSFER_SIZE(SIZE) (((SIZE) < 0x3FFU) && ((SIZE) != 0U)) + /** * @brief CRC Length for limited instance */ @@ -1092,6 +1095,8 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) +#define IS_SPI_CRC_POLYNOMIAL_SIZE(POLYNOM, LENGTH) (((POLYNOM) >> (((LENGTH) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL) + #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ @@ -1105,6 +1110,8 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); #define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) + +#define IS_SPI_TRANSFER_SIZE(SIZE) (((SIZE) < 0xFFFFU) && ((SIZE) != 0U)) /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h index e5919c183d..bbe19eb398 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h @@ -416,29 +416,28 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ @@ -1964,9 +1963,11 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ - (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ - ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + ((READ_BIT((__HANDLE__)->Instance->CR1, TIM_CR1_DITHEN) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x000FFFEFU))) : \ + ((__PERIOD__) > 0U )) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -2025,7 +2026,6 @@ mode. #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h index 1460ba821b..240c76c5ae 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h @@ -292,7 +292,6 @@ typedef enum HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ - HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ @@ -1217,7 +1216,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1232,8 +1231,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h index fd29060dd7..062bc86ba6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h @@ -239,8 +239,6 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @{ */ -void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); - void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h index 36b95bbe4f..d08fef2034 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart.h @@ -142,7 +142,7 @@ typedef struct __USART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value + uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value of @ref USARTEx_Slave_Mode */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value @@ -708,8 +708,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h index 9a80671cb3..55deb3151d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_usart_ex.h @@ -72,7 +72,7 @@ typedef struct * @{ */ #define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ #define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h index 8014fe488d..0e3e1edf2f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_xspi.h @@ -393,38 +393,38 @@ typedef struct /** @defgroup XSPI_MemorySize XSPI Memory Size * @{ */ -#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Byte = 2^( 0+1)) */ -#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Byte = 2^( 1+1)) */ -#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Byte = 2^( 2+1)) */ -#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Byte = 2^( 3+1)) */ -#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Byte = 2^( 4+1)) */ -#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Byte = 2^( 5+1)) */ -#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Byte = 2^( 6+1)) */ -#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Byte = 2^( 7+1)) */ -#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Byte = 2^( 8+1)) */ -#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KByte = 2^( 9+1)) */ -#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KByte = 2^(10+1)) */ -#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KByte = 2^(11+1)) */ -#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KByte = 2^(12+1)) */ -#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KByte = 2^(13+1)) */ -#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KByte = 2^(14+1)) */ -#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KByte = 2^(15+1)) */ -#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KByte = 2^(16+1)) */ -#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KByte = 2^(17+1)) */ -#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KByte = 2^(18+1)) */ -#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MByte = 2^(19+1)) */ -#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MByte = 2^(20+1)) */ -#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MByte = 2^(21+1)) */ -#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MByte = 2^(22+1)) */ -#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MByte = 2^(23+1)) */ -#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MByte = 2^(24+1)) */ -#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MByte = 2^(25+1)) */ -#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MByte = 2^(26+1)) */ -#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MByte = 2^(27+1)) */ -#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (256 MByte = 2^(28+1)) */ -#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits (256 MByte = 2^(29+1)) */ -#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits (256 MByte = 2^(30+1)) */ -#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits (256 MByte = 2^(31+1)) */ +#define HAL_XSPI_SIZE_16B (0x00000000U) /*!< 16 bits ( 2 Bytes = 2^( 0+1)) */ +#define HAL_XSPI_SIZE_32B (0x00000001U) /*!< 32 bits ( 4 Bytes = 2^( 1+1)) */ +#define HAL_XSPI_SIZE_64B (0x00000002U) /*!< 64 bits ( 8 Bytes = 2^( 2+1)) */ +#define HAL_XSPI_SIZE_128B (0x00000003U) /*!< 128 bits ( 16 Bytes = 2^( 3+1)) */ +#define HAL_XSPI_SIZE_256B (0x00000004U) /*!< 256 bits ( 32 Bytes = 2^( 4+1)) */ +#define HAL_XSPI_SIZE_512B (0x00000005U) /*!< 512 bits ( 64 Bytes = 2^( 5+1)) */ +#define HAL_XSPI_SIZE_1KB (0x00000006U) /*!< 1 Kbits (128 Bytes = 2^( 6+1)) */ +#define HAL_XSPI_SIZE_2KB (0x00000007U) /*!< 2 Kbits (256 Bytes = 2^( 7+1)) */ +#define HAL_XSPI_SIZE_4KB (0x00000008U) /*!< 4 Kbits (512 Bytes = 2^( 8+1)) */ +#define HAL_XSPI_SIZE_8KB (0x00000009U) /*!< 8 Kbits ( 1 KBytes = 2^( 9+1)) */ +#define HAL_XSPI_SIZE_16KB (0x0000000AU) /*!< 16 Kbits ( 2 KBytes = 2^(10+1)) */ +#define HAL_XSPI_SIZE_32KB (0x0000000BU) /*!< 32 Kbits ( 4 KBytes = 2^(11+1)) */ +#define HAL_XSPI_SIZE_64KB (0x0000000CU) /*!< 64 Kbits ( 8 KBytes = 2^(12+1)) */ +#define HAL_XSPI_SIZE_128KB (0x0000000DU) /*!< 128 Kbits ( 16 KBytes = 2^(13+1)) */ +#define HAL_XSPI_SIZE_256KB (0x0000000EU) /*!< 256 Kbits ( 32 KBytes = 2^(14+1)) */ +#define HAL_XSPI_SIZE_512KB (0x0000000FU) /*!< 512 Kbits ( 64 KBytes = 2^(15+1)) */ +#define HAL_XSPI_SIZE_1MB (0x00000010U) /*!< 1 Mbits (128 KBytes = 2^(16+1)) */ +#define HAL_XSPI_SIZE_2MB (0x00000011U) /*!< 2 Mbits (256 KBytes = 2^(17+1)) */ +#define HAL_XSPI_SIZE_4MB (0x00000012U) /*!< 4 Mbits (512 KBytes = 2^(18+1)) */ +#define HAL_XSPI_SIZE_8MB (0x00000013U) /*!< 8 Mbits ( 1 MBytes = 2^(19+1)) */ +#define HAL_XSPI_SIZE_16MB (0x00000014U) /*!< 16 Mbits ( 2 MBytes = 2^(20+1)) */ +#define HAL_XSPI_SIZE_32MB (0x00000015U) /*!< 32 Mbits ( 4 MBytes = 2^(21+1)) */ +#define HAL_XSPI_SIZE_64MB (0x00000016U) /*!< 64 Mbits ( 8 MBytes = 2^(22+1)) */ +#define HAL_XSPI_SIZE_128MB (0x00000017U) /*!< 128 Mbits ( 16 MBytes = 2^(23+1)) */ +#define HAL_XSPI_SIZE_256MB (0x00000018U) /*!< 256 Mbits ( 32 MBytes = 2^(24+1)) */ +#define HAL_XSPI_SIZE_512MB (0x00000019U) /*!< 512 Mbits ( 64 MBytes = 2^(25+1)) */ +#define HAL_XSPI_SIZE_1GB (0x0000001AU) /*!< 1 Gbits (128 MBytes = 2^(26+1)) */ +#define HAL_XSPI_SIZE_2GB (0x0000001BU) /*!< 2 Gbits (256 MBytes = 2^(27+1)) */ +#define HAL_XSPI_SIZE_4GB (0x0000001CU) /*!< 4 Gbits (512 MBytes = 2^(28+1)) */ +#define HAL_XSPI_SIZE_8GB (0x0000001DU) /*!< 8 Gbits ( 1 GBytes = 2^(29+1)) */ +#define HAL_XSPI_SIZE_16GB (0x0000001EU) /*!< 16 Gbits ( 2 GBytes = 2^(30+1)) */ +#define HAL_XSPI_SIZE_32GB (0x0000001FU) /*!< 32 Gbits ( 4 GBytes = 2^(31+1)) */ /** * @} */ @@ -480,38 +480,38 @@ typedef struct /** @defgroup XSPI_ChipSelectBoundary XSPI Chip Select Boundary * @{ */ -#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ -#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Byte = 2^(1)) */ -#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Byte = 2^(2)) */ -#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Byte = 2^(3)) */ -#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Byte = 2^(4)) */ -#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Byte = 2^(5)) */ -#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Byte = 2^(6)) */ -#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Byte = 2^(7)) */ -#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Byte = 2^(8)) */ -#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Byte = 2^(9)) */ -#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KByte = 2^(10)) */ -#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KByte = 2^(11)) */ -#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KByte = 2^(12)) */ -#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KByte = 2^(13)) */ -#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KByte = 2^(14)) */ -#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KByte = 2^(15)) */ -#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KByte = 2^(16)) */ -#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KByte = 2^(17)) */ -#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KByte = 2^(18)) */ -#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KByte = 2^(19)) */ -#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MByte = 2^(20)) */ -#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MByte = 2^(21)) */ -#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MByte = 2^(22)) */ -#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MByte = 2^(23)) */ -#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MByte = 2^(24)) */ -#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MByte = 2^(25)) */ -#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MByte = 2^(26)) */ -#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MByte = 2^(27)) */ -#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MByte = 2^(28)) */ -#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MByte = 2^(29)) */ -#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GByte = 2^(30)) */ -#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GByte = 2^(31)) */ +#define HAL_XSPI_BONDARYOF_NONE (0x00000000U) /*! CS boundary disabled */ +#define HAL_XSPI_BONDARYOF_16B (0x00000001U) /*!< 16 bits ( 2 Bytes = 2^(1)) */ +#define HAL_XSPI_BONDARYOF_32B (0x00000002U) /*!< 32 bits ( 4 Bytes = 2^(2)) */ +#define HAL_XSPI_BONDARYOF_64B (0x00000003U) /*!< 64 bits ( 8 Bytes = 2^(3)) */ +#define HAL_XSPI_BONDARYOF_128B (0x00000004U) /*!< 128 bits ( 16 Bytes = 2^(4)) */ +#define HAL_XSPI_BONDARYOF_256B (0x00000005U) /*!< 256 bits ( 32 Bytes = 2^(5)) */ +#define HAL_XSPI_BONDARYOF_512B (0x00000006U) /*!< 512 bits ( 64 Bytes = 2^(6)) */ +#define HAL_XSPI_BONDARYOF_1KB (0x00000007U) /*!< 1 Kbits (128 Bytes = 2^(7)) */ +#define HAL_XSPI_BONDARYOF_2KB (0x00000008U) /*!< 2 Kbits (256 Bytes = 2^(8)) */ +#define HAL_XSPI_BONDARYOF_4KB (0x00000009U) /*!< 4 Kbits (512 Bytes = 2^(9)) */ +#define HAL_XSPI_BONDARYOF_8KB (0x0000000AU) /*!< 8 Kbits ( 1 KBytes = 2^(10)) */ +#define HAL_XSPI_BONDARYOF_16KB (0x0000000BU) /*!< 16 Kbits ( 2 KBytes = 2^(11)) */ +#define HAL_XSPI_BONDARYOF_32KB (0x0000000CU) /*!< 32 Kbits ( 4 KBytes = 2^(12)) */ +#define HAL_XSPI_BONDARYOF_64KB (0x0000000DU) /*!< 64 Kbits ( 8 KBytes = 2^(13)) */ +#define HAL_XSPI_BONDARYOF_128KB (0x0000000EU) /*!< 128 Kbits ( 16 KBytes = 2^(14)) */ +#define HAL_XSPI_BONDARYOF_256KB (0x0000000FU) /*!< 256 Kbits ( 32 KBytes = 2^(15)) */ +#define HAL_XSPI_BONDARYOF_512KB (0x00000010U) /*!< 512 Kbits ( 64 KBytes = 2^(16)) */ +#define HAL_XSPI_BONDARYOF_1MB (0x00000011U) /*!< 1 Mbits (128 KBytes = 2^(17)) */ +#define HAL_XSPI_BONDARYOF_2MB (0x00000012U) /*!< 2 Mbits (256 KBytes = 2^(18)) */ +#define HAL_XSPI_BONDARYOF_4MB (0x00000013U) /*!< 4 Mbits (512 KBytes = 2^(19)) */ +#define HAL_XSPI_BONDARYOF_8MB (0x00000014U) /*!< 8 Mbits ( 1 MBytes = 2^(20)) */ +#define HAL_XSPI_BONDARYOF_16MB (0x00000015U) /*!< 16 Mbits ( 2 MBytes = 2^(21)) */ +#define HAL_XSPI_BONDARYOF_32MB (0x00000016U) /*!< 32 Mbits ( 4 MBytes = 2^(22)) */ +#define HAL_XSPI_BONDARYOF_64MB (0x00000017U) /*!< 64 Mbits ( 8 MBytes = 2^(23)) */ +#define HAL_XSPI_BONDARYOF_128MB (0x00000018U) /*!< 128 Mbits ( 16 MBytes = 2^(24)) */ +#define HAL_XSPI_BONDARYOF_256MB (0x00000019U) /*!< 256 Mbits ( 32 MBytes = 2^(25)) */ +#define HAL_XSPI_BONDARYOF_512MB (0x0000001AU) /*!< 512 Mbits ( 64 MBytes = 2^(26)) */ +#define HAL_XSPI_BONDARYOF_1GB (0x0000001BU) /*!< 1 Gbits (128 MBytes = 2^(27)) */ +#define HAL_XSPI_BONDARYOF_2GB (0x0000001CU) /*!< 2 Gbits (256 MBytes = 2^(28)) */ +#define HAL_XSPI_BONDARYOF_4GB (0x0000001DU) /*!< 4 Gbits (512 MBytes = 2^(29)) */ +#define HAL_XSPI_BONDARYOF_8GB (0x0000001EU) /*!< 8 Gbits ( 1 GBytes = 2^(30)) */ +#define HAL_XSPI_BONDARYOF_16GB (0x0000001FU) /*!< 16 Gbits ( 2 GBytes = 2^(31)) */ /** * @} */ @@ -781,7 +781,6 @@ typedef struct */ #if defined(OCTOSPIM) - /** @defgroup XSPI_IO_Manger_IOPort XSPI IO Port * @{ */ @@ -971,11 +970,11 @@ HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_Hyper uint32_t Timeout); /* XSPI indirect mode functions */ -HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout); HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); -HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); /* XSPI status flag polling mode functions */ @@ -1191,7 +1190,6 @@ HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSC #define IS_XSPI_DLYB_BYPASS(DLYB) (((DLYB) == HAL_XSPI_DELAY_BLOCK_ON) || \ ((DLYB) == HAL_XSPI_DELAY_BLOCK_BYPASS)) - #define IS_XSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) #define IS_XSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_XSPI_OPTYPE_COMMON_CFG) || \ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h index a6970bfd12..9d72f9aed3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h @@ -3723,7 +3723,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32 { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); - return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH); + /* Note: Value shift +1 for correspondence with channel definition using ADC_CHANNEL_ID_NUMBER_MASK */ + uint32_t ch_decimal = (READ_BIT(*preg, ADC_OFR1_OFFSET1_CH) >> (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS + 1UL)); + return (uint32_t)__LL_ADC_DECIMAL_NB_TO_CHANNEL(ch_decimal); } /** @@ -4779,42 +4781,8 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_REG_RANK_15 * @arg @ref LL_ADC_REG_RANK_16 * Note: Specific case for ADC4, use literals LL_ADC_REG_RANK_x_ADC4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 (3) - * @arg @ref LL_ADC_CHANNEL_1 (3) - * @arg @ref LL_ADC_CHANNEL_2 (3) - * @arg @ref LL_ADC_CHANNEL_3 (3) - * @arg @ref LL_ADC_CHANNEL_4 (3) - * @arg @ref LL_ADC_CHANNEL_5 (3) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) - * - * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. - * (2) On STM32U5, parameter available only on ADC instance: ADC4. - * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). - * Other channels are slow channels (conversion rate: refer to reference manual). - * (1, 2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @retval Returned value corresponds to one of literals LL_ADC_CHANNEL_x with specific formatting, + * refer to note of this function. */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { @@ -5968,42 +5936,8 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_INJ_RANK_2 * @arg @ref LL_ADC_INJ_RANK_3 * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 (3) - * @arg @ref LL_ADC_CHANNEL_1 (3) - * @arg @ref LL_ADC_CHANNEL_2 (3) - * @arg @ref LL_ADC_CHANNEL_3 (3) - * @arg @ref LL_ADC_CHANNEL_4 (3) - * @arg @ref LL_ADC_CHANNEL_5 (3) - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC4 (2) - * @arg @ref LL_ADC_CHANNEL_VBAT_ADC4 (2) - * - * (1) On STM32U5, parameter available only on ADC instance: ADC1, ADC2. - * (2) On STM32U5, parameter available only on ADC instance: ADC4. - * (3) On STM32U5, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). - * Other channels are slow channels (conversion rate: refer to reference manual). - * (1, 2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @retval Returned value corresponds to one of literals LL_ADC_CHANNEL_x with specific formatting, + * refer to note of this function. */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { @@ -8582,6 +8516,20 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } +/** + * @brief Get flag ADC internal voltage regulator (LDO) ready. + * @note On this STM32 series, this flag indicates LDO state in different way depending on ADC instances: + * - ADC4: latched as other flags, clear flag function available + * - ADC1, ADC2 (if available): current state (not latched as other flags, no clear flag function) + * @rmtoll ISR LDORDY LL_ADC_IsActiveFlag_LDORDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL); +} + /** * @brief Clear flag ADC ready. * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC @@ -8695,6 +8643,19 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); } +/** + * @brief Clear flag ADC internal voltage regulator (LDO) ready. + * @note On this STM32 series, this flag indicates LDO state in different way depending on ADC instances: + * - ADC4: latched as other flags, clear flag function available + * - ADC1, ADC2 (if available): current state (not latched as other flags, no clear flag function) + * @rmtoll ISR LDORDY LL_ADC_ClearFlag_LDORDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_LDORDY(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_LDORDY); +} /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cordic.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cordic.h index 3920592b68..8dd4021760 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cordic.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cordic.h @@ -131,12 +131,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE * @{ */ -#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one - 32-bit data input (Q1.31 format), or two - 16-bit data input (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input - (Q1.31 format) */ +#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one + 32-bits data input (Q1.31 format), or two + 16-bits data input (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input + (Q1.31 format) */ /** * @} */ @@ -144,12 +144,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBREAD NBREAD * @{ */ -#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data output (Q1.31 format), or two - 16-bit data output (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output - (Q1.31 format) */ +#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one + 32-bits data output (Q1.31 format), or two + 16-bits data output (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output + (Q1.31 format) */ /** * @} */ @@ -218,9 +218,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions * @{ */ @@ -749,8 +747,6 @@ __STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx) * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h index 78afbdd4f3..afae552ad3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h @@ -102,10 +102,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control * @{ */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U -#define LL_MPU_CTRL_HARDFAULT_NMI 2U -#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U -#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -113,22 +113,28 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes * @{ */ -#define LL_MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define LL_MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define LL_MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ - -#define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ -#define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - -#define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */ -#define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - -#define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ -#define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ -#define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ -#define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/* Device memory attributes */ +#define LL_MPU_DEVICE_NGNRNE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define LL_MPU_DEVICE_NGNRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_NGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ + +/* Normal memory attributes */ +/* Non-cacheable memory attribute */ +#define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ +#define LL_MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through */ +#define LL_MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back */ +/* - transient mode attribute */ +#define LL_MPU_TRANSIENT 0x0U /*!< Normal memory, transient */ +#define LL_MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient */ +/* - allocation attribute */ +#define LL_MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate */ +#define LL_MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate */ +#define LL_MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate */ +#define LL_MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate */ /** * @} */ @@ -145,8 +151,8 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access * @{ */ -#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) -#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< Execute attribute */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< Execute never attribute */ /** * @} */ @@ -154,9 +160,9 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable * @{ */ -#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) +#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< Not shareable attribute */ +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< Outer shareable attribute */ +#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< Inner shareable attribute */ /** * @} */ @@ -164,10 +170,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes * @{ */ -#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< Read/write privileged-only attribute */ +#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< Read/write privileged/unprivileged attribute */ +#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< Read-only privileged-only attribute */ +#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< Read-only privileged/unprivileged attribute */ /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmac.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmac.h index 970aeb9387..d8161456af 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmac.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_fmac.h @@ -38,7 +38,6 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ /** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants * @{ @@ -147,9 +146,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions * @{ */ @@ -1033,8 +1030,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions * @{ @@ -1042,7 +1037,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx); ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx); - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h index da22b3e075..1fa88dfdaa 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lptim.h @@ -94,10 +94,10 @@ static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] = /** Legacy definitions for compatibility purpose @cond 0 */ -#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1 /* for legacy purpose */ -#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2 /* for legacy purpose */ -#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1 /* for legacy purpose */ -#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2 /* for legacy purpose */ +#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1 +#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2 +#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1 +#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2 /** @endcond */ @@ -541,12 +541,12 @@ typedef struct /** Legacy definitions for compatibility purpose @cond 0 */ -#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O /* for legacy purpose */ -#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM /* for legacy purpose */ +#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM +#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 +#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 +#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O +#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O +#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM /** @endcond */ @@ -1689,6 +1689,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL)); } + /** * @brief Clear the autoreload match flag (ARRMCF) * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h index b64ce2a80d..6acd292952 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_opamp.h @@ -193,8 +193,8 @@ typedef struct /** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting * @{ */ -#define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */ -#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (OPAMP_CSR_VP_SEL) /*!< OPAMP non inverting input connected to DAC1 channel output(channel1 for OPAMP1, channel2 for OPAMP2) */ +#define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U /*!< OPAMP non inverting input connected to GPIO pin (pin PA0 for OPAMP1, pin PA6 for OPAMP2) */ +#define LL_OPAMP_INPUT_NONINVERT_DAC (OPAMP_CSR_VP_SEL) /*!< OPAMP non inverting input connected to DAC1 channel output(channel1 for OPAMP1, channel2 for OPAMP2) */ /** * @} */ @@ -213,13 +213,15 @@ typedef struct * @{ */ #define LL_OPAMP_NONINVERTINGINPUT_IO0 LL_OPAMP_INPUT_NONINVERT_IO0 -#define LL_OPAMP_NONINVERTINGINPUT_DAC_CH LL_OPAMP_INPUT_NONINV_DAC1_CH1 +#define LL_OPAMP_NONINVERTINGINPUT_DAC_CH LL_OPAMP_INPUT_NONINVERT_DAC #define LL_OPAMP_INVERTINGINPUT_IO0 LL_OPAMP_INPUT_INVERT_IO0 #define LL_OPAMP_INVERTINGINPUT_IO1 LL_OPAMP_INPUT_INVERT_IO1 #define LL_OPAMP_INVERTINGINPUT_CONNECT_NO LL_OPAMP_INPUT_INVERT_CONNECT_NO -#define LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 LL_OPAMP_INPUT_NONINV_DAC1_CH1 +#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 LL_OPAMP_INPUT_NONINVERT_DAC + +#define LL_OPAMP_INPUT_NONINVERT_DAC1_CH1 LL_OPAMP_INPUT_NONINVERT_DAC /** * @} */ @@ -554,7 +556,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(const OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @param InputNonInverting This parameter can be one of the following values: * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 - * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC * @retval None */ __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting) @@ -568,7 +570,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32 * @param OPAMPx OPAMP instance * @retval Returned value can be one of the following values: * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 - * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 + * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC */ __STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(const OPAMP_TypeDef *OPAMPx) { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h index 6a62949c2c..75a8fc455b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rng.h @@ -674,6 +674,9 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) { +#if defined(RNG_HTCR_NIST_VALUE) + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ +#endif /* defined(RNG_HTCR_NIST_VALUE) */ WRITE_REG(RNGx->HTCR, HTCFG); } @@ -691,11 +694,47 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) /** * @} */ +#if defined(RNG_NSCR_NIST_VALUE) + +/** @defgroup RNG_LL_EF_Noise_Test_Control Noise Test Control + * @{ + */ + +/** + * @brief Set RNG Noise Test Control + * @rmtoll NSCR NOISECFG LL_RNG_SetNoiseConfig + * @param RNGx RNG Instance + * @param NOISECFG can be values of 32 bits + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetNoiseConfig(RNG_TypeDef *RNGx, uint32_t NOISECFG) +{ + /* For NIST compliance we can fin the recommended value in the application note AN4230 */ + WRITE_REG(RNGx->NSCR, NOISECFG); +} + +/** + * @brief Get RNG Noise Test Control + * @rmtoll NSCR NOISECFG LL_RNG_GetNoiseConfig + * @param RNGx RNG Instance + * @retval Return 32-bit RNG Noise Test configuration + */ +__STATIC_INLINE uint32_t LL_RNG_GetNoiseConfig(const RNG_TypeDef *RNGx) +{ + + return (uint32_t)READ_REG(RNGx->NSCR); +} + +/** + * @} + */ + +#endif /* defined(RNG_NSCR_NIST_VALUE) */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h index f714f38b22..f8984ade48 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_sdmmc.h @@ -357,12 +357,12 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) -#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (cycles) */ #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_DATATIMEOUT */ #ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ -#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT +#define SDMMC_SWDATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_SWDATATIMEOUT */ #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) @@ -1208,12 +1208,12 @@ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx); /* Command path state machine (CPSM) management functions */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command); uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response); /* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data); uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx); @@ -1283,7 +1283,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); /** @addtogroup HAL_SDMMC_LL_Group6 * @{ */ -uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf); +uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, const SDMMC_DMALinkNodeConfTypeDef *pNodeConf); uint32_t SDMMC_DMALinkedList_InsertNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pPrevNode, SDMMC_DMALinkNodeTypeDef *pNode); uint32_t SDMMC_DMALinkedList_RemoveNode(SDMMC_DMALinkedListTypeDef *pLinkedList, SDMMC_DMALinkNodeTypeDef *pNode); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h index 45b5f811d6..275a4da595 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h @@ -135,6 +135,19 @@ extern "C" { * @} */ +#if defined(SYSCFG_CFGR1_ENDCAP) +/** @defgroup SYSTEM_LL_DECOUPLING_CAPACITANCE SYSCFG DECOUPLING CAPACITANCE + * @{ + */ +#define LL_SYSCFG_HSPI_CAPACITANCE_OFF 0x00000000U /*!< Decoupling with no capacitance value on HSPI supply */ +#define LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3 SYSCFG_CFGR1_ENDCAP_0 /*!< Decoupling with 1/3 of capacitance value on HSPI supply */ +#define LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3 SYSCFG_CFGR1_ENDCAP_1 /*!< Decoupling with 2/3 of capacitance value on HSPI supply */ +#define LL_SYSCFG_HSPI_CAPACITANCE_FULL SYSCFG_CFGR1_ENDCAP /*!< Decoupling with full capacitance value on HSPI supply */ +/** + * @} + */ +#endif /* SYSCFG_CFGR1_ENDCAP */ + /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK * @{ */ @@ -151,6 +164,77 @@ extern "C" { * @} */ +#if defined(SYSCFG_OTGHSPHYCR_CLKSEL) +/** @defgroup SYSTEM_LL_OTG_PHY_CLOCK_FREQUENCY SYSCFG OTG High-speed (HS) PHY reference clock frequency selection + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_CLK_16MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< Reference clock freqeuncy is 16 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 19.2 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_20MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 20 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_24MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 24 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_26MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | \ + SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 26 Mhz */ +#define LL_SYSCFG_OTGHSPHY_CLK_32MHZ (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | \ + SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< Reference clock freqeuncy is 32 Mhz */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYCR_CLKSEL */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE) +/** @defgroup SYSTEM_LL_OTG_PHYTUNER_DISCONNECT_THRESTHOLD SYSCFG OTG High-speed (HS) PHYTUNER disconnnect threshold + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ +#define LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE) +/** @defgroup SYSTEM_LL_OTG_SQUELSH SYSCFG OTG High-speed (HS) PHY Squelch threshold adjustment + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ +#define LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE) +/** @defgroup SYSTEM_LL_OTG_TRANSMITTER_PREEMPHASIS_CURRENT SYSCFG OTG High-speed (HS) transmitter preemphasis current control + * @{ + */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ +#define LL_SYSCFG_OTGHSPHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | \ + SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ +/** + * @} + */ +#endif /* SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */ + +/** @defgroup SYSCFG_Lock_items SYSCFG Lock items + * @{ + */ +#define LL_SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ +#define LL_SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define LL_SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ +#define LL_SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ +#define LL_SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ +#define LL_SYSCFG_LOCK_ALL (LL_SYSCFG_MPU_NSEC | LL_SYSCFG_VTOR_NSEC | LL_SYSCFG_SAU | LL_SYSCFG_MPU_SEC | \ + LL_SYSCFG_VTOR_AIRCR_SEC) /*!< All */ +#else +#define LL_SYSCFG_LOCK_ALL (LL_SYSCFG_MPU_NSEC | LL_SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + /** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes * @note Only available when system implements security (TZEN=1) * @{ @@ -267,10 +351,10 @@ extern "C" { /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE * @{ */ -#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ -#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ -#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 0 (VREF_OUT3) */ -#define LL_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_2 /*!< Voltage reference scale 1 (VREF_OUT4) */ +#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define LL_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ /** * @} */ @@ -406,8 +490,75 @@ __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); } +#if defined(SYSCFG_CFGR1_ENDCAP) +/** + * @brief Set decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP LL_SYSCFG_SetHSPIDecouplingCapacitance + * @param Capacitance This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_FULL + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP, Capacitance); +} + +/** + * @brief Get decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP LL_SYSCFG_GetHSPIDecouplingCapacitance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_FULL + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetHSPIDecouplingCapacitance(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP)); +} +#endif /* SYSCFG_CFGR1_ENDCAP */ + +#if defined(SYSCFG_CFGR1_SRAMCACHED) +/** + * @brief Enable the cachability of internal SRAMs by DCACHE2. + * @rmtoll SYSCFG_CFGR1 SRAMCACHED LL_SYSCFG_EnableSRAMsCachability + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableSRAMsCachability(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} + +/** + * @brief Disable the cachability of internal SRAMs by DCACHE2. + * @rmtoll SYSCFG_CFGR1 SRAMCACHED LL_SYSCFG_DisableSRAMsCachability + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableSRAMsCachability(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); +} + /** - * @brief Enable Floating Point Unit Invalid operation Interrupt + * @brief Check if internal SRAMs cachability by DCACHE2 is enabled or disabled. + * @rmtoll SYSCFG_CFGR1 SRAMCACHED LL_SYSCFG_IsEnabledSRAMsCachability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledSRAMsCachability(void) +{ + return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED) == SYSCFG_CFGR1_SRAMCACHED) ? 1UL : 0UL); +} +#endif /* SYSCFG_CFGR1_SRAMCACHED */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_FPU_IT_MANAGEMENT FPU interrupt management + * @{ + */ + +/** + * @brief Enable Floating Point Unit Invalid operation Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC * @retval None */ @@ -417,7 +568,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) } /** - * @brief Enable Floating Point Unit Divide-by-zero Interrupt + * @brief Enable Floating Point Unit Divide-by-zero Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC * @retval None */ @@ -427,7 +578,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) } /** - * @brief Enable Floating Point Unit Underflow Interrupt + * @brief Enable Floating Point Unit Underflow Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC * @retval None */ @@ -437,7 +588,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) } /** - * @brief Enable Floating Point Unit Overflow Interrupt + * @brief Enable Floating Point Unit Overflow Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC * @retval None */ @@ -447,7 +598,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) } /** - * @brief Enable Floating Point Unit Input denormal Interrupt + * @brief Enable Floating Point Unit Input denormal Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC * @retval None */ @@ -457,7 +608,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) } /** - * @brief Enable Floating Point Unit Inexact Interrupt + * @brief Enable Floating Point Unit Inexact Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC * @retval None */ @@ -467,7 +618,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) } /** - * @brief Disable Floating Point Unit Invalid operation Interrupt + * @brief Disable Floating Point Unit Invalid operation Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC * @retval None */ @@ -477,7 +628,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) } /** - * @brief Disable Floating Point Unit Divide-by-zero Interrupt + * @brief Disable Floating Point Unit Divide-by-zero Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC * @retval None */ @@ -487,7 +638,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) } /** - * @brief Disable Floating Point Unit Underflow Interrupt + * @brief Disable Floating Point Unit Underflow Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC * @retval None */ @@ -497,7 +648,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) } /** - * @brief Disable Floating Point Unit Overflow Interrupt + * @brief Disable Floating Point Unit Overflow Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC * @retval None */ @@ -507,7 +658,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) } /** - * @brief Disable Floating Point Unit Input denormal Interrupt + * @brief Disable Floating Point Unit Input denormal Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC * @retval None */ @@ -517,7 +668,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) } /** - * @brief Disable Floating Point Unit Inexact Interrupt + * @brief Disable Floating Point Unit Inexact Interrupt. * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC * @retval None */ @@ -587,7 +738,182 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) } /** - * @brief Set connections to TIM1/8/15/16/17 Break inputs + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_CPU_LOCK CPU secure/non-secure lock + * @{ + */ + +/** + * @brief Lock the secure or non-secure VTOR registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_LockVTOR + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockVTOR(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSVTAIRCR); +#else + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Check the lock state of secure or non-secure VTOR registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_IsLockedVTOR + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedVTOR(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSVTAIRCR) == SYSCFG_CSLCKR_LOCKSVTAIRCR) ? 1UL : 0UL); +#else + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR) == SYSCFG_CNSLCKR_LOCKNSVTOR) ? 1UL : 0UL); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the non-secure VTOR registers. + * @rmtoll CNSLCKR LOCKNSVTOR LL_SYSCFG_LockVTOR_NS + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockVTOR_NS(void) +{ + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR); +} + +/** + * @brief Check the lock state of non-secure VTOR registers. + * @rmtoll CNSLCKR LOCKNSVTOR LL_SYSCFG_IsLockedVTOR_NS + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedVTOR_NS(void) +{ + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR) == SYSCFG_CNSLCKR_LOCKNSVTOR) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Lock the secure or non-secure MPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKNSMPU/LOCKSMPU LL_SYSCFG_LockMPU + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockMPU(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSMPU); +#else + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Check the lock state of secure or non-secure MPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKNSMPU/LOCKSMPU LL_SYSCFG_IsLockedMPU + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedMPU(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSMPU) == SYSCFG_CSLCKR_LOCKSMPU) ? 1UL : 0UL); +#else + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU) == SYSCFG_CNSLCKR_LOCKNSMPU) ? 1UL : 0UL); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the non-secure MPU registers. + * @rmtoll CNSLCKR LOCKNSMPU LL_SYSCFG_LockMPU_NS + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockMPU_NS(void) +{ + SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU); +} + +/** + * @brief Check the lock state of non-secure MPU registers. + * @rmtoll CNSLCKR LOCKNSMPU LL_SYSCFG_IsLockedMPU_NS + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedMPU_NS(void) +{ + return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU) == SYSCFG_CNSLCKR_LOCKNSMPU) ? 1UL : 0UL); +} + +/** + * @brief Lock the secure SAU registers. + * @rmtoll CSLCKR LOCKSAU LL_SYSCFG_LockSAU + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockSAU(void) +{ + SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSAU); +} + +/** + * @brief Check the lock state of secure SAU registers. + * @rmtoll CSLCKR LOCKSAU LL_SYSCFG_IsLockedSAU + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsLockedSAU(void) +{ + return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSAU) == SYSCFG_CSLCKR_LOCKSAU) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Lock the secure or non-secure CPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_LockConfig + * @param Item Item(s) to set lock on. + * This parameter can be a combination of: + * @arg @ref LL_SYSCFG_MPU_NSEC + * @arg @ref LL_SYSCFG_VTOR_NSEC + * @arg @ref LL_SYSCFG_SAU + * @arg @ref LL_SYSCFG_MPU_SEC + * @arg @ref LL_SYSCFG_VTOR_AIRCR_SEC + * @arg @ref LL_SYSCFG_LOCK_ALL + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockConfig(uint32_t Item) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + MODIFY_REG(SYSCFG->CSLCKR, (SYSCFG_CSLCKR_LOCKSVTAIRCR | SYSCFG_CSLCKR_LOCKSMPU | SYSCFG_CSLCKR_LOCKSAU), Item); +#else + MODIFY_REG(SYSCFG->CNSLCKR, (SYSCFG_CNSLCKR_LOCKNSVTOR | SYSCFG_CNSLCKR_LOCKNSMPU), Item); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the non-secure CPU registers. + * @rmtoll CSLCKR/CNSLCKR LOCKSVTAIRCR/LOCKNSVTOR LL_SYSCFG_LockConfig_NS + * @param Item Item(s) to set lock on. + * This parameter can be a combination of: + * @arg @ref LL_SYSCFG_MPU_NSEC + * @arg @ref LL_SYSCFG_VTOR_NSEC + * @arg @ref LL_SYSCFG_LOCK_ALL + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_LockConfig_NS(uint32_t Item) +{ + MODIFY_REG(SYSCFG->CNSLCKR, (SYSCFG_CNSLCKR_LOCKNSVTOR | SYSCFG_CNSLCKR_LOCKNSMPU), Item); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_TIMER_BREAK Timer break inputs + * @{ + */ + +/** + * @brief Set connections to TIM1/8/15/16/17 Break inputs. * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n @@ -605,7 +931,7 @@ __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) } /** - * @brief Get connections to TIM1/8/15/16/17 Break inputs + * @brief Get connections to TIM1/8/15/16/17 Break inputs. * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n @@ -622,63 +948,68 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL)); } +/** + * @} + */ /** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management * @{ */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /** - * @brief Configure Secure mode - * @note Only available from secure state when system implements security (TZEN=1) - * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure - * @param Configuration This parameter shall be the full combination - * of the following values: - * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC - * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC - * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + * @brief Clear Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus * @retval None */ -__STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration) +__STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void) { - WRITE_REG(SYSCFG->SECCFGR, Configuration); + SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE); } -#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @brief Get Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done + * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE)); +} /** - * @brief Get Secure mode configuration - * @note Only available when system implements security (TZEN=1) - * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure - * @retval Returned value is the combination of the following values: - * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC - * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC - * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams + * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus + * @retval None */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void) +__STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void) { - return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU)); + SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR); } /** - * @} + * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams + * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done + * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR)); +} /** * @} */ -/** @defgroup SYSTEM_LL_EF_COMPENSATION SYSCFG COMPENSATION +/** @defgroup SYSTEM_LL_EF_SYSCFG_COMPENSATION SYSCFG Compensation cell * @{ */ /** - * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD. * @rmtoll CCVR PCV1 LL_SYSCFG_GetPMOSVddCompensationValue * @retval Returned value is the PMOS compensation cell */ @@ -688,7 +1019,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationValue(void) } /** - * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD. * @rmtoll CCVR NCV1 LL_SYSCFG_GetNMOSVddCompensationValue * @retval Returned value is the NMOS compensation cell */ @@ -698,7 +1029,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void) } /** - * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2 + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2. * @rmtoll CCVR PCV2 LL_SYSCFG_GetPMOSVddIO2CompensationValue * @retval Returned value is the PMOS compensation cell */ @@ -708,7 +1039,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationValue(void) } /** - * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2 + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2. * @rmtoll CCVR NCV2 LL_SYSCFG_GetNMOSVddIO2CompensationValue * @retval Returned value is the NMOS compensation cell */ @@ -719,7 +1050,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationValue(void) #if defined(SYSCFG_CCVR_PCV3) /** - * @brief Get the compensation cell value of the HSPI IO PMOS transistor supplied by VDD + * @brief Get the compensation cell value of the HSPI IO PMOS transistor supplied by VDD. * @rmtoll CCVR PCV3 LL_SYSCFG_GetPMOSVddHSPICompensationValue * @retval Returned value is the PMOS compensation cell */ @@ -729,7 +1060,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationValue(void) } /** - * @brief Get the compensation cell value of the HSPI IO NMOS transistor supplied by VDD + * @brief Get the compensation cell value of the HSPI IO NMOS transistor supplied by VDD. * @rmtoll CCVR NCV3 LL_SYSCFG_GetNMOSVddHSPICompensationValue * @retval Returned value is the NMOS compensation cell */ @@ -740,7 +1071,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationValue(void) #endif /* SYSCFG_CCVR_PCV3 */ /** - * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD. * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS1 bit of the @@ -753,7 +1084,7 @@ __STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode) } /** - * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD. * @rmtoll CCCR PCC1 LL_SYSCFG_GetPMOSVddCompensationCode * @retval Returned value is the PMOS compensation cell */ @@ -763,7 +1094,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void) } /** - * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2 + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2. * @rmtoll CCCR PCC2 LL_SYSCFG_SetPMOSVddIO2CompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS2 bit of the @@ -775,9 +1106,8 @@ __STATIC_INLINE void LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode) MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC2, PMOSCode << SYSCFG_CCCR_PCC2_Pos); } - /** - * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2 + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2. * @rmtoll CCCR PCC2 LL_SYSCFG_GetPMOSVddIO2CompensationCode * @retval Returned value is the PMOS compensation */ @@ -788,7 +1118,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationCode(void) #if defined(SYSCFG_CCCR_PCC3) /** - * @brief Set the compensation cell code of the HSPI IO PMOS transistor supplied by VDD + * @brief Set the compensation cell code of the HSPI IO PMOS transistor supplied by VDD. * @rmtoll CCCR PCC3 LL_SYSCFG_SetPMOSVddHSPICompensationCode * @param PMOSCode PMOS compensation code * This code is applied to the PMOS compensation cell when the CS3 bit of the @@ -801,7 +1131,7 @@ __STATIC_INLINE void LL_SYSCFG_SetPMOSVddHSPICompensationCode(uint32_t PMOSCode) } /** - * @brief Get the compensation cell code of the HSPI IO PMOS transistor supplied by VDD + * @brief Get the compensation cell code of the HSPI IO PMOS transistor supplied by VDD. * @rmtoll CCCR PCC3 LL_SYSCFG_GetPMOSVddHSPICompensationCode * @retval Returned value is the PMOS compensation */ @@ -812,7 +1142,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationCode(void) #endif /* SYSCFG_CCCR_PCC3 */ /** - * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD. * @rmtoll CCCR PCC2 LL_SYSCFG_SetNMOSVddCompensationCode * @param NMOSCode NMOS compensation code * This code is applied to the NMOS compensation cell when the CS2 bit of the @@ -825,7 +1155,7 @@ __STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode) } /** - * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD. * @rmtoll CCCR NCC1 LL_SYSCFG_GetNMOSVddCompensationCode * @retval Returned value is the Vdd compensation cell code for NMOS transistors */ @@ -835,7 +1165,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationCode(void) } /** - * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2 + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2. * @rmtoll CCCR NCC2 LL_SYSCFG_SetNMOSVddIO2CompensationCode * @param NMOSCode NMOS compensation code * This code is applied to the NMOS compensation cell when the CS2 bit of the @@ -848,9 +1178,8 @@ __STATIC_INLINE void LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode) MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC2, NMOSCode << SYSCFG_CCCR_NCC2_Pos); } - /** - * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2 + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2. * @rmtoll CCCR NCC2 LL_SYSCFG_GetNMOSVddIO2CompensationCode * @retval Returned value is the NMOS compensation cell code */ @@ -861,7 +1190,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationCode(void) #if defined(SYSCFG_CCCR_NCC3) /** - * @brief Set the compensation cell code of the HSPI IO NMOS transistor supplied by VDD + * @brief Set the compensation cell code of the HSPI IO NMOS transistor supplied by VDD. * @rmtoll CCCR NCC3 LL_SYSCFG_SetNMOSVddHSPICompensationCode * @param NMOSCode NMOS compensation code * This code is applied to the NMOS compensation cell when the CS3 bit of the @@ -875,7 +1204,7 @@ __STATIC_INLINE void LL_SYSCFG_SetNMOSVddHSPICompensationCode(uint32_t NMOSCode) } /** - * @brief Get the compensation cell code of the HSPI IO NMOS transistor supplied by VDD + * @brief Get the compensation cell code of the HSPI IO NMOS transistor supplied by VDD. * @rmtoll CCCR NCC3 LL_SYSCFG_GetNMOSVddHSPICompensationCode * @retval Returned value is the NMOS compensation cell code */ @@ -886,7 +1215,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationCode(void) #endif /* SYSCFG_CCCR_NCC3 */ /** - * @brief Enable the Compensation Cell of GPIO supplied by VDD + * @brief Enable the Compensation Cell of GPIO supplied by VDD. * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell * @note The vdd compensation cell can be used only when the device supply * voltage ranges from 1.71 to 3.6 V @@ -898,7 +1227,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableVddCompensationCell(void) } /** - * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2 + * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2. * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell * @note The Vdd I/O compensation cell can be used only when the device supply * voltage ranges from 1.08 to 3.6 V @@ -911,7 +1240,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableVddIO2CompensationCell(void) #if defined(SYSCFG_CCCSR_EN3) /** - * @brief Enable the Compensation Cell of HSPI IO supplied by VDD + * @brief Enable the Compensation Cell of HSPI IO supplied by VDD. * @rmtoll CCCSR EN3 LL_SYSCFG_EnableVddHSPICompensationCell * @retval None */ @@ -922,7 +1251,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableVddHSPICompensationCell(void) #endif /* SYSCFG_CCCSR_EN3 */ /** - * @brief Disable the Compensation Cell of GPIO supplied by VDD + * @brief Disable the Compensation Cell of GPIO supplied by VDD. * @rmtoll CCCSR EN1 LL_SYSCFG_DisableVddCompensationCell * @note The Vdd compensation cell can be used only when the device supply * voltage ranges from 1.71 to 3.6 V @@ -934,7 +1263,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableVddCompensationCell(void) } /** - * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2 + * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2. * @rmtoll CCCSR EN2 LL_SYSCFG_DisableVddIO2CompensationCell * @note The Vdd I/O compensation cell can be used only when the device supply * voltage ranges from 1.08 to 3.6 V @@ -947,7 +1276,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableVddIO2CompensationCell(void) #if defined(SYSCFG_CCCSR_EN3) /** - * @brief Disable the Compensation Cell of HSPI IO supplied by VDD + * @brief Disable the Compensation Cell of HSPI IO supplied by VDD. * @rmtoll CCCSR EN3 LL_SYSCFG_DisableVddHSPICompensationCell * @retval None */ @@ -958,7 +1287,7 @@ __STATIC_INLINE void LL_SYSCFG_DisableVddHSPICompensationCell(void) #endif /* SYSCFG_CCCSR_EN3 */ /** - * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable + * @brief Check if the Compensation Cell of GPIO supplied by VDD is enabled. * @rmtoll CCCSR EN1 LL_SYSCFG_IsEnabled_VddCompensationCell * @retval State of bit (1 or 0). */ @@ -968,7 +1297,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddCompensationCell(void) } /** - * @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enable + * @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enabled. * @rmtoll CCCSR EN2 LL_SYSCFG_IsEnabled_VddIO2CompensationCell * @retval State of bit (1 or 0). */ @@ -979,7 +1308,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void) #if defined(SYSCFG_CCCSR_EN3) /** - * @brief Check if the Compensation Cell of HSPI IO supplied by VDD is enable + * @brief Check if the Compensation Cell of HSPI IO supplied by VDD is enabled. * @rmtoll CCCSR EN3 LL_SYSCFG_IsEnabled_VddHSPICompensationCell * @retval State of bit (1 or 0). */ @@ -990,7 +1319,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddHSPICompensationCell(void) #endif /* SYSCFG_CCCSR_EN3 */ /** - * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD. * @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddCMPCR * @retval State of bit (1 or 0). */ @@ -1000,7 +1329,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void) } /** - * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2 + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2. * @rmtoll CCCSR RDY2 LL_SYSCFG_IsActiveFlag_VddIO2CMPCR * @retval State of bit (1 or 0). */ @@ -1011,7 +1340,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void) #if defined(SYSCFG_CCCSR_RDY3) /** - * @brief Get Compensation Cell ready Flag of HSPI IO supplied by VDD + * @brief Get Compensation Cell ready Flag of HSPI IO supplied by VDD. * @rmtoll CCCSR RDY3 LL_SYSCFG_IsActiveFlag_VddHSPICMPCR * @retval State of bit (1 or 0). */ @@ -1022,7 +1351,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddHSPICMPCR(void) #endif /* SYSCFG_CCCSR_RDY3 */ /** - * @brief Set the compensation cell code selection of GPIO supplied by VDD + * @brief Set the compensation cell code selection of GPIO supplied by VDD. * @rmtoll CCCSR CS1 LL_SYSCFG_SetVddCellCompensationCode * @param CompCode: Selects the code to be applied for the Vdd compensation cell * This parameter can be one of the following values: @@ -1036,7 +1365,7 @@ __STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode) } /** - * @brief Set the compensation cell code selection of GPIO supplied by VDDIO2 + * @brief Set the compensation cell code selection of GPIO supplied by VDDIO2. * @rmtoll CCCSR CS2 LL_SYSCFG_SetVddIO2CellCompensationCode * @param CompCode: Selects the code to be applied for the VddIO compensation cell * This parameter can be one of the following values: @@ -1051,7 +1380,7 @@ __STATIC_INLINE void LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode) #if defined(SYSCFG_CCCSR_CS3) /** - * @brief Set the compensation cell code selection of HSPI IO supplied by VDD + * @brief Set the compensation cell code selection of HSPI IO supplied by VDD. * @rmtoll CCCSR CS3 LL_SYSCFG_SetVddHSPICellCompensationCode * @param CompCode: Selects the code to be applied for the VddIO compensation cell * This parameter can be one of the following values: @@ -1066,7 +1395,7 @@ __STATIC_INLINE void LL_SYSCFG_SetVddHSPICellCompensationCode(uint32_t CompCode) #endif /* SYSCFG_CCCSR_CS3 */ /** - * @brief Get the compensation cell code selection of GPIO supplied by VDD + * @brief Get the compensation cell code selection of GPIO supplied by VDD. * @rmtoll CCCSR CS1 LL_SYSCFG_GetVddCellCompensationCode * @retval Returned value can be one of the following values: * @arg LL_SYSCFG_VDD_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) @@ -1078,7 +1407,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void) } /** - * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2 + * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2. * @rmtoll CCCSR CS2 LL_SYSCFG_GetVddIO2CellCompensationCode * @retval Returned value can be one of the following values: * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) @@ -1092,7 +1421,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddIO2CellCompensationCode(void) #if defined(SYSCFG_CCCSR_CS3) /** - * @brief Get the compensation cell code selection of HSPI IO supplied by VDD + * @brief Get the compensation cell code selection of HSPI IO supplied by VDD. * @rmtoll CCCSR CS3 LL_SYSCFG_GetVddHSPICellCompensationCode * @retval Returned value can be one of the following values: * @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) @@ -1104,6 +1433,247 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetVddHSPICellCompensationCode(void) return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS3)); } #endif /* SYSCFG_CCCSR_CS3 */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_OTGPHY OTG HS PHY configurations + * @{ + */ + +#if defined(SYSCFG_OTGHSPHYCR_EN) +/** + * @brief Enable the OTG high-speed PHY. + * @rmtoll SYSCFG_OTGHSPHYCR EN LL_SYSCFG_EnableOTGPHY + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableOTGPHY(void) +{ + SET_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN); +} + +/** + * @brief Disable the OTG high-speed PHY. + * @rmtoll SYSCFG_OTGHSPHYCR EN LL_SYSCFG_DisableOTGPHY + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableOTGPHY(void) +{ + CLEAR_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN); +} + +/** + * @brief Check if the OTG high-speed PHY is enabled or disabled. + * @rmtoll SYSCFG_OTGHSPHYCR EN LL_SYSCFG_IsEnabledOTGPHY + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledOTGPHY(void) +{ + return ((READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN) == SYSCFG_OTGHSPHYCR_EN) ? 1UL : 0UL); +} +#endif /* SYSCFG_OTGHSPHYCR_EN */ + +#if defined(SYSCFG_OTGHSPHYCR_PDCTRL) +/** + * @brief Enable the OTG high-speed PHY common block power-down control. + * @rmtoll SYSCFG_OTGHSPHYCR PDCTRL LL_SYSCFG_EnableOTGPHYPowerDown + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableOTGPHYPowerDown(void) +{ + SET_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL); +} + +/** + * @brief Disable the OTG high-speed PHY common block power-down control. + * @rmtoll SYSCFG_OTGHSPHYCR PDCTRL LL_SYSCFG_DisableOTGPHYPowerDown + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableOTGPHYPowerDown(void) +{ + CLEAR_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL); +} + +/** + * @brief Check if the OTG high-speed PHY common block power-down is enabled or disabled. + * @rmtoll SYSCFG_OTGHSPHYCR PDCTRL LL_SYSCFG_IsEnabledOTGPHYPowerDown + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledOTGPHYPowerDown(void) +{ + return ((READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL) == SYSCFG_OTGHSPHYCR_PDCTRL) ? 1UL : 0UL); +} +#endif /* SYSCFG_OTGHSPHYCR_PDCTRL */ + +#if defined(SYSCFG_OTGHSPHYCR_CLKSEL) +/** + * @brief Set the OTG high-speed PHY reference clock frequency selection. + * @rmtoll SYSCFG_OTGHSPHYCR CLKSEL LL_SYSCFG_SetOTGPHYReferenceClockFrequency + * @param ClockFrequency This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_16MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_20MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_24MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_26MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_32MHZ + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYReferenceClockFrequency(uint32_t ClockFrequency) +{ + MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, ClockFrequency); +} + +/** + * @brief Get the OTG high-speed PHY reference clock frequency selection. + * @rmtoll SYSCFG_OTGHSPHYCR CLKSEL LL_SYSCFG_GetOTGPHYReferenceClockFrequency + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_16MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_20MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_24MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_26MHZ + * @arg @ref LL_SYSCFG_OTGHSPHY_CLK_32MHZ + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYReferenceClockFrequency(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL)); +} +#endif /* SYSCFG_OTGHSPHYCR_CLKSEL */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE) +/** + * @brief Set the OTG high-speed PHY disconnect threshold adjustment. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 COMPDISTUNE LL_SYSCFG_SetOTGPHYDisconnectThresholdAdjustment + * @param DisconnectThreshold This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYDisconnectThresholdAdjustment(uint32_t DisconnectThreshold) +{ + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold); +} + +/** + * @brief Get the OTG high-speed PHY disconnect threshold adjustment. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 COMPDISTUNE LL_SYSCFG_GetOTGPHYDisconnectThresholdAdjustment + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYDisconnectThresholdAdjustment(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE)); +} +#endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_SQRXTUNE) +/** + * @brief Set the voltage level for the threshold used to detect valid high-speed data. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 SQRXTUNE LL_SYSCFG_SetOTGPHYSquelchThresholdAdjustment + * @param SquelchThreshold This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYSquelchThresholdAdjustment(uint32_t SquelchThreshold) +{ + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold); +} + +/** + * @brief Get the voltage level for the threshold used to detect valid high-speed data. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 SQRXTUNE LL_SYSCFG_GetOTGPHYSquelchThresholdAdjustment + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT + * @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYSquelchThresholdAdjustment(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE)); +} +#endif /* SYSCFG_OTGHSPHYTUNER2_SQRXTUNE */ + +#if defined(SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE) +/** + * @brief Set the OTG high-speed PHY transmitter preemphasis current control. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 TXPREEMPAMPTUNE LL_SYSCFG_SetOTGPHYTransmitterPreemphasisCurrent + * @param PreemphasisCurrent This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_1X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_2X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_3X + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetOTGPHYTransmitterPreemphasisCurrent(uint32_t PreemphasisCurrent) +{ + MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent); +} + +/** + * @brief Get the OTG high-speed PHY transmitter preemphasis current control. + * @rmtoll SYSCFG_OTGHSPHYTUNER2 TXPREEMPAMPTUNE LL_SYSCFG_GetOTGPHYTransmitterPreemphasisCurrent + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_1X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_2X + * @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_3X + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYTransmitterPreemphasisCurrent(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE)); +} +#endif /* SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure Secure mode. + * @note Only available from secure state when system implements security (TZEN=1) + * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure + * @param Configuration This parameter shall be the full combination + * of the following values: + * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC + * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC + * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration) +{ + WRITE_REG(SYSCFG->SECCFGR, Configuration); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get Secure mode configuration. + * @note Only available when system implements security (TZEN=1) + * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure + * @retval Returned value is the combination of the following values: + * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC + * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC + * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU)); +} + +/** + * @} + */ + /** * @} */ @@ -1173,7 +1743,6 @@ __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } - /** * @brief Enable the Debug Clock Trace * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock @@ -1574,6 +2143,7 @@ __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) /** @defgroup SYSTEM_LL_EF_FLASH FLASH * @{ */ + /** * @brief Set FLASH Latency * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency @@ -1725,59 +2295,6 @@ __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) * @} */ - -/** @defgroup SYSTEM_LL_EF_ERASE_MEMORIE_STATUS ERASE MEMORIE STATUS - * @{ - */ - -/** - * @brief Clear Status of End of Erase for ICACHE and PKA RAMs - * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void) -{ - SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE); -} - -/** - * @brief Get Status of End of Erase for ICACHE and PKA RAMs - * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus - * @retval Returned value can be one of the following values: - * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done - * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE)); -} - - -/** - * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams - * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void) -{ - SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR); -} - -/** - * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams - * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus - * @retval Returned value can be one of the following values: - * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done - * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR)); -} -/** - * @} - */ - #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */ /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h index 4780f66494..ea33667602 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_tim.h @@ -682,10 +682,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); } @@ -4036,7 +4036,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u /** * @brief Select the external trigger (ETR) input source. - * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or + * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or * not a timer instance supports ETR source selection. * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource * @param TIMx Timer instance diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h index 62b63d8264..46741ac84f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h @@ -869,7 +869,7 @@ __STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Enable Rx hard resrt interrupt + * @brief Enable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1034,7 +1034,7 @@ __STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Disable Rx hard resrt interrupt + * @brief Disable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1199,7 +1199,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPD } /** - * @brief Check if Rx hard resrt interrupt enabled + * @brief Check if Rx hard reset interrupt enabled * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Clear Rx hard resrt interrupt + * @brief Clear Rx hard reset interrupt * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1468,10 +1468,10 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx) */ /** - * @brief Check if FRS interrupt + * @brief Check if FRS Event Flag is active * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx) { @@ -1482,7 +1482,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPD * @brief Check if type c event on CC2 * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) { @@ -1493,7 +1493,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const * * @brief Check if type c event on CC1 * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) { @@ -1501,10 +1501,21 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const * } /** - * @brief Check if Rx message end interrupt + * @brief Check if Rx error flag is active + * @rmtoll SR RXERR LL_UCPD_IsActiveFlag_RxErr + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxErr(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXERR) == UCPD_SR_RXERR) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx message end flag is active * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx) { @@ -1512,10 +1523,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const } /** - * @brief Check if Rx overrun interrupt + * @brief Check if Rx overrun flag is active * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx) { @@ -1523,10 +1534,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UC } /** - * @brief Check if Rx hard resrt interrupt + * @brief Check if Rx hard reset flag is active * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx) { @@ -1534,7 +1545,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const U } /** - * @brief Check if Rx orderset interrupt + * @brief Check if Rx orderset flag is active * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1545,7 +1556,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *con } /** - * @brief Check if Rx non empty interrupt + * @brief Check if Rx non empty flag is active * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1556,7 +1567,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCP } /** - * @brief Check if TX underrun interrupt + * @brief Check if TX underrun flag is active * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1567,7 +1578,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UC } /** - * @brief Check if hard reset sent interrupt + * @brief Check if hard reset sent flag is active * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1578,7 +1589,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *con } /** - * @brief Check if hard reset discard interrupt + * @brief Check if hard reset discard flag is active * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1589,7 +1600,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *con } /** - * @brief Check if Tx message abort interrupt + * @brief Check if Tx message abort flag is active * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1600,7 +1611,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const } /** - * @brief Check if Tx message sent interrupt + * @brief Check if Tx message sent flag is active * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1611,7 +1622,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *cons } /** - * @brief Check if Tx message discarded interrupt + * @brief Check if Tx message discarded flag is active * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1622,7 +1633,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *cons } /** - * @brief Check if Tx data receive interrupt + * @brief Check if Tx data interrupt flag is active * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1812,7 +1823,7 @@ __STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx) /** * @brief Read data - * @rmtoll TXDR RXDATA LL_UCPD_ReadData + * @rmtoll RXDR RXDATA LL_UCPD_ReadData * @param UCPDx UCPD Instance * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF */ @@ -1855,7 +1866,7 @@ __STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt) */ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx); -ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct); +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct); void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct); /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h index e644ab255a..ac1bb184ad 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h @@ -935,7 +935,7 @@ typedef USB_HCTypeDef USB_DRD_HCTypeDef; } \ else if ((wCount) <= 62U) \ { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html index a4a9266bd7..22b823558e 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html @@ -40,15 +40,164 @@

Purpose

Update History

- +

Main Changes

    -
  • Maintenance Release V1.6.0 of STM32CubeU5 Firmware Package to deploy the new HAL SDIO driver.
  • General updates to fix known defects and implementation enhancements.

HAL/LL Drivers updates

    +
  • HAL/LL ADC driver +
      +
    • Add LL_ADC_IsActiveFlag_LDORDY() macro to get ADC internal voltage regulator ready flag.
      • +
    • Set return value of LL_ADC_GetOffsetChannel() to format LL_ADC_CHANNEL_X.
      • +
    • +
  • HAL/LL CRYP driver +
      +
    • Update CRYP driver to use correctly the wrapped key in decryption mode.
      • +
    • +
  • HAL/LL GFXMMU driver +
      +
    • Update HAL_GFXMMU_GetState() API to fix wrong interrupt management.
      • +
    • +
  • HAL/LL GTZC driver +
      +
    • Update HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() API to use correct size in case of FMC_BANK1.
      • +
    • +
  • HAL/LL IWDG driver +
      +
    • Calculate the maximum Timeout period HAL_IWDG_DEFAULT_TIMEOUT based on a Prescaler=128 at LSI frequency=32kHz.
      • +
    • +
  • HAL/LL OPAMP driver +
      +
    • Rename the define of non-inverting OPAMP input connected to DAC output.
      • +
    • +
  • HAL/LL OSPI driver +
      +
    • Fix issue related to second XSPI instance management inside XSPIM.
      • +
    • +
  • HAL/LL PKA driver +
      +
    • Remove static global variables and add them to PKA handle to be compliant with HAL coding rules.
      • +
    • Use PKA RAM erase timeout in HAL_PKA_Init() and HAL_PKA_MspDeInit() APIs to avoid SAES decryption failure after PKA deinitialization.
      • +
    • +
  • HAL/LL PWR driver +
      +
    • Add guidance to HAL_PWR_ConfigAttributes() API.
      • +
    • Enhance Wake-Up Interrupt Handling for STOP3 Mode.
      • +
    • +
  • HAL/LL RCC driver +
      +
    • Add missing call to UNUSED() macro to avoid compilation warnings related to the unused arguments.
      • +
    • Add guidance to HAL_RCC_ConfigAttributes() API.
      • +
    • +
  • HAL/LL TIM driver +
      +
    • Include Dithering mode in IS_TIM_PERIOD macro.
      • +
    • Fix update flag (UIF) clearing in TIM_Base_SetConfig.
      • +
    • +
  • HAL/LL DMA driver +
      +
    • Update LL_DMA_CreateLinkNode() API to add missing assert checks.
      • +
    • Update HAL_DMAEx_List_BuildNode() API to remove duplicated assert checks.
      • +
    • Update DMA_List_BuildNode() API to clear CLLR register of the last node of a queue.
      • +
    • +
  • HAL FDCAN driver +
      +
    • Fix assert issue when Standard or Extended filter numbers are zero.
      • +
    • Fix the incorrect comments.
      • +
    • +
  • HAL/LL RNG driver +
      +
    • Add LL_RNG_SetNoiseConfig() API to find the recommended value for NIST compliance.
      • +
    • Update HAL_RNG_GenerateRandomNumber() and HAL_RNGEx_RecoverSeedError() APIs to distinguish between RecoverSeedError and SeedError.
      • +
    • +
  • HAL/LL RTC_BKP driver +
      +
    • Avoid entering initialization mode when calling HAL_RTC_Init() if the RTC is already configured in binary mode to prevent unwanted reset of the SSR register.
      • +
    • +
  • HAL/LL SDMMC driver +
      +
    • Add missing eMMC RPMB APIs.
      • +
    • Add support of customized SDIO Card enumeration sequence.
      • +
    • +
  • HAL/LL SPI driver +
      +
    • Add protection against wrong transfer size during transmission.
      • +
    • Update HAL_SPI_TransmitReceive_DMA() API to check coherence between data size and DMA TX configuration.
      • +
    • Fix CRC computation to feat with standard CRC16-CCITT (XMODEM).
      • +
    • +
  • HAL I2C driver +
      +
    • Remove tmp variable from I2C_TransferConfig() function.
      • +
    • Update HAL_I2C_IsDeviceReady() API to take into account the number of trials.
      • +
    • +
  • HAL SYSCFG driver +
      +
    • Rename APIs HAL_SYSCFG_EnableIOAnalogSwitchBooster(),HAL_SYSCFG_DisableIOAnalogSwitchBooster(), HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection() and HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection() to be aligned with MISRAC2012 rule 5.1
      • +
    • +
  • LL SYSTEM driver +
      +
    • Enhance LL System Source Code.
      • +
    • Fix LL_VREFBUF_VOLTAGE_SCALE3 value.
      • +
    • +
  • HAL UART driver +
      +
    • Ensure UART Rx buffer is not written beyond boundaries in case of RX FIFO reception in Interrupt mode.
      • +
    • Align prescaler value used by default in UART_GET_DIV_FACTOR macro with RM.
      • +
    • Ensure TC flag is cleared prior starting DMA transmit.
      • +
    • Remove reference to HAL_UARTEx_WakeupCallback and to HAL_UART_WAKEUP_CB_ID defines.
      • +
    • Add HAL_UART_RXEVENT_IDLE event notification to user in case of HAL_UARTEx_ReceiveToIdle_DMA() use with Circular DMA, even if occurring just after TC event.
      • +
    • Apply DMAT/DMAR specific management for HAL_UARTEx_ReceiveToIdle() and HAL_UARTEx_ReceiveToIdle_IT() APIs.
      • +
    • Correct DMA Rx abort procedure impact on ongoing Tx transfer in polling mode.
      • +
    • Correct wrong comment in HAL_UARTEx_DisableFifoMode() API.
      • +
    • +
  • HAL USART driver +
      +
    • Align prescaler value used by default in USART_GET_DIV_FACTOR macro with RM.
      • +
    • Correct wrong comment in HAL_USARTEx_DisableFifoMode() API.
      • +
    • Improve the visibility of the SPI function support in HAL USART description and comments.
      • +
    • +
  • HAL SMARTCARD driver +
      +
    • Implement workaround to resolve HW bug.
      • +
    • +
  • HAL XSPI driver +
      +
    • Change XSPI_WaitFlagStateUntilTimeout() API handle state to HAL_XSPI_STATE_READY in case of Timeout to avoid blocking driver operation.
      • +
    • Correct comments for XSPI_MemorySize and XSPI_ChipSelectBoundary related definitions.
      • +
    • Update management of SSHIFT when DTR is activated for data transfer in XSPI_ConfigCmd() API.
      • +
    • Update state verification inside Abort APIs.
      • +
    • +
  • HAL/LL USB driver +
      +
    • hal_hcd.c/ll_usb.c: fix USB data toggle.
      • +
    • hal_pcd.c/ll_usb.c: fix added to support bulk transfer in double buffer mode.
      • +
    • hal_hcd.c: ensure to reactivate the usb channel in case of transfer error.
      • +
    • Fix the condition on EONUM flag of DOEPCTLx register in HAL_PCD_IRQHandler() to correctly check on the frame number parity.
      • +
    • +
+

Known Limitations

+
    +
  • N/A
    • +
+

Backward compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Maintenance Release V1.6.0 of STM32CubeU5 Firmware Package to deploy the new HAL SDIO driver.
    • +
  • General updates to fix known defects and implementation enhancements.
    • +
+

HAL/LL Drivers updates

+
  • HAL GENERIC driver
    • update stm32u5xx_hal_conf_template file to add the support for the new HAL SDIO driver.
      • @@ -71,11 +220,11 @@

      HAL/LL Drivers updates

    • Support new HAL SDIO driver.
-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -84,7 +233,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • HAL and LL drivers Maintenance Release for STM32U535xx/STM32U545xx, STM32U575xx/STM32U585xx, STM32U599xx/STM32U5A9xx, STM32U595xx/STM32U5A5xx, STM32U5F9xx/STM32U5G9xx and STM32U5F7xx/STM32U5G7xx devices
  • Add the HAL MMC replay protected memory block management feature
    • @@ -265,11 +414,11 @@

    LL Drivers updates

  • Rename LL_UTILS_PACKAGETYPE_WLCSP144_SMPS to LL_UTILS_PACKAGETYPE_LQFP100_DSI_SMPS define
-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -278,7 +427,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • HAL and LL drivers Maintenance Release for STM32U5XX devices
  • Update ADC HAL and LL drivers to fix known defects and add implementation enhancements
    • @@ -302,11 +451,11 @@

    LL Drivers updates

  • Add new Helper macro for differential mode raw data to voltage conversion
-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -315,7 +464,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • HAL and LL drivers official Release for STM32U5F7xx/STM32U5G7xx, STM32U5F9xx/STM32U5G9xx, STM32U535xx/STM32U545xx, STM32U575xx/STM32U585xx, STM32U595xx/STM32U5A5xx and STM32U599xx/STM32U5A9xx devices
  • Add 2 new HAL drivers : GFXTIM and JPEG highlighting the graphics aspect of STM32U5F7/STM32U5G7/STM32U5F9/STM32U5G9 devices
    • @@ -405,11 +554,11 @@

    LL Drivers updates

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -418,7 +567,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • HAL and LL drivers Official Release for STM32U535xx / STM32U545xx, STM32U575xx / STM32U585xx, STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices.
  • Update STM32U545xx_User_Manual, STM32U585xx_User_Manual and STM32U5A9xx_User_Manual CHM User Manuals
    • @@ -618,11 +767,11 @@

    LL Drivers updates

Note: HAL/LL Backward compatibility ensured by legacy defines.

-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -631,7 +780,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • HAL and LL drivers Maintenance Release for STM32U575xx / STM32U585xx devices and new support of STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices
  • Add New LTDC, GFXMMU, DSI, GPU2D HAL drivers highlighting the graphics aspect of STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices
    • @@ -858,11 +1007,11 @@

    LL Drivers updates

Backward compatibility ensured by legacy defines

-

Known Limitations

+

Known Limitations

  • N/A
-

Backward compatibility

+

Backward compatibility

  • N/A
@@ -871,7 +1020,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Patch release V1.0.2 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
@@ -887,11 +1036,11 @@

LL Drivers updates

  • Backward compatibility ensured by legacy defines
    • -

    Known Limitations

    +

    Known Limitations

    • N/A
    -

    Backward compatibility

    +

    Backward compatibility

    • N/A
    @@ -900,7 +1049,7 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • Patch release V1.0.1 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
    @@ -949,11 +1098,11 @@

    LL Drivers updates

  • Add LL_I2C_EnableFastModePlus, LL_I2C_DisableFastModePlus and LL_I2C_IsEnabledFastModePlus APIs
    • -

    Known Limitations

    +

    Known Limitations

    • N/A
    -

    Backward compatibility

    +

    Backward compatibility

    • N/A
    @@ -962,11 +1111,11 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • First official release of HAL and LL drivers for STM32U575xx / STM32U585xx devices
    -

    Known Limitations

    +

    Known Limitations

    • N/A
    diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c index f1136de678..b587c12cca 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c @@ -52,11 +52,11 @@ * @{ */ /** - * @brief STM32U5xx HAL Driver version number 1.6.0 + * @brief STM32U5xx HAL Driver version number 1.6.1 */ #define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32U5xx_HAL_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ -#define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32U5xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ |(__STM32U5xx_HAL_VERSION_SUB1 << 16U)\ @@ -664,7 +664,7 @@ void HAL_SYSCFG_DisableVREFBUF(void) * * @retval None */ -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) +void HAL_SYSCFG_EnableIOAnalogBooster(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } @@ -674,7 +674,7 @@ void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) * * @retval None */ -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) +void HAL_SYSCFG_DisableIOAnalogBooster(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); } @@ -684,7 +684,7 @@ void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) * * @retval None */ -void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void) +void HAL_SYSCFG_EnableIOAnalogVoltageSelection(void) { SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); } @@ -694,11 +694,45 @@ void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void) * * @retval None */ -void HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection(void) +void HAL_SYSCFG_DisableIOAnalogVoltageSelection(void) { CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); } +#if defined(SYSCFG_CFGR1_ENDCAP) +/** + * @brief Set decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP HAL_SYSCFG_SetHSPIDecouplingCapacitance + * @param Capacitance This parameter can be one of the following values: + * @arg @ref SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_FULL + * @retval None + */ +void HAL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_DECOUPLING_CAPACITANCE(Capacitance)); + + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP, Capacitance); +} + +/** + * @brief Get decoupling capacitance on HSPI supply. + * @rmtoll SYSCFG_CFGR1 ENDCAP HAL_SYSCFG_GetHSPIDecouplingCapacitance + * @retval Returned value can be one of the following values: + * @arg @ref SYSCFG_HSPI_CAPACITANCE_OFF + * @arg @ref SYSCFG_HSPI_CAPACITANCE_1_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_2_DIV_3 + * @arg @ref SYSCFG_HSPI_CAPACITANCE_FULL + */ +uint32_t HAL_SYSCFG_GetHSPIDecouplingCapacitance(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP)); +} +#endif /* SYSCFG_CFGR1_ENDCAP */ + #if defined(SYSCFG_CFGR1_SRAMCACHED) /** * @brief Enable the Cacheability of internal SRAMx by DCACHE2 @@ -756,6 +790,7 @@ void HAL_SYSCFG_EnableVddHSPICompensationCell(void) SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); } #endif /* SYSCFG_CCCSR_EN3 */ + /** * @brief Disable the Compensation Cell of GPIO supplied by VDD * @rmtoll CCCSR EN1 HAL_SYSCFG_DisableVddCompensationCell @@ -865,8 +900,6 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem) */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - - /** @defgroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions * @brief SYSCFG attributes management functions. * @@ -957,7 +990,6 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri This parameter can be one of @ref SYSCFG_OTG_PHY_Enable * @retval None */ - void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig) { /* Check the parameter */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c index d3b051c7e6..5eb8029c3d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cordic.c @@ -164,12 +164,12 @@ static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAError(DMA_HandleTypeDef *hdma); + /** * @} */ /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions * @{ */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c index fc9ffb222d..4d317ce445 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c @@ -74,19 +74,23 @@ (++) Reload Value should not exceed 0xFFFFFF [..] - *** How to configure MPU (secure and non secure) using CORTEX HAL driver *** + *** How to configure MPU using CORTEX HAL driver *** =========================================================== [..] - This section provides functions allowing to Enable and configure the MPU secure and non-secure. + This section provides functions allowing to configure the Memory Protection Unit (MPU). + (#) Disable the MPU using HAL_MPU_Disable(). + (#) Configure the necessary MPU memory attributes using HAL_MPU_ConfigMemoryAttributes(). + (#) Configure the necessary MPU regions using HAL_MPU_ConfigRegion() ennsuring that the MPU region configuration link to + the right MPU attributes number. (#) Enable the MPU using HAL_MPU_Enable() function. - (#) Disable the MPU using HAL_MPU_Disable() function. - (#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU. - (#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU. - (#) Configure the MPU region using HAL_MPU_ConfigRegion() - and HAL_MPU_ConfigRegion_NS() to address the non secure MPU. - (#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes() - and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU. + + -@- The memory management fault exception is enabled in HAL_MPU_Enable() function and the system will enter the memory + management fault handler MemManage_Handler() when an illegal memory access is performed. + -@- If the MPU has previously been programmed, disable the unused regions to prevent any previous region configuration + from affecting the new MPU configuration. + -@- MPU APIs ending with '_NS' allow to control the non-secure Memory Protection Unit (MPU_NS) from the secure context + and the same sequence as above applies to configure the non-secure MPU. @endverbatim ****************************************************************************** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc_ex.c index 061ab92235..3d15366d20 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_crc_ex.c @@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ } - - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c index c873ad74f3..054ba9240e 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp.c @@ -363,6 +363,7 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma); static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize); static void CRYP_SetIV(CRYP_HandleTypeDef *hcryp); static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); @@ -635,6 +636,13 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size, data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode); @@ -649,10 +657,23 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD { /* Disable AES to change key mode */ __HAL_CRYP_DISABLE(hcryp); + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set key mode selection (Normal, Wrapped or Shared key )*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED); } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the key size data type, AlgoMode and operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | \ AES_CR_KEYSEL | AES_CR_KEYPROT | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | \ @@ -1206,7 +1227,11 @@ HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_Contex hcryp->Init.KeyMode = pcont->KeyMode; hcryp->Phase = pcont->Phase; hcryp->KeyIVConfig = pcont->KeyIVConfig; - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } /* Restore CRYP CR register content */ WRITE_REG(hcryp->Instance->CR, (uint32_t)(pcont->CR_Reg)); @@ -1379,11 +1404,25 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, if (hcryp->Instance == AES) { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); } else { + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set the operating mode and normal key selection */ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_ENCRYPT | CRYP_KEYMODE_NORMAL); } @@ -1474,10 +1513,22 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, { hcryp->Size = Size; } - - /* Set Decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + if (IS_AES_ALL_INSTANCE(hcryp->Instance)) + { + /* Set Decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else + { + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_DECRYPT | CRYP_KEYMODE_NORMAL); + } /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; @@ -1584,7 +1635,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1613,6 +1670,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1687,7 +1745,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -1715,6 +1779,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInpu default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1772,7 +1837,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set encryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -1878,6 +1949,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -1934,7 +2006,13 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp { hcryp->Size = Size; } - + /* Check the busy flag before writing CR register */ + if (CRYP_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYP_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Set decryption operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); @@ -1962,6 +2040,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp default: hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + hcryp->State = HAL_CRYP_STATE_READY; status = HAL_ERROR; break; } @@ -2005,26 +2084,30 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInp */ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) { + uint32_t itsource = hcryp->Instance->IER; + uint32_t itflagsr = hcryp->Instance->SR; + uint32_t itflagisr = hcryp->Instance->ISR; + /* Check if Read or write error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET) + if ((itsource & CRYP_IT_RWEIE) != 0U) { /* If write Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET) + if ((itflagsr & CRYP_FLAG_WRERR) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); } /* If read Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET) + if ((itflagsr & CRYP_FLAG_RDERR) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); } } /* Check if Key error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET) + if ((itsource & CRYP_IT_KEIE) != 0U) { - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET) + if ((itflagisr & CRYP_FLAG_KEIF) != 0U) { hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY; __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF); @@ -2033,9 +2116,9 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) } } - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET) + if ((itflagisr & CRYP_FLAG_CCF) != 0U) { - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + if ((itsource & CRYP_IT_CCFIE) != 0U) { /* Clear computation complete flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); @@ -3536,7 +3619,31 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ +static HAL_StatusTypeDef CRYP_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @brief Writes Key in Key registers. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -3610,7 +3717,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { if (hcryp->KeyIVConfig == 1U) @@ -5761,7 +5867,7 @@ static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *In static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output) { uint32_t outputaddr = (uint32_t)Output; - uint32_t count = 0U; + uint32_t count; /* In case of GCM payload phase encryption, check that suspension can be carried out */ if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp_ex.c index 86b58c4bce..6862b3b510 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cryp_ex.c @@ -39,7 +39,7 @@ /** @addtogroup CRYPEx_Private_Defines * @{ */ - +#define CRYPEx_GENERAL_TIMEOUT 82U #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ #define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */ #define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ @@ -66,6 +66,7 @@ /* Private function prototypes -----------------------------------------------*/ static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout); /* Exported functions---------------------------------------------------------*/ /** @addtogroup CRYPEx_Exported_Functions * @{ @@ -125,6 +126,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c /* Check if initialization phase has already been performed */ if (hcryp->Phase == CRYPEx_PHASE_PROCESS) { + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Change the CRYP phase */ hcryp->Phase = CRYPEx_PHASE_FINAL; @@ -143,19 +151,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, c while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) { /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -459,7 +464,13 @@ HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } /* Encryption operating mode(Mode 0)*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); @@ -504,7 +515,13 @@ HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_ /* Set the operating mode */ MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); - + /* Check the busy flag before writing CR register */ + if (CRYPEx_WaitFLAG(hcryp, AES_SR_BUSY, SET, CRYPEx_GENERAL_TIMEOUT) != HAL_OK) + { + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } status = CRYPEx_KeyDecrypt(hcryp, Timeout); } else @@ -724,6 +741,31 @@ static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t T __HAL_UNLOCK(hcryp); return HAL_OK; } +/** + * @brief Wait Instance Flag + * @param hcryp cryp handle + * @param flag Specifies the flag to check + * @param Status Flag status (SET or RESET) + * @param Timeout Timeout duration + * @retval HAL status. + */ + +static HAL_StatusTypeDef CRYPEx_WaitFLAG(CRYP_HandleTypeDef *hcryp, uint32_t flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + while (__HAL_CRYP_GET_FLAG(hcryp, flag) == Status) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + CLEAR_BIT(hcryp->Instance->CR, AES_CR_EN); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + /* return error */ + return HAL_ERROR; + } + } + return HAL_OK; +} /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c index cbfc1ac14f..f75b812b2a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dac.c @@ -1263,6 +1263,14 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } + else + { + /* In case of mode normal and buffer disabled, connection to both on chip periph and external pin is not possible */ + if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_DISABLE) + { + assert_param(sConfig->DAC_ConnectOnChipPeripheral != DAC_CHIPCONNECT_BOTH); + } + } assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode)); assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c index 30ce86bb76..828fbb74bd 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dcmi.c @@ -86,7 +86,7 @@ and a pointer to the user callback function. Use function HAL_DCMI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. This function allows to reset following callbacks: @@ -98,10 +98,10 @@ (+) MspDeInitCallback : callback for DCMI MspDeInit. By default, after the HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: + all callbacks are reset to the corresponding legacy weak (overridden) functions: examples FrameEventCallback(), HAL_DCMI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DCMI_Init + reset to the legacy weak (overridden) functions in the HAL_DCMI_Init and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_DCMI_Init and HAL_DCMI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -116,7 +116,7 @@ When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -1000,7 +1000,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) * the embedded synchronization delimiters unmasks. * @retval HAL status */ -HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask) +HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, const DCMI_SyncUnmaskTypeDef *SyncUnmask) { /* Process Locked */ __HAL_LOCK(hdcmi); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c index b8c6ac1ff6..d60eca23d8 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c @@ -1091,10 +1091,6 @@ HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNod assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); } /* Check DMA channel security and privilege attributes parameters */ @@ -3901,9 +3897,21 @@ static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO); } /********************************************************************************* CBR2 register value is updated */ - } + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_2D_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } + else + { + /* Update CLLR register value *************************************************************************************/ + /* Reset CLLR Register value : channel linked-list address register offset */ + pNode->LinkRegisters[NODE_CLLR_LINEAR_DEFAULT_OFFSET] = 0U; + /********************************************************************************* CLLR register value is cleared */ + } + /* Update node information value ************************************************************************************/ /* Set node information */ pNode->NodeInfo = pNodeConfig->NodeType; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dsi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dsi.c index cfe40f630d..501784e610 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dsi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dsi.c @@ -1808,14 +1808,14 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t NbParams, uint32_t Param1, - uint8_t *ParametersTable) + const uint8_t *ParametersTable) { uint32_t uicounter; uint32_t nbBytes; uint32_t count; uint32_t tickstart; uint32_t fifoword; - uint8_t *pparams = ParametersTable; + const uint8_t *pparams = ParametersTable; /* Process locked */ __HAL_LOCK(hdsi); @@ -2861,7 +2861,7 @@ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane * the configuration information for the DSI. * @retval HAL state */ -HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) +HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi) { return hdsi->State; } @@ -2872,7 +2872,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) * the configuration information for the DSI. * @retval DSI Error Code */ -uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) +uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi) { /* Get the error code */ return hdsi->ErrorCode; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c index b0dcc8edee..5ca5d8fee4 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fdcan.c @@ -1302,7 +1302,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA if (sFilterConfig->IdType == FDCAN_STANDARD_ID) { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.StdFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU)); assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType)); @@ -1322,7 +1322,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */ { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.ExtFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU)); assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c index 5d437fa35d..0e65908df9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_fmac.c @@ -204,7 +204,6 @@ not defined, the callback registration feature is not available and weak callbacks are used. - @endverbatim * */ @@ -229,7 +228,6 @@ /** @defgroup FMAC_Private_Constants FMAC Private Constants * @{ */ - #define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU) #define MAX_PRELOAD_INDEX 0xFFU #define PRELOAD_ACCESS_DMA 0x00U @@ -322,7 +320,6 @@ /* Private variables ---------------------------------------------------------*/ /* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ - static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac); @@ -348,7 +345,6 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma); static void FMAC_DMAError(DMA_HandleTypeDef *hdma); /* Functions Definition ------------------------------------------------------*/ - /** @defgroup FMAC_Exported_Functions FMAC Exported Functions * @{ */ @@ -1203,7 +1199,7 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti */ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check handle state is ready */ if (hfmac->State == HAL_FMAC_STATE_READY) @@ -1222,11 +1218,24 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { (*(hfmac->pInputSize)) = hfmac->InputCurrentSize; } + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_IT) && (hfmac->pOutput != NULL)) { (*(hfmac->pOutputSize)) = hfmac->OutputCurrentSize; } + if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_DMA) + { + /* Disable the DMA stream managing FMAC input data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaIn); + } + + if ((hfmac->OutputAccess == FMAC_BUFFER_ACCESS_DMA) && (status == HAL_OK)) + { + /* Disable the DMA stream managing FMAC output data */ + status = HAL_DMA_Abort_IT(hfmac->hdmaOut); + } + /* Reset FMAC unit (internal pointers) */ if (FMAC_Reset(hfmac) == HAL_ERROR) { @@ -1239,8 +1248,6 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { /* Reset the data pointers */ FMAC_ResetDataPointers(hfmac); - - status = HAL_OK; } /* Reset the busy flag */ @@ -2576,7 +2583,6 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma) #else HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ - } /** @@ -2708,11 +2714,11 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma) HAL_FMAC_ErrorCallback(hfmac); #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ } + /** * @} */ - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gfxmmu.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gfxmmu.c index c2b16597c9..82c12bf3e8 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gfxmmu.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gfxmmu.c @@ -538,7 +538,7 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf * @param Address Start address of LUT in flash. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address) @@ -593,7 +593,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, * This parameter must be a number between Min_Data = 1 and Max_Data = 1024. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber) { @@ -640,7 +640,7 @@ HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, * @param lutLine LUT line parameters. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine) +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_LutLineTypeDef *lutLine) { HAL_StatusTypeDef status = HAL_OK; @@ -725,7 +725,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uin * @retval HAL status. * @note This function is only available on STM32U599/STM32U5A9 devices. */ -HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers) +HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, const GFXMMU_BuffersTypeDef *Buffers) { HAL_StatusTypeDef status = HAL_OK; @@ -761,7 +761,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU * @note This function is only available on STM32U599/STM32U5A9 devices. */ HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu, - GFXMMU_CachePrefetchTypeDef *CachePrefetch) + const GFXMMU_CachePrefetchTypeDef *CachePrefetch) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_FUNCTIONAL_STATE(CachePrefetch->Activation)); @@ -814,7 +814,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu, * @note This function is only available on STM32U5F9/STM32U5G9 devices. */ HAL_StatusTypeDef HAL_GFXMMU_ModifyAddressCache(GFXMMU_HandleTypeDef *hgfxmmu, - GFXMMU_AddressCacheTypeDef *AddressCache) + const GFXMMU_AddressCacheTypeDef *AddressCache) { HAL_StatusTypeDef status = HAL_OK; assert_param(IS_FUNCTIONAL_STATE(AddressCache->Activation)); @@ -910,7 +910,7 @@ __weak void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu) * @param hgfxmmu GFXMMU handle. * @retval GFXMMU state. */ -HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu) +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu) { /* Return GFXMMU handle state */ return hgfxmmu->State; @@ -924,6 +924,7 @@ HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu) uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu) { uint32_t error_code; + uint32_t primask = __get_PRIMASK(); /* Enter in critical section */ __disable_irq(); @@ -933,7 +934,7 @@ uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu) hgfxmmu->ErrorCode = GFXMMU_ERROR_NONE; /* Exit from critical section */ - __enable_irq(); + __set_PRIMASK(primask); /* Return GFXMMU error code */ return error_code; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c index c8b17c129f..023a52131a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c @@ -612,7 +612,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddres break; #if defined (FMC_BANK1) case FMC_BANK1: - size = TZSC_MPCWM1_MEM_SIZE; + size = TZSC_MPCWM2_MEM_SIZE; if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) { register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c index 067f1133d5..8f81950c2d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash.c @@ -272,10 +272,10 @@ */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); static void HASH_DMAError(DMA_HandleTypeDef *hdma); -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size); static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash); static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash); static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout); @@ -764,7 +764,7 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -790,7 +790,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -805,7 +805,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -822,7 +822,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -848,7 +848,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -863,7 +863,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBu * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -911,7 +911,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -935,7 +935,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -949,7 +949,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -965,7 +965,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -990,7 +990,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1004,7 +1004,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1077,7 +1077,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1107,7 +1107,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1164,7 +1164,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutB * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -1183,7 +1183,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -1225,7 +1225,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -1243,7 +1243,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1297,7 +1297,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1322,7 +1322,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1832,7 +1832,7 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma) * suspension time is stored in the handle for resumption later on. * @retval HAL status */ -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -1951,7 +1951,7 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size message digest size in bytes. * @retval None */ -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size) { uint32_t msgdigest = (uint32_t)pMsgDigest; @@ -2502,10 +2502,10 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2537,7 +2537,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Set the phase */ @@ -2553,7 +2553,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; Size_tmp = hhash->HashInCount; } /* ... or multi-buffer HASH processing end */ @@ -2561,7 +2561,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint { /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; + pInBuffer_tmp = (const uint8_t *)pInBuffer; Size_tmp = Size; /* Configure the number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(Size); @@ -2639,9 +2639,9 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2673,7 +2673,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */ } @@ -2684,7 +2684,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Check if initialization phase has already be performed */ @@ -2742,7 +2742,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -2864,7 +2864,7 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3030,7 +3030,7 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; @@ -3235,7 +3235,7 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, ui * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3313,7 +3313,7 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3424,7 +3424,7 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash_ex.c index 8215c1549d..dcbae5f16a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hash_ex.c @@ -148,7 +148,7 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -174,7 +174,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -189,7 +189,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -206,7 +206,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -232,7 +232,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -247,7 +247,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -290,7 +290,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -314,7 +314,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -328,7 +328,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -344,7 +344,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -368,7 +368,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -382,7 +382,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -434,7 +434,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -464,7 +464,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -521,7 +521,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -540,7 +540,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -583,7 +583,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -601,7 +601,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -659,7 +659,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -683,7 +683,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -759,7 +759,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -780,7 +780,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -806,7 +806,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -829,7 +829,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -850,7 +850,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -876,7 +876,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -898,7 +898,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -919,7 +919,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -945,7 +945,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -967,7 +967,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); @@ -988,7 +988,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -1014,7 +1014,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c index 009b208791..ad79d6e82e 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_hcd.c @@ -1710,6 +1710,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else { hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; } } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); @@ -2140,7 +2146,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, return HAL_ERROR; } - if (((epnum & 0xFU)== 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) + if (((epnum & 0xFU) == 0U) && ((hhcd->ep0_PmaAllocState & 0xF000U) != 0U)) { hhcd->hc[ch_num & 0xFU].pmaadress = hhcd->hc[0U].pmaadress; hhcd->hc[ch_num & 0xFU].pmaaddr0 = hhcd->hc[0U].pmaaddr0; @@ -3832,8 +3838,8 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num & 0xFU].xfer_len == 0U) || ((received_bytes < hhcd->hc[ch_num & 0xFU].max_packet))) { - hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; - hhcd->hc[ch_num & 0xFU].state = HC_XFRC; + hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; + hhcd->hc[ch_num & 0xFU].state = HC_XFRC; } else { @@ -3846,10 +3852,10 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) { - hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + hhcd->hc[ch_num & 0xFU].toggle_in ^= 1U; } } - /* manage NACK Response */ + /* Manage NACK Response */ else if (((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_NAK) && (hhcd->hc[ch_num & 0xFU].urb_state != URB_DONE)) { @@ -3863,7 +3869,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) HCD_SET_CH_RX_STATUS(hhcd->Instance, phy_chnum, USB_CH_RX_DIS); } } - /* manage STALL Response */ + /* Manage STALL Response */ else if ((ch_reg & USB_CH_RX_STRX) == USB_CH_RX_STALL) { (void)HAL_HCD_HC_Halt(hhcd, ch_num); @@ -3952,7 +3958,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* Handle Isochronous channel */ if ((ch_reg & USB_CH_UTYPE) == USB_EP_ISOCHRONOUS) { - /* correct transaction */ + /* Correct transaction */ if ((hhcd->Instance->ISTR & USB_ISTR_ERR) == 0U) { /* Double buffer isochronous out */ @@ -3961,7 +3967,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) HCD_SET_CH_TX_CNT(hhcd->Instance, phy_chnum, 0U); } #if (USE_USB_DOUBLE_BUFFER == 1U) - else /* double buffer isochronous out */ + else /* Double buffer isochronous out */ { /* Odd Transaction */ if ((ch_reg & USB_CH_DTOG_TX) != 0U) @@ -4010,14 +4016,20 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) hhcd->hc[ch_num & 0xFU].xfer_len = 0U; } + if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || + (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) + { + hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; + } + /* Transfer no yet finished only one packet of mps is transferred and ACKed from device */ if (hhcd->hc[ch_num & 0xFU].xfer_len != 0U) { - /* manage multiple Xfer */ + /* Manage multiple Xfer */ hhcd->hc[ch_num & 0xFU].xfer_buff += data_xfr; hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; - /* start a new transfer */ + /* Start a new transfer */ (void) USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num & 0xFU]); } else @@ -4026,12 +4038,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) hhcd->hc[ch_num & 0xFU].xfer_count += data_xfr; hhcd->hc[ch_num & 0xFU].state = HC_XFRC; hhcd->hc[ch_num & 0xFU].urb_state = URB_DONE; - - if ((hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_BULK) || - (hhcd->hc[ch_num & 0xFU].ep_type == EP_TYPE_INTR)) - { - hhcd->hc[ch_num & 0xFU].toggle_out ^= 1U; - } } } /* Check NACK Response */ @@ -4046,7 +4052,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* Get Channel register value */ WregCh = *(__IO uint32_t *)(&(hhcd->Instance->CHEP0R) + phy_chnum); - /*clear NAK status*/ + /* Clear NAK status */ WregCh &= ~USB_CHEP_NAK & USB_CHEP_REG_MASK; /* Update channel register Value */ @@ -4137,13 +4143,13 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) /* Host Port State */ hhcd->HostState = HCD_HCD_STATE_DISCONNECTED; - /* clear all allocated virtual channel */ + /* Clear all allocated virtual channel */ HAL_HCD_ClearPhyChannel(hhcd); /* Reset the PMA current pointer */ (void)HAL_HCD_PMAReset(hhcd); - /* reset Ep0 Pma allocation state */ + /* Reset Ep0 Pma allocation state */ hhcd->ep0_PmaAllocState = 0U; /* Disconnection Callback */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c index 31582a2dd2..3b1a2ee7f0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c @@ -3458,6 +3458,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __IO uint32_t I2C_Trials = 0UL; + HAL_StatusTypeDef status = HAL_OK; + FlagStatus tmp1; FlagStatus tmp2; @@ -3515,37 +3517,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + } while (I2C_Trials < Trials); /* Update I2C state */ @@ -7624,15 +7653,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c index 6f6cac1fcc..b1c88eacc7 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_iwdg.c @@ -137,7 +137,8 @@ The timeout value is multiplied by 1000 to be converted in milliseconds. LSI startup time is also considered here by adding LSI_STARTUP_TIME converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT (((1UL * 1024UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) +#define HAL_IWDG_DEFAULT_TIMEOUT (((1UL * 1024UL * 1000UL) / (LSI_VALUE / 128U)) + \ + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_EWU | IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c index 184b4d0fca..821aaea8fa 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_lptim.c @@ -387,10 +387,10 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) { if ((hlptim->Instance == LPTIM3) || (hlptim->Instance == LPTIM4)) { - /* Check LPTIM3 Input1 source */ + /* Check LPTIM Input1 source */ assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); - /* Configure LPTIM3 Input1 source */ + /* Configure LPTIM Input1 source */ hlptim->Instance->CFGR2 = hlptim->Init.Input1Source; } } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c index 634c867967..3ea9aaea58 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc.c @@ -2120,7 +2120,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U); @@ -2271,7 +2271,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp * will contain the MMC card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); @@ -4302,7 +4302,6 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 * @brief Used to select the partition. * @param hmmc: Pointer to MMC handle * @param Partition: Partition type - * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition) @@ -4683,7 +4682,7 @@ HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, /** * @brief Allows to get the value of write counter within the RPMB partition. * @param hmmc: Pointer to MMC handle - * @param Nonce: pointer to the value of nonce (16 bytes) + * @param pNonce: pointer to the value of nonce (16 bytes) * @param Timeout: Specify timeout value * @retval write counter value. */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc_ex.c index 79589f4b74..77b66947a1 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mmc_ex.c @@ -217,7 +217,8 @@ HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_DisableCircularMode(MMC_DMALinkedListT * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, + const MMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -326,7 +327,8 @@ HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_ReadBlocks(MMC_HandleTypeDef *hmmc, MM * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, MMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_MMCEx_DMALinkedList_WriteBlocks(MMC_HandleTypeDef *hmmc, + const MMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c index 1a4a2077a6..86b77be302 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c @@ -1148,7 +1148,8 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1241,7 +1242,8 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -2708,8 +2710,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * } /********************* Deactivation of other instance *********************/ - if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || - (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || + if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || + ((cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && (cfg->DQSPort != 0U)) || + (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c index 45621b97bb..bed0c62be8 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c @@ -1055,7 +1055,6 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) __HAL_PCD_DISABLE(hpcd); (void)USB_DevDisconnect(hpcd->Instance); - #if defined (USB_OTG_FS) || defined (USB_OTG_HS) (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -1486,7 +1485,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && - ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; @@ -1951,7 +1950,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1966,7 +1965,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; #if defined (USB_OTG_FS) || defined (USB_OTG_HS) @@ -2642,7 +2641,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); } } @@ -2763,7 +2761,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -2839,7 +2837,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2871,11 +2869,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2925,6 +2923,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2936,10 +2940,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2970,7 +2976,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2998,6 +3004,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -3010,10 +3022,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -3043,7 +3057,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -3052,13 +3066,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; } #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - #endif /* defined (USB_DRD_FS) */ /** @@ -3066,7 +3079,6 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c index a4a9f4ac5d..1e61af7f86 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c @@ -484,7 +484,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } } - /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -519,7 +518,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) return HAL_OK; } - #endif /* defined (USB_DRD_FS) */ /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c index 5618ef5b0b..b93ae117da 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pka.c @@ -1121,11 +1121,18 @@ void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) */ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); + } + else + { + return HAL_ERROR; + } } /** @@ -1136,11 +1143,18 @@ HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTy */ HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in) { - /* Set input parameter in PKA RAM */ - PKA_PointCheck_Set(hpka, in); + if ((in->pMontgomeryParam) != NULL) + { + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); - /* Start the operation */ - return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); + } + else + { + return HAL_ERROR; + } } /** diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c index a7a6fbda3e..29304a020b 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c @@ -594,7 +594,6 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry) * clear of pending events before. * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and * no clear of pending event before. - * @note In System STOP mode, all I/O pins keep the same state as in Run mode. * @retval None. */ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry) @@ -836,6 +835,13 @@ __weak void HAL_PWR_PVDCallback(void) * privileged access. * @note Privilege attribute for nsecure items can be managed by a secure * privileged access or by a nsecure privileged access. + * @note As the privileged attributes concern either all secure or all non-secure + * PWR resources accesses and not each PWR individual items access attribute, + * the application must ensure that the privilege access attribute configurations + * are coherent amongst the security level set on PWR individual items so not to + * overwrite a previous more restricted access rule (consider either all secure + * and/or all non-secure PWR resources accesses by privileged-only transactions + * or privileged and unprivileged transactions). * @param Item : Specifies the item(s) to set attributes on. * This parameter can be a combination of @ref PWR_Items. * @param Attributes : Specifies the available attribute(s). @@ -933,6 +939,8 @@ HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; } #else + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); /* Get Non-Secure privileges attribute */ attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; #endif /* __ARM_FEATURE_CMSE */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c index 0dc86b9ab2..15b487453a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c @@ -864,7 +864,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN1); } } @@ -877,7 +877,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN2); } } @@ -890,7 +890,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN3); } } @@ -903,7 +903,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN4); } } @@ -916,7 +916,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN5); } } @@ -929,7 +929,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN6); } } @@ -942,7 +942,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN7); } } @@ -955,7 +955,7 @@ void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8); /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); + HAL_PWREx_S3WUCallback(PWR_WAKEUP_PIN8); } } } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c index 1b47d2327d..0d84eb060c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c @@ -1657,6 +1657,10 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { GPIO_InitTypeDef gpio_initstruct; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(RCC_MCOx); + /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); @@ -2062,6 +2066,14 @@ __weak void HAL_RCC_CSSCallback(void) /** * @brief Configure the RCC item attribute(s). * @note Available attributes are to secure items and set RCC as privileged. + * @note As the privileged attributes concern either all secure or all + * non-secure RCC resources accesses and not each RCC individual items + * access attribute, the application must ensure that the privilege + * access attribute configurations are coherent amongst the security + * level set on RCC individual items so not to overwrite a previous + * more restricted access rule (consider either all secure and/or all + * non-secure RCC resources accesses by privileged-only transactions or + * privileged and unprivileged transactions). * @param Item Item(s) to set attributes on. * This parameter can be a one or a combination of @ref RCC_items * @param Attributes specifies the RCC secure/privilege attributes. @@ -2101,10 +2113,14 @@ void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes) /* Non-secure Privilege attribute */ case RCC_NSEC_PRIV: SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); break; /* Non-secure Non-Privilege attribute */ case RCC_NSEC_NPRIV: CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); break; #endif /* __ARM_FEATURE_CMSE */ default: @@ -2154,6 +2170,9 @@ HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut #else /* Get Non-Secure privileges attribute */ attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV; + /* Prevent unused argument(s) compilation warning */ + UNUSED(Item); + #endif /* __ARM_FEATURE_CMSE */ /* return value */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c index bfcbe13eee..eaa87eceab 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng.c @@ -197,8 +197,20 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Disable RNG */ __HAL_RNG_DISABLE(hrng); +#if defined(RNG_CR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->CR, RNG_CR_NIST_VALUE | RNG_CR_CONDRST | hrng->Init.ClockErrorDetection); +#else /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); +#endif /* RNG_CR_NIST_VALUE */ +#if defined(RNG_HTCR_NIST_VALUE) + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->HTCR, RNG_HTCR_NIST_VALUE); +#endif /* RNG_HTCR_NIST_VALUE */ +#if defined(RNG_NSCR_NIST_VALUE) + WRITE_REG(hrng->Instance->NSCR, RNG_NSCR_NIST_VALUE); +#endif /* RNG_NSCR_NIST_VALUE */ /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); @@ -238,7 +250,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { hrng->State = HAL_RNG_STATE_ERROR; hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; @@ -641,6 +653,8 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t status = RNG_RecoverSeedError(hrng); if (status == HAL_ERROR) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; return status; } } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c index adeb1b3bbb..1458006886 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rng_ex.c @@ -30,7 +30,7 @@ #if defined(RNG) -/** @addtogroup RNG_Ex +/** @addtogroup RNGEx * @brief RNG Extended HAL module driver. * @{ */ @@ -41,7 +41,7 @@ /* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Private_Constants +/** @addtogroup RNGEx_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -53,11 +53,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions * @{ */ -/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim @@ -309,6 +309,11 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /* sequence to fully recover from a seed error */ status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + } } else { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c index 96999b17f9..236e5ca5ee 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rtc.c @@ -362,39 +362,45 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Check if the calendar has been not initialized */ + /* Check whether the calendar needs to be initialized */ if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) { - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - if (status == HAL_OK) + /* Check that the RTC mode is not 'binary only' */ + if (__HAL_RTC_GET_BINARY_MODE(hrtc) != RTC_BINARY_ONLY) { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); - /* Set RTC_CR register */ - SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); - - /* Configure the RTC PRER */ - WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the Binary mode */ - MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); if (status == HAL_OK) { - MODIFY_REG(RTC->CR, \ - RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ - hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + + /* Configure the Binary mode */ + MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + + if (status == HAL_OK) + { + MODIFY_REG(RTC->CR, \ + RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + } } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } } else { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c index 594045c1b8..af08837d2c 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd.c @@ -2111,7 +2111,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); @@ -2327,7 +2327,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT * will contain the SD card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd_ex.c index 0e44eb5a60..b18160c1ec 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sd_ex.c @@ -196,7 +196,8 @@ HAL_StatusTypeDef HAL_SDEx_DMALinkedList_DisableCircularMode(SD_DMALinkedListTyp * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SDMMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, + const SDMMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -290,7 +291,8 @@ HAL_StatusTypeDef HAL_SDEx_DMALinkedList_ReadBlocks(SD_HandleTypeDef *hsd, SDMMC * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, SDMMC_DMALinkedListTypeDef *pLinkedList, +HAL_StatusTypeDef HAL_SDEx_DMALinkedList_WriteBlocks(SD_HandleTypeDef *hsd, + const SDMMC_DMALinkedListTypeDef *pLinkedList, uint32_t BlockAdd, uint32_t NumberOfBlocks) { diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c index a2d420733b..83b3e70525 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_sdio.c @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2024 STMicroelectronics. + * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -86,6 +86,9 @@ (#) Configure the SDIO Card speed mode by the API : HAL_SDIO_SetSpeedMode(). + (#) To custumize the SDIO Init card function for the enumeration card sequence, you can register a user callback + function by calling the HAL_SDIO_RegisterIdentifyCardCallback before the HAL_SDIO_Init() function. + *** SDIO Card Read operation *** ============================== [..] @@ -311,6 +314,7 @@ HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) { SDIO_InitTypeDef Init; uint32_t sdmmc_clk; + uint8_t data; /* Check the parameters */ assert_param(hsdio != NULL); @@ -375,12 +379,31 @@ HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); - if (SDIO_InitCard(hsdio) != HAL_OK) + if (hsdio->SDIO_IdentifyCard == NULL) + { + hsdio->SDIO_IdentifyCard = SDIO_InitCard; + } + /* SDIO enumeration sequence */ + if (hsdio->SDIO_IdentifyCard(hsdio) != HAL_OK) { hsdio->State = HAL_SDIO_STATE_RESET; return HAL_ERROR; } + /* Configure the SDMMC user parameters */ + Init.ClockEdge = hsdio->Init.ClockEdge; + Init.ClockPowerSave = hsdio->Init.ClockPowerSave; + Init.BusWide = hsdio->Init.BusWide; + Init.HardwareFlowControl = hsdio->Init.HardwareFlowControl; + Init.ClockDiv = hsdio->Init.ClockDiv; + (void)SDMMC_Init(hsdio->Instance, Init); + + data = (hsdio->Init.BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U; + if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK) + { + return HAL_ERROR; + } + hsdio->Context = SDIO_CONTEXT_NONE; hsdio->State = HAL_SDIO_STATE_READY; @@ -1937,6 +1960,7 @@ HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDI return status; } +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ #if (USE_SDIO_TRANSCEIVER != 0U) /** @@ -1999,7 +2023,30 @@ HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsd } #endif /* USE_SDIO_TRANSCEIVER */ -#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ +/** + * @brief Register a User SDIO Identification Callback + * @param hsdio: Pointer to SDIO handle + * @param pCallback: pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_IdentifyCardCallbackTypeDef pCallback) +{ + /* Check the parameters */ + assert_param(hsdio != NULL); + assert_param(pCallback != NULL); + + if (pCallback == NULL) + { + /* Update the error code */ + hsdio->ErrorCode |= HAL_SDIO_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + hsdio->SDIO_IdentifyCard = pCallback; + + return HAL_OK; +} /** * @} */ @@ -2403,7 +2450,7 @@ HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio) * @param Callback io IRQ handler. */ HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction, - HAL_SDIO_IOFunction_CallbackTypeDef Callback) + HAL_SDIO_IOFunction_CallbackTypeDef pCallback) { /* Check the parameters */ assert_param(hsdio != NULL); @@ -2415,7 +2462,7 @@ HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, return HAL_ERROR; } - hsdio->SDIO_IOFunction_Callback[(uint32_t)IOFunction] = Callback; + hsdio->SDIO_IOFunction_Callback[(uint32_t)IOFunction] = pCallback; hsdio->IOFunctionMask |= (1U << (uint8_t)IOFunction); return HAL_OK; @@ -2444,7 +2491,6 @@ static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio) uint16_t sdio_rca = 1U; uint32_t Resp4; uint32_t nbr_of_func; - SDMMC_InitTypeDef Init; /* Identify card operating voltage */ errorstate = SDMMC_CmdGoIdleState(hsdio->Instance); @@ -2514,21 +2560,6 @@ static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio) return HAL_ERROR; } - /* Configure the SDMMC user parameters */ - Init.ClockEdge = hsdio->Init.ClockEdge; - Init.ClockPowerSave = hsdio->Init.ClockPowerSave; - Init.BusWide = hsdio->Init.BusWide; - Init.HardwareFlowControl = hsdio->Init.HardwareFlowControl; - Init.ClockDiv = hsdio->Init.ClockDiv; - (void)SDMMC_Init(hsdio->Instance, Init); - - uint8_t data = (hsdio->Init.BusWide == HAL_SDIO_4_WIRES_MODE) ? 2U : 0U; - - if (SDIO_WriteDirect(hsdio, SDMMC_SDIO_CCCR4_SD_BYTE3, HAL_SDIO_WRITE_ONLY, SDIO_FUNCTION_0, &data) != HAL_OK) - { - return HAL_ERROR; - } - return HAL_OK; } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c index dc0b588985..cb904b2194 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_smartcard.c @@ -828,6 +828,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, co /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -935,6 +943,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; @@ -1001,6 +1017,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->TxXferCount = Size; hsmartcard->TxISR = NULL; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); @@ -1094,6 +1118,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->RxXferSize = Size; hsmartcard->RxXferCount = Size; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the USART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Configure Rx interrupt processing */ if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess)) { @@ -1395,8 +1427,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1420,8 +1454,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1492,8 +1528,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1558,8 +1596,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1657,9 +1697,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable DMA Tx at UART level */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1681,8 +1723,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmarx != NULL) { @@ -1771,8 +1815,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmatx != NULL) { @@ -1869,8 +1915,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ if (hsmartcard->hdmarx != NULL) { @@ -2052,8 +2100,10 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Rx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Rx channel */ if (hsmartcard->hdmarx != NULL) { @@ -2106,8 +2156,10 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the SMARTCARD DMA Tx request if enabled */ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { +#if !defined(USART_DMAREQUESTS_SW_WA) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Abort the SMARTCARD DMA Tx channel */ if (hsmartcard->hdmatx != NULL) { @@ -2744,10 +2796,12 @@ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); hsmartcard->TxXferCount = 0U; +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the SMARTCARD associated USART CR3 register */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Enable the SMARTCARD Transmit Complete Interrupt */ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); } @@ -2767,10 +2821,12 @@ static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); +#if !defined(USART_DMAREQUESTS_SW_WA) /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the SMARTCARD associated USART CR3 register */ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); +#endif /* USART_DMAREQUESTS_SW_WA */ /* At end of Rx process, restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c index 58e66052ef..86f93668e9 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c @@ -240,6 +240,9 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { uint32_t crc_length; uint32_t packet_length; +#if (USE_SPI_CRC != 0UL) + uint32_t crc_poly_msb_mask; +#endif /* USE_SPI_CRC */ /* Check the SPI handle allocation */ if (hspi == NULL) @@ -327,6 +330,9 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) crc_length = hspi->Init.CRCLength; } + /* Verify the correctness of polynom size */ + assert_param(IS_SPI_CRC_POLYNOMIAL_SIZE(hspi->Init.CRCPolynomial, crc_length)); + /* Verify that the CRC Length is higher than DataSize */ if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos)) { @@ -444,15 +450,21 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) || ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT))) { + /* Set SPI_CR1_CRC33_17 bit */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); + /* Write CRC polynomial in SPI Register */ + WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); } else { + /* Clear SPI_CR1_CRC33_17 bit */ CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); - } - /* Write CRC polynomial in SPI Register */ - WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); + /* Write CRC polynomial and set MSB bit at 1 in SPI Register */ + /* Set MSB is mandatory for a correct CRC computation */ + crc_poly_msb_mask = (0x1UL << ((crc_length >> SPI_CFG1_CRCSIZE_Pos) + 0x1U)); + WRITE_REG(hspi->Instance->CRCPOLY, (hspi->Init.CRCPolynomial) | crc_poly_msb_mask); + } } #endif /* USE_SPI_CRC */ @@ -834,6 +846,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1050,6 +1072,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint32_t temp_sr_reg; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); #if defined (__GNUC__) __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ @@ -1057,6 +1082,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1115,13 +1150,32 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { - /* Check the RXWNE/EOT flag */ - if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); hspi->pRxBuffPtr += sizeof(uint32_t); hspi->RxXferCount--; } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + } + /* Check if transfer is locked because of a suspend */ + else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP)) + { + /* Verify suspend is triggered by hardware and not software */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + } + } else { /* Timeout management */ @@ -1147,6 +1201,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + /* Check the RXP flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { @@ -1158,6 +1215,43 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->pRxBuffPtr += sizeof(uint16_t); hspi->RxXferCount--; } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + /* Check if transfer is locked because of a suspend */ + else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP)) + { + /* Verify suspend is triggered by hardware and not software */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + } + } else { /* Timeout management */ @@ -1183,6 +1277,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + /* Check the RXP flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { @@ -1190,6 +1287,35 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->pRxBuffPtr += sizeof(uint8_t); hspi->RxXferCount--; } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + /* Check if transfer is locked because of a suspend */ + else if (HAL_IS_BIT_SET(temp_sr_reg, SPI_SR_SUSP)) + { + /* Verify suspend is triggered by hardware and not software */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + } + } else { /* Timeout management */ @@ -1260,12 +1386,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t uint32_t tickstart; uint32_t fifo_length; + uint32_t temp_sr_reg; uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1341,28 +1480,44 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check RXWNE/EOT flag */ - if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL)) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount --; - initial_RxXferCount = hspi->RxXferCount; - } + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + if (initial_RxXferCount > 0UL) { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - /* Unlock the process */ - __HAL_UNLOCK(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1388,32 +1543,70 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check the RXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + if (initial_RxXferCount > 0UL) { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1432,28 +1625,58 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t initial_TxXferCount = hspi->TxXferCount; } - /* Check the RXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + if (initial_RxXferCount > 0UL) { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; - /* Unlock the process */ - __HAL_UNLOCK(hspi); + /* Unlock the process */ + __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } + } } } } @@ -1495,6 +1718,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pD /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if ((pData == NULL) || (Size == 0UL)) { return HAL_ERROR; @@ -1579,6 +1812,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1674,6 +1917,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1790,6 +2043,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *p /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -1976,6 +2239,15 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } if (hspi->State != HAL_SPI_STATE_READY) { @@ -2166,6 +2438,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Check transfer size parameter */ + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_TRANSFER_SIZE(Size)); + } + else + { + assert_param(IS_SPI_TRANSFER_SIZE(Size)); + } + if (hspi->State != HAL_SPI_STATE_READY) { return HAL_BUSY; @@ -2200,9 +2482,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); /* Packing mode management is enabled by the DMA settings */ - if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && \ + ((hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) || \ + (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD)) && \ (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ - ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && \ + ((hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE) || \ + (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE)))) { /* Restriction the DMA data received is not allowed in this mode */ /* Unlock the process */ @@ -2609,6 +2895,15 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized before any call to DMA Abort functions */ + if (hspi->hdmarx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */ + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + } + if (hspi->hdmatx != NULL) { if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c index e46eb95022..e26b02892a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c @@ -57,7 +57,6 @@ data transfers. (#) SPIEx function: - (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_EnableLockConfiguration() (++) HAL_SPIEx_ConfigureUnderrun() diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c index 97eadff426..48d7aa5653 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c @@ -7280,8 +7280,6 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - TIMx->CR1 = tmpcr1; - /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; @@ -7294,16 +7292,15 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure TIMx->RCR = Structure->RepetitionCounter; } + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ - if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - { - /* Clear the update flag */ - CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - } + TIMx->CR1 = tmpcr1; } /** @@ -7428,7 +7425,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; - } if (IS_TIM_BREAK_INSTANCE(TIMx)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c index afe917be16..186beac392 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c @@ -872,7 +872,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -1149,17 +1149,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann (+) Stop the Complementary PWM and disable interrupts. (+) Start the Complementary PWM and enable DMA transfers. (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - @endverbatim * @{ */ @@ -1403,7 +1392,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the TIM Break interrupt (only if no more channel is active) */ tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) { __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); } @@ -2199,6 +2188,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); @@ -2215,15 +2205,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); - - /* Set BREAK AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { @@ -2231,20 +2213,13 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); - - /* Set BREAK2 AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); - } + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); } /* Set TIMx_BDTR */ @@ -2268,7 +2243,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - { HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; @@ -2703,7 +2677,6 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B } break; } - case TIM_BREAKINPUT_BRK2: { /* Check initial conditions */ @@ -3177,7 +3150,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim) */ /** - * @brief Hall commutation changed callback in non-blocking mode + * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3191,7 +3164,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) */ } /** - * @brief Hall commutation changed half complete callback in non-blocking mode + * @brief Commutation half complete callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3206,7 +3179,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break detection callback in non-blocking mode + * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ @@ -3221,7 +3194,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) } /** - * @brief Hall Break2 detection callback in non blocking mode + * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ @@ -3461,6 +3434,11 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } else { /* nothing to do */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c index e1a10962ca..0281da35c2 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c @@ -721,7 +721,6 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID @@ -846,7 +845,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID @@ -1444,6 +1442,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; +#if defined(USART_DMAREQUESTS_SW_WA) + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + +#endif /* USART_DMAREQUESTS_SW_WA */ if (huart->hdmatx != NULL) { /* Set the UART DMA transfer complete callback */ @@ -1506,9 +1509,11 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } } +#if !defined(USART_DMAREQUESTS_SW_WA) /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); +#endif /* USART_DMAREQUESTS_SW_WA */ /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -2577,6 +2582,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -3919,7 +3946,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -4591,6 +4617,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } @@ -4755,6 +4782,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c index 9118d79228..e276ee185f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c @@ -555,7 +555,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) /* Disable UART */ __HAL_UART_DISABLE(huart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; @@ -705,6 +705,14 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p return HAL_ERROR; } +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; @@ -824,6 +832,14 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t return HAL_ERROR; } +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->RxEventType = HAL_UART_RXEVENT_TC; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c index 0d77c727ea..3793fb1b0a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart.c @@ -144,7 +144,7 @@ */ /** @defgroup USART USART - * @brief HAL USART Synchronous module driver + * @brief HAL USART Synchronous SPI module driver * @{ */ @@ -227,8 +227,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + in synchronous SPI master/slave mode. + (+) For the synchronous SPI mode only these parameters can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit @@ -240,7 +240,7 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous SPI configuration procedure (details for the procedure are available in reference manual). @endverbatim @@ -318,7 +318,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) return HAL_ERROR; } - /* In Synchronous mode, the following bits must be kept cleared: + /* In Synchronous SPI mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register. */ @@ -659,11 +659,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART synchronous + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI data transfers. - [..] The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). + [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input). [..] @@ -3224,7 +3223,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c index 83112cccfe..c050547f02 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_usart_ex.c @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) /* Disable USART */ __HAL_USART_DISABLE(husart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c index 3b52eeb352..f7dcc45345 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_xspi.c @@ -1282,7 +1282,7 @@ HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusC * @note This function is used only in Indirect Write Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout) +HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout) { HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); @@ -1302,7 +1302,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, uint8_t *const pD /* Configure counters and size */ hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; hxspi->XferSize = hxspi->XferCount; - hxspi->pBuffPtr = pData; + hxspi->pBuffPtr = (uint8_t *)pData; /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -1444,7 +1444,7 @@ HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pDa * @note This function is used only in Indirect Write Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; @@ -1462,7 +1462,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const /* Configure counters and size */ hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; hxspi->XferSize = hxspi->XferCount; - hxspi->pBuffPtr = pData; + hxspi->pBuffPtr = (uint8_t *)pData; /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -1565,7 +1565,7 @@ HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const * of data and the fifo threshold should be aligned on word * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; uint32_t data_size = hxspi->Instance->DLR + 1U; @@ -1644,7 +1644,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *cons if (status == HAL_OK) { hxspi->XferSize = hxspi->XferCount; - hxspi->pBuffPtr = pData; + hxspi->pBuffPtr = (uint8_t *)pData; /* Configure CR register with functional mode as indirect write */ MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); @@ -2542,12 +2542,10 @@ HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSP HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) { HAL_StatusTypeDef status = HAL_OK; - uint32_t state; uint32_t tickstart = HAL_GetTick(); - /* Check if the state is in one of the busy or configured states */ - state = hxspi->State; - if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + /* Check if the state is not in reset state */ + if (hxspi->State != HAL_XSPI_STATE_RESET) { /* Check if the DMA is enabled */ if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) @@ -2620,11 +2618,9 @@ HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) { HAL_StatusTypeDef status = HAL_OK; - uint32_t state; - /* Check if the state is in one of the busy or configured states */ - state = hxspi->State; - if (((state & XSPI_BUSY_STATE_MASK) != 0U) || ((state & XSPI_CFG_STATE_MASK) != 0U)) + /* Check if the state is not in reset state */ + if (hxspi->State != HAL_XSPI_STATE_RESET) { /* Disable all interrupts */ HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HAL_XSPI_IT_TE)); @@ -3586,7 +3582,7 @@ static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxsp { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hxspi->State = HAL_XSPI_STATE_ERROR; + hxspi->State = HAL_XSPI_STATE_READY; hxspi->ErrorCode |= HAL_XSPI_ERROR_TIMEOUT; return HAL_TIMEOUT; @@ -3662,6 +3658,14 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC /* Configure the CCR register with DQS and SIOO modes */ *ccr_reg = (pCmd->DQSMode | pCmd->SIOOMode); + /* Workaround for Erratasheet: Memory-mapped write error response when DQS output is disabled */ + if (pCmd->OperationType == HAL_XSPI_OPTYPE_WRITE_CFG) + { + /* When doing memory-mapped writes, set the DQSE bit of the OCTOSPI_WCCR register, + even for memories that have no DQS pin. */ + SET_BIT((*ccr_reg), XSPI_CCR_DQSE); + } + if (pCmd->AlternateBytesMode != HAL_XSPI_ALT_BYTES_NONE) { /* Configure the ABR register with alternate bytes value */ @@ -3684,6 +3688,25 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC } } + /* Configure SSHIFT register to handle SDR/DTR data transfer */ + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE) + { + /* Deactivate sample shifting when receiving data in DTR mode (DDTR=1) */ + CLEAR_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); + } + else if (hxspi->Init.SampleShifting == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE) + { + /* Configure sample shifting */ + SET_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); + } + else + { + /* Do nothing */ + } + } + if (pCmd->InstructionMode != HAL_XSPI_INSTRUCTION_NONE) { if (pCmd->AddressMode != HAL_XSPI_ADDRESS_NONE) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c index 5b074bcdac..1ff6e2e7f2 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c @@ -875,9 +875,8 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode)); assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection)); } - - /* Check node type */ - if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE) + /* Check non 2D addressing settings */ + if (DMA_InitNodeStruct->NodeType != LL_DMA_LPDMA_LINEAR_NODE) { assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength)); assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength)); @@ -1133,6 +1132,11 @@ uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DM pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2)); } } + else + { + /* Reset of the CLLR of the node being created */ + pNode->LinkRegisters[reg_counter] = 0U; + } return (uint32_t)SUCCESS; } diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmac.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmac.c index efc43f5848..19e0f767ac 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmac.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_fmac.c @@ -113,8 +113,6 @@ ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx) return (status); } - - /** * @} */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c index 1b0a5d9547..183caeaf49 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_opamp.c @@ -64,7 +64,7 @@ /* compatibility with other STM32 families. */ #define IS_LL_OPAMP_INPUT_NONINVERTING(__OPAMPX__, __INPUT_NONINVERTING__) \ ( ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_IO0) \ - || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINV_DAC1_CH1) \ + || ((__INPUT_NONINVERTING__) == LL_OPAMP_INPUT_NONINVERT_DAC) \ ) /* Note: Comparator non-inverting inputs parameters are the same on all */ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rng.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rng.c index 468f19d98c..398fa82ccf 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rng.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_rng.c @@ -110,7 +110,7 @@ ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content * - ERROR: not applicable */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct) { /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c index 2aea608e21..03636ed13f 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_sdmmc.c @@ -349,7 +349,7 @@ uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx) * the configuration information for the SDMMC command * @retval HAL status */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command) { uint32_t tmpreg = 0; @@ -417,7 +417,7 @@ uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response) * that contains the configuration information for the SDMMC data. * @retval HAL status */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data) +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data) { uint32_t tmpreg = 0; @@ -1849,7 +1849,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) * @param pNodeConf: Pointer to configuration parameters for new node to add. * @retval Error status */ -uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, SDMMC_DMALinkNodeConfTypeDef *pNodeConf) +uint32_t SDMMC_DMALinkedList_BuildNode(SDMMC_DMALinkNodeTypeDef *pNode, const SDMMC_DMALinkNodeConfTypeDef *pNodeConf) { if ((pNode == NULL) || (pNodeConf == NULL)) diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c index 43623683e8..3fed68ca5d 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_tim.c @@ -748,6 +748,8 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ @@ -760,8 +762,6 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *T MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); @@ -815,8 +815,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); @@ -844,8 +842,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); @@ -894,8 +894,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); @@ -923,8 +921,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); @@ -973,8 +973,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); /* Disable the Channel 3: Reset the CC3E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); @@ -1002,8 +1000,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); @@ -1052,8 +1052,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); /* Disable the Channel 4: Reset the CC4E Bit */ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); @@ -1081,8 +1079,10 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM if (IS_TIM_BREAK_INSTANCE(TIMx)) { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); /* Set the complementary output Polarity */ MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U); @@ -1357,7 +1357,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - /* Select the Polarity and set the CC2E Bit */ + /* Select the Polarity and set the CC4E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c index 66ed62f8cd..a7148bdac3 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c @@ -112,7 +112,7 @@ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) * the configuration information for the UCPD peripheral. * @retval An ErrorStatus enumeration value. (Return always SUCCESS) */ -ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct) +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct) { /* Check the ucpd Instance UCPDx*/ assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c index 4c841c9349..1ffe57c1f6 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c @@ -794,17 +794,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef } else { - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); + } } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - if (ep->type == EP_TYPE_ISOC) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); - } } if (dma == 1U) @@ -2604,6 +2604,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -2708,7 +2712,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -2810,9 +2814,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -2844,19 +2848,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -2865,15 +2875,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -2884,18 +2892,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -2939,26 +2937,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } @@ -3397,7 +3392,14 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, } /* Clear device address, Endpoint number and Low Speed Endpoint fields */ - wChRegVal &= ~(USB_CHEP_DEVADDR | USB_CHEP_ADDR | USB_CHEP_LSEP); + wChRegVal &= ~(USB_CHEP_DEVADDR | + USB_CHEP_ADDR | + USB_CHEP_LSEP | + USB_CHEP_NAK | + USB_CHEP_KIND | + USB_CHEP_ERRTX | + USB_CHEP_ERRRX | + (0xFU << 27)); /* Set device address and Endpoint number associated to the channel */ wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) | @@ -3446,6 +3448,18 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) if (hc->doublebuffer == 0U) { + if ((hc->ep_type == EP_TYPE_BULK) || + (hc->ep_type == EP_TYPE_INTR)) + { + USB_DRD_CLEAR_RX_DTOG(USBx, phy_ch_num); + + /* Set Data PID */ + if (hc->data_pid == HC_PID_DATA1) + { + USB_DRD_RX_DTOG(USBx, phy_ch_num); + } + } + /* Set RX buffer count */ USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); } @@ -3503,6 +3517,18 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) { USB_DRD_CHEP_TX_SETUP(USBx, phy_ch_num); } + + if ((hc->ep_type == EP_TYPE_BULK) || + (hc->ep_type == EP_TYPE_INTR)) + { + USB_DRD_CLEAR_TX_DTOG(USBx, phy_ch_num); + + /* Set Data PID */ + if (hc->data_pid == HC_PID_DATA1) + { + USB_DRD_TX_DTOG(USBx, phy_ch_num); + } + } } #if (USE_USB_DOUBLE_BUFFER == 1U) else if (hc->ep_type == EP_TYPE_BULK) diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index cee30061e2..6b5af8d613 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -17,7 +17,7 @@ * STM32L5: 1.0.6 * STM32MP1: 1.6.0 * STM32U0: 1.2.0 - * STM32U5: 1.6.0 + * STM32U5: 1.6.1 * STM32WB: 1.14.4 * STM32WBA: 1.5.0 * STM32WL: 1.3.0 From ad802bbd627c53d19467a1cfffabc397146fbdc8 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 9 Jan 2025 11:16:52 +0100 Subject: [PATCH 2/2] system(U5): update STM32U5xx CMSIS Drivers to v1.4.1 Included in STM32CubeU5 FW v1.7.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32U5xx/Include/stm32u535xx.h | 9 +- .../Device/ST/STM32U5xx/Include/stm32u545xx.h | 9 +- .../Device/ST/STM32U5xx/Include/stm32u575xx.h | 356 +++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u585xx.h | 356 +++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u595xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u599xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5a5xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5a9xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5f7xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5f9xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5g7xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5g9xx.h | 364 ++++++++++++------ .../Device/ST/STM32U5xx/Include/stm32u5xx.h | 10 +- .../Device/ST/STM32U5xx/Release_Notes.html | 38 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 15 files changed, 2427 insertions(+), 1265 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h index 4c1c81abc7..a26269d33a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h @@ -216,7 +216,7 @@ typedef enum /** @} */ /* End of group Configuration_of_CMSIS */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -4796,6 +4796,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ /* */ @@ -16168,7 +16171,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -20293,7 +20296,7 @@ typedef struct #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -4960,6 +4960,9 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) /******************************************************************************/ /* */ @@ -16720,7 +16723,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -20889,7 +20892,7 @@ typedef struct #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5198,6 +5198,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xA2B0U) +#define RNG_NSCR_NIST_VALUE (0x17CBBU) /******************************************************************************/ /* */ @@ -17682,7 +17686,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -20856,9 +20860,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -20894,6 +20916,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -20965,11 +20990,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -20995,11 +21026,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -21040,9 +21074,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -21084,9 +21118,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -21118,6 +21152,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -21136,6 +21173,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -21177,21 +21217,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -21215,9 +21270,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -21251,6 +21306,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -21272,9 +21330,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -21328,12 +21386,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -21372,19 +21433,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -21597,51 +21684,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -21700,7 +21787,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -21709,7 +21795,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -21717,7 +21802,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -21763,9 +21847,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -21805,10 +21889,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -21820,7 +21904,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -21834,19 +21917,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -21950,6 +22030,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -21979,9 +22062,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -22014,9 +22097,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -22025,14 +22108,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -22064,15 +22147,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -22090,6 +22170,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -22104,18 +22190,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -22125,22 +22229,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5411,6 +5411,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xA2B0U) +#define RNG_NSCR_NIST_VALUE (0x17CBBU) /******************************************************************************/ /* */ @@ -18292,7 +18296,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -21518,9 +21522,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -21556,6 +21578,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -21627,11 +21652,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -21657,11 +21688,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -21702,9 +21736,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -21746,9 +21780,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -21780,6 +21814,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -21798,6 +21835,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -21839,21 +21879,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -21877,9 +21932,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -21913,6 +21968,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -21934,9 +21992,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -21990,12 +22048,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -22034,19 +22095,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -22259,51 +22346,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -22362,7 +22449,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -22371,7 +22457,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -22379,7 +22464,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -22425,9 +22509,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -22467,10 +22551,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -22482,7 +22566,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -22496,19 +22579,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -22612,6 +22692,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -22641,9 +22724,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -22676,9 +22759,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -22687,14 +22770,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -22726,15 +22809,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -22752,6 +22832,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -22766,18 +22852,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -22787,22 +22891,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5443,6 +5443,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) /******************************************************************************/ /* */ @@ -18792,7 +18796,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -22154,9 +22158,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -22192,6 +22214,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -22263,11 +22288,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -22293,11 +22324,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -22338,9 +22372,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -22382,9 +22416,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -22416,6 +22450,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -22434,6 +22471,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -22475,21 +22515,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -22513,9 +22568,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -22549,6 +22604,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -22570,9 +22628,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -22626,12 +22684,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -22670,19 +22731,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -22847,7 +22934,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -22875,13 +22962,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -22907,51 +22994,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -23010,7 +23097,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -23019,7 +23105,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -23027,7 +23112,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -23073,9 +23157,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -23115,10 +23199,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -23130,7 +23214,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -23144,19 +23227,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -23260,6 +23340,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -23289,9 +23372,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -23324,9 +23407,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -23335,14 +23418,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -23374,15 +23457,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -23400,6 +23480,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -23414,18 +23500,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -23435,22 +23539,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5731,6 +5731,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) /******************************************************************************/ /* */ @@ -22566,7 +22570,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -25988,9 +25992,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -26026,6 +26048,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -26097,11 +26122,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -26127,11 +26158,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -26172,9 +26206,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -26216,9 +26250,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -26250,6 +26284,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -26268,6 +26305,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -26309,21 +26349,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -26347,9 +26402,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -26383,6 +26438,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -26404,9 +26462,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -26460,12 +26518,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -26504,19 +26565,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -26681,7 +26768,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -26709,13 +26796,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -26741,51 +26828,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -26844,7 +26931,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -26853,7 +26939,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -26861,7 +26946,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -26907,9 +26991,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -26949,10 +27033,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -26964,7 +27048,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -26978,19 +27061,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -27094,6 +27174,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -27123,9 +27206,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -27158,9 +27241,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -27169,14 +27252,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -27208,15 +27291,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -27234,6 +27314,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -27248,18 +27334,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -27269,22 +27373,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5656,6 +5656,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) /******************************************************************************/ /* */ @@ -19402,7 +19406,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -22816,9 +22820,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -22854,6 +22876,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -22925,11 +22950,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -22955,11 +22986,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -23000,9 +23034,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -23044,9 +23078,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -23078,6 +23112,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -23096,6 +23133,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -23137,21 +23177,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -23175,9 +23230,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -23211,6 +23266,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -23232,9 +23290,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -23288,12 +23346,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -23332,19 +23393,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -23509,7 +23596,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -23537,13 +23624,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -23569,51 +23656,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -23672,7 +23759,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -23681,7 +23767,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -23689,7 +23774,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -23735,9 +23819,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -23777,10 +23861,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -23792,7 +23876,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -23806,19 +23889,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -23922,6 +24002,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -23951,9 +24034,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -23986,9 +24069,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -23997,14 +24080,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -24036,15 +24119,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -24062,6 +24142,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -24076,18 +24162,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -24097,22 +24201,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5944,6 +5944,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) /******************************************************************************/ /* */ @@ -23176,7 +23180,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -26650,9 +26654,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -26688,6 +26710,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -26759,11 +26784,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -26789,11 +26820,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -26834,9 +26868,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -26878,9 +26912,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -26912,6 +26946,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -26930,6 +26967,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -26971,21 +27011,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -27009,9 +27064,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -27045,6 +27100,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -27066,9 +27124,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -27122,12 +27180,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -27166,19 +27227,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -27343,7 +27430,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -27371,13 +27458,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -27403,51 +27490,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -27506,7 +27593,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -27515,7 +27601,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -27523,7 +27608,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -27569,9 +27653,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -27611,10 +27695,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -27626,7 +27710,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -27640,19 +27723,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -27756,6 +27836,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -27785,9 +27868,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -27820,9 +27903,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -27831,14 +27914,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -27870,15 +27953,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -27896,6 +27976,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -27910,18 +27996,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -27931,22 +28035,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5739,6 +5739,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) /******************************************************************************/ /* */ @@ -20385,7 +20389,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -23835,9 +23839,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -23873,6 +23895,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -23944,11 +23969,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -23974,11 +24005,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -24019,9 +24053,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -24063,9 +24097,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -24097,6 +24131,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -24115,6 +24152,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -24156,21 +24196,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -24194,9 +24249,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -24230,6 +24285,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -24251,9 +24309,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -24307,12 +24365,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -24351,19 +24412,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -24528,7 +24615,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -24556,13 +24643,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -24588,51 +24675,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -24691,7 +24778,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -24700,7 +24786,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -24708,7 +24793,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -24754,9 +24838,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -24796,10 +24880,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -24811,7 +24895,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -24825,19 +24908,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -24941,6 +25021,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -24970,9 +25053,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -25005,9 +25088,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -25016,14 +25099,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -25055,15 +25138,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -25081,6 +25161,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -25095,18 +25181,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -25116,22 +25220,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5859,6 +5859,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) /******************************************************************************/ /* */ @@ -23526,7 +23530,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -26988,9 +26992,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -27026,6 +27048,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -27097,11 +27122,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -27127,11 +27158,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -27172,9 +27206,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -27216,9 +27250,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -27250,6 +27284,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -27268,6 +27305,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -27309,21 +27349,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -27347,9 +27402,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -27383,6 +27438,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -27404,9 +27462,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -27460,12 +27518,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -27504,19 +27565,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -27681,7 +27768,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -27709,13 +27796,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -27741,51 +27828,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -27844,7 +27931,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -27853,7 +27939,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -27861,7 +27946,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -27907,9 +27991,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -27949,10 +28033,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -27964,7 +28048,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -27978,19 +28061,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -28094,6 +28174,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -28123,9 +28206,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -28158,9 +28241,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -28169,14 +28252,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -28208,15 +28291,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -28234,6 +28314,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -28248,18 +28334,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -28269,22 +28373,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -5952,6 +5952,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) /******************************************************************************/ /* */ @@ -20995,7 +20999,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -24497,9 +24501,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -24535,6 +24557,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -24606,11 +24631,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -24636,11 +24667,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -24681,9 +24715,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -24725,9 +24759,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -24759,6 +24793,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -24777,6 +24814,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -24818,21 +24858,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -24856,9 +24911,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -24892,6 +24947,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -24913,9 +24971,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -24969,12 +25027,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -25013,19 +25074,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -25190,7 +25277,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -25218,13 +25305,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -25250,51 +25337,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -25353,7 +25440,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -25362,7 +25448,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -25370,7 +25455,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -25416,9 +25500,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -25458,10 +25542,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -25473,7 +25557,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -25487,19 +25570,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -25603,6 +25683,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -25632,9 +25715,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -25667,9 +25750,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -25678,14 +25761,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -25717,15 +25800,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -25743,6 +25823,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -25757,18 +25843,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -25778,22 +25882,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32u5xx.h" /*!< STM32U5xx System */ @@ -6072,6 +6072,10 @@ typedef struct #define RNG_HTCR_HTCFG_Pos (0U) #define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ #define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) /******************************************************************************/ /* */ @@ -24136,7 +24140,7 @@ typedef struct #define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ #define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk #define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) #define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk #define TAMP_CR3_ITAMP8NOER_Pos (7U) #define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ @@ -27650,9 +27654,27 @@ typedef struct #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ -#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) -#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ -#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURMOD_Pos (21U) +#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1U << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */ /******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) @@ -27688,6 +27710,9 @@ typedef struct #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1U << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ @@ -27759,11 +27784,17 @@ typedef struct #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ +#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U) +#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1U << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */ +#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ +#define USB_OTG_HFIR_RLDCTRL_Pos (16U) +#define USB_OTG_HFIR_RLDCTRL_Msk (0x1U << USB_OTG_HFIR_RLDCTRL_Pos) /*!< 0x00010000 */ +#define USB_OTG_HFIR_RLDCTRL USB_OTG_HFIR_RLDCTRL_Msk /*!< Reload control */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) @@ -27789,11 +27820,14 @@ typedef struct #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ +#define USB_OTG_DSTS_DEVLNSTS_Pos (22U) +#define USB_OTG_DSTS_DEVLNSTS_Msk (0x3U << USB_OTG_DSTS_DEVLNSTS_Pos) /*!< 0x00C00000 */ +#define USB_OTG_DSTS_DEVLNSTS USB_OTG_DSTS_DEVLNSTS_Msk /*!< Device line status */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ -#define USB_OTG_GAHBCFG_GINT_Pos (0U) -#define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ -#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_GINTMSK_Pos (0U) +#define USB_OTG_GAHBCFG_GINTMSK_Msk (0x1U << USB_OTG_GAHBCFG_GINTMSK_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINTMSK USB_OTG_GAHBCFG_GINTMSK_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ @@ -27834,9 +27868,9 @@ typedef struct #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ -#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) -#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_PHYLPC_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPC_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPC_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPC USB_OTG_GUSBCFG_PHYLPC_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ @@ -27878,9 +27912,9 @@ typedef struct #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ -#define USB_OTG_GRSTCTL_HSRST_Pos (1U) -#define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ -#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_PSRST_Pos (1U) +#define USB_OTG_GRSTCTL_PSRST_Msk (0x1U << USB_OTG_GRSTCTL_PSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_PSRST USB_OTG_GRSTCTL_PSRST_Msk /*!< Partial soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ @@ -27912,6 +27946,9 @@ typedef struct #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DIEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DIEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPMSK_AHBERRM USB_OTG_DIEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ @@ -27930,6 +27967,9 @@ typedef struct #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPMSK_NAKM_Pos (13U) +#define USB_OTG_DIEPMSK_NAKM_Msk (0x1U << USB_OTG_DIEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) @@ -27971,21 +28011,36 @@ typedef struct #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1U << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< AHB error mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_STSPHSRXM_Pos (5U) +#define USB_OTG_DOEPMSK_STSPHSRXM_Msk (0x1U << USB_OTG_DOEPMSK_STSPHSRXM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_STSPHSRXM USB_OTG_DOEPMSK_STSPHSRXM_Msk /*!< Status phase received for control write mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ -#define USB_OTG_DOEPMSK_OPEM_Pos (8U) -#define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ -#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_OUTPKTERRM_Pos (8U) +#define USB_OTG_DOEPMSK_OUTPKTERRM_Msk (0x1U << USB_OTG_DOEPMSK_OUTPKTERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OUTPKTERRM USB_OTG_DOEPMSK_OUTPKTERRM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1U << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKMSK_Pos (13U) +#define USB_OTG_DOEPMSK_NAKMSK_Msk (0x1U << USB_OTG_DOEPMSK_NAKMSK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKMSK USB_OTG_DOEPMSK_NAKMSK_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETMSK_Pos (14U) +#define USB_OTG_DOEPMSK_NYETMSK_Msk (0x1U << USB_OTG_DOEPMSK_NYETMSK_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETMSK USB_OTG_DOEPMSK_NYETMSK_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) @@ -28009,9 +28064,9 @@ typedef struct #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ -#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) -#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ -#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_GONAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_GONAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GONAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_GONAKEFF USB_OTG_GINTSTS_GONAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ @@ -28045,6 +28100,9 @@ typedef struct #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ @@ -28066,9 +28124,9 @@ typedef struct #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ -#define USB_OTG_GINTSTS_WKUINT_Pos (31U) -#define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ -#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ +#define USB_OTG_GINTSTS_WKUPINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUPINT_Msk (0x1U << USB_OTG_GINTSTS_WKUPINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUPINT USB_OTG_GINTSTS_WKUPINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) @@ -28122,12 +28180,15 @@ typedef struct #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ -#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Pos)/*!< 0x00200000 */ +#define USB_OTG_GINTMSK_IPXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDETM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1U << USB_OTG_GINTMSK_RSTDETM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ @@ -28166,19 +28227,45 @@ typedef struct #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ +/******************** Bit definition for USB_OTG_GRXSTSR register ********************/ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSR_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSR_EPNUM_CHNUM USB_OTG_GRXSTSR_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ +#define USB_OTG_GRXSTSR_BCNT_Pos (4U) +#define USB_OTG_GRXSTSR_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSR_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSR_BCNT USB_OTG_GRXSTSR_BCNT_Msk /*!< Byte count */ +#define USB_OTG_GRXSTSR_DPID_Pos (15U) +#define USB_OTG_GRXSTSR_DPID_Msk (0x3U << USB_OTG_GRXSTSR_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSR_DPID USB_OTG_GRXSTSR_DPID_Msk /*!< Data PID */ +#define USB_OTG_GRXSTSR_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSR_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSR_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSR_PKTSTS USB_OTG_GRXSTSR_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSR_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSR_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSR_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSR_FRMNUM USB_OTG_GRXSTSR_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSR_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSR_STSPHST_Msk (0x1U << USB_OTG_GRXSTSR_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSR_STSPHST USB_OTG_GRXSTSR_STSPHST_Msk /*!< Status phase start */ + /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ -#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) -#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM_CHNUM USB_OTG_GRXSTSP_EPNUM_CHNUM_Msk /*!< Endpoint/Channel number */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< Byte count */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< Data PID */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_GRXSTSP_FRMNUM_Pos (21U) +#define USB_OTG_GRXSTSP_FRMNUM_Msk (0xFU << USB_OTG_GRXSTSP_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_GRXSTSP_FRMNUM USB_OTG_GRXSTSP_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_GRXSTSP_STSPHST_Pos (27U) +#define USB_OTG_GRXSTSP_STSPHST_Msk (0x1U << USB_OTG_GRXSTSP_STSPHST_Pos) /*!< 0x08000000 */ +#define USB_OTG_GRXSTSP_STSPHST USB_OTG_GRXSTSP_STSPHST_Msk /*!< Status phase start */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) @@ -28343,7 +28430,7 @@ typedef struct #define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */ #define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */ #define USB_OTG_GCCFG_FSVMINUS_Pos (2U) -#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_FSVMINUS_Msk (0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */ #define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */ #define USB_OTG_GCCFG_SESSVLD_Pos (3U) #define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */ @@ -28371,13 +28458,13 @@ typedef struct #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (PD) mode enable */ #define USB_OTG_GCCFG_VBVALOVAL_Pos (23U) #define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */ -#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */ +#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 PHY input */ #define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) #define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */ -#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */ +#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 PHY input override */ #define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) #define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */ -#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of femtoPHY pulldown resistors, used when ID PAD is disabled */ +#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables of PHY pulldown resistors, used when ID PAD is disabled */ /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) @@ -28403,51 +28490,51 @@ typedef struct #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ -#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) -#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ -#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) -#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ -#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ -#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) -#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ -#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ -#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) -#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ -#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ -#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) -#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ -#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ -#define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) -#define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ -#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ -#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) -#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ -#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ -#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) -#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ -#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ -#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) -#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ -#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ -#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) -#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ -#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ -#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) -#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ -#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ -#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) -#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ -#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_BESL_Pos (2U) -#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ -#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ -#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) -#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ -#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /* Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) @@ -28506,7 +28593,6 @@ typedef struct #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ - #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ @@ -28515,7 +28601,6 @@ typedef struct #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ - #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ @@ -28523,7 +28608,6 @@ typedef struct #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ - #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ @@ -28569,9 +28653,9 @@ typedef struct #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ -#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) -#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ -#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFSIZ_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFSIZ_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFSIZ USB_OTG_HPTXFSIZ_PTXFSIZ_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) @@ -28611,10 +28695,10 @@ typedef struct #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SD1PID_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -28626,7 +28710,6 @@ typedef struct #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ - #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ @@ -28640,19 +28723,16 @@ typedef struct #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ - #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ - -#define USB_OTG_HCCHAR_MC_Pos (20U) -#define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ -#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ -#define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ -#define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ - +#define USB_OTG_HCCHAR_MCNT_Pos (20U) +#define USB_OTG_HCCHAR_MCNT_Msk (0x3U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MCNT USB_OTG_HCCHAR_MCNT_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MCNT_0 (0x1U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MCNT_1 (0x2U << USB_OTG_HCCHAR_MCNT_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ @@ -28756,6 +28836,9 @@ typedef struct #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1U << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ @@ -28785,9 +28868,9 @@ typedef struct #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ -#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) -#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ -#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_AHBERRM_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERRM_Msk (0x1U << USB_OTG_HCINTMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERRM USB_OTG_HCINTMSK_AHBERRM_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ @@ -28820,9 +28903,9 @@ typedef struct #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) -#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MCNT USB_OTG_DIEPTSIZ_MCNT_Msk /*!< Multi count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) @@ -28831,14 +28914,14 @@ typedef struct #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_HCTSIZ_DOPING_Pos (31U) -#define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ -#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCTSIZ_DOPNG_Pos (31U) +#define USB_OTG_HCTSIZ_DOPNG_Msk (0x1U << USB_OTG_HCTSIZ_DOPNG_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPNG USB_OTG_HCTSIZ_DOPNG_Msk /*!< Do PING */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) @@ -28870,15 +28953,12 @@ typedef struct #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DOEPCTL_DPID_EONUM_Pos (16U) +#define USB_OTG_DOEPCTL_DPID_EONUM_Msk (0x1U << USB_OTG_DOEPCTL_DPID_EONUM_Pos) /*!< 0x00010000 */ +#define USB_OTG_DOEPCTL_DPID_EONUM USB_OTG_DOEPCTL_DPID_EONUM_Msk /*!< Endpoint data PID */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ -#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ -#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) -#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ @@ -28896,6 +28976,12 @@ typedef struct #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID/Set even frame */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos (29U) +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD1PID_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPCTL_SD1PID_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM_Msk /*!< Set DATA1 PID/Set odd frame */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ @@ -28910,18 +28996,36 @@ typedef struct #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DOEPINT_AHBERR_Pos (2U) +#define USB_OTG_DOEPINT_AHBERR_Msk (0x1U << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ +#define USB_OTG_DOEPINT_STSPHSRX_Pos (5U) +#define USB_OTG_DOEPINT_STSPHSRX_Msk (0x1U << USB_OTG_DOEPINT_STSPHSRX_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPINT_STSPHSRX USB_OTG_DOEPINT_STSPHSRX_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ +#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) +#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1U << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ +#define USB_OTG_DOEPINT_BERR_Pos (12U) +#define USB_OTG_DOEPINT_BERR_Msk (0x1U << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DOEPINT_NAK_Pos (13U) +#define USB_OTG_DOEPINT_NAK_Msk (0x1U << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK input */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ +#define USB_OTG_DOEPINT_STPKTRX_Pos (15U) +#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1U << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ +#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup packet received */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) @@ -28931,22 +29035,32 @@ typedef struct #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) -#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ -#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ -#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_Pos (29U) +#define USB_OTG_DOEPTSIZ_RXDPID_Msk (0x3U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID USB_OTG_DOEPTSIZ_RXDPID_Msk /*!< SETUP packet count */ +#define USB_OTG_DOEPTSIZ_RXDPID_0 (0x1U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_DOEPTSIZ_RXDPID_1 (0x2U << USB_OTG_DOEPTSIZ_RXDPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ -#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) -#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ -#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ -#define USB_OTG_PCGCCTL_GATECLK_Pos (1U) -#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ -#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!Release Notes for  STM32U5xx C

    Update History

    - +

    Main Changes

    +
      +
    • General updates to fix known defects and implementation enhancements.
      • +
    • Fix TAMP_CR3_ITAMP7NOER bit definition to be aligned with reference manual.
      • +
    • Add missing USB_OTG_GINTSTS_RSTDET bit definition.
      • +
    • Align USB OTG bit definition with reference manual.
      • +
    +

    Backward Compatibility

    +
      +
    • N/A
      • +
    +
    +
    +
    + +
    +

    Main Changes

    CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

    • Add Bits definition for RNG_NSCR register for RNG noise source control
      • @@ -45,7 +61,7 @@

      Main Changes

    • Fix wrong declaration of g_pfnVectors size in GCC startup_stm32u5XXxx.s files
    • Update linker files to properly mark sections readonly for GCC12
    -

    Backward Compatibility

    +

    Backward Compatibility

    • N/A
    @@ -54,12 +70,12 @@

    Backward Compatibility

    -

    Main Changes

    +

    Main Changes

    CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

    • Update STM32U5A5xx devices list with STM32U5A5QII3Q under “stm32u5xx.h” file
    -

    Backward Compatibility

    +

    Backward Compatibility

    • N/A
    @@ -68,7 +84,7 @@

    Backward Compatibility

    -

    Main Changes

    +

    Main Changes

    CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

    • Support of new STM32U5F9xx, STM32U5G9xx, STM32U5F7xx and STM32U5G7xx devices: @@ -78,7 +94,7 @@

      Main Changes

    • Add linker files for EWARM and STM32CubeIDE toolchains of STM32U5F9xx/STM32U5G9xx/STM32U5F7xx/STM32U5G7xx devices
    -

    Backward Compatibility

    +

    Backward Compatibility

    • N/A
    @@ -87,7 +103,7 @@

    Backward Compatibility

    -

    Main Changes

    +

    Main Changes

    CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

    • Support of stm32u535xx and stm32u545xx devices: @@ -140,7 +156,7 @@

      Main Changes

    • Rename ADC4_PW_VREFSECSMP to ADC4_PWRR_VREFSECSMP
    -

    Backward Compatibility

    +

    Backward Compatibility

    • N/A
    @@ -149,7 +165,7 @@

    Backward Compatibility

    -

    Main Changes

    +

    Main Changes

    • CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
        @@ -179,7 +195,7 @@

        Main Changes

        -

        Main Changes

        +

        Main Changes

        • Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define
        • Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define
          • @@ -191,7 +207,7 @@

          Main Changes

          -

          Main Changes

          +

          Main Changes

          • First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
          diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 0e3e0ae7c6..c2b839afcd 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -17,7 +17,7 @@ * STM32L5: 1.0.6 * STM32MP1: 1.6.0 * STM32U0: 1.2.0 - * STM32U5: 1.4.0 + * STM32U5: 1.4.1 * STM32WB: 1.12.2 * STM32WBA: 1.5.0 * STM32WL: 1.2.0